Re: [Intel-gfx] [PATCH] drm/i915/skl: Enabling PSR2 SU with frame sync

On Saturday 21 March 2015 02:50 AM, Vivi, Rodrigo wrote: On Fri, 2015-03-20 at 11:27 +0530, Sonika Jindal wrote: We make use of HW tracking for Selective update region and enable frame sync on sink. We use hardware's hardcoded data values for frame sync and GTC. Before enabling HW tracking for

Re: [Intel-gfx] [PATCH v2 5/9] drm/i915: Pass primary plane size to .update_primary_plane()

Looks good to me. Reviewed-by: Sonika Jindal On Thursday 19 March 2015 07:58 PM, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä In preparation to movable/resizeable primary planes pass the clipped plane size to .update_primary_plane(). v2: Pass src size too and use it appropriatel

Re: [Intel-gfx] [PATCH] Add Dmesg Triage Feature: further triage i-g-t kmsg log to reduce result noise resulted from piglit dmesg defect

Sure. Thanks ! Best Regards Ethan, Gao -Original Message- From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter Sent: Friday, March 20, 2015 6:30 PM To: Gao, Ethan Cc: Lespiau, Damien; intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH] Add Dmesg Tria

Re: [Intel-gfx] [PATCH] drm/i915: Reduce frequency of unspecific HSW reg debugging

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6023 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -4 272/272

Re: [Intel-gfx] [PATCH 04/19] drm/i915: Allocate a crtc_state also when the crtc is being disabled

> -Original Message- > From: Ander Conselvan De Oliveira [mailto:conselv...@gmail.com] > Sent: Friday, March 20, 2015 1:41 AM > To: Konduru, Chandra > Cc: intel-gfx@lists.freedesktop.org; Roper, Matthew D > Subject: Re: [PATCH 04/19] drm/i915: Allocate a crtc_state also when the crtc > i

Re: [Intel-gfx] [PATCH 03/19] drm/i915: Allocate a drm_atomic_state for the legacy modeset code

> -Original Message- > From: Ander Conselvan De Oliveira [mailto:conselv...@gmail.com] > Sent: Friday, March 20, 2015 12:00 AM > To: Konduru, Chandra > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [PATCH 03/19] drm/i915: Allocate a drm_atomic_state for the > legacy modeset code > >

Re: [Intel-gfx] [PATCH 16/19] drm/i915: Check lane sharing between pipes B & C using atomic state

> -Original Message- > From: Conselvan De Oliveira, Ander > Sent: Thursday, March 19, 2015 11:46 PM > To: Konduru, Chandra > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [PATCH 16/19] drm/i915: Check lane sharing between pipes B & C > using atomic state > > On Thu, 2015-03-19 at 20

Re: [Intel-gfx] [PATCH 17/19] drm/i915: Convert intel_pipe_will_have_type() to using atomic state

> -Original Message- > From: Ander Conselvan De Oliveira [mailto:conselv...@gmail.com] > Sent: Thursday, March 19, 2015 11:28 PM > To: Konduru, Chandra > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [PATCH 17/19] drm/i915: Convert intel_pipe_will_have_type() to > using atomic state

[Intel-gfx] [PATCH] drm/i915: Reduce frequency of unspecific HSW reg debugging

Delay the expensive read on the FPGA_DBG register from once per mmio to once per forcewake section when we are doing the general wellbeing check rather than the targetted error detection. This almost reduces the overhead of the debug facility (for example when submitting execlists) to zero whilst k

[Intel-gfx] [QA 2015/03/20 ww12] Testing report for `drm-intel-testing` (was: Updated -next)

Summary We covered the platforms: Skylake, Braswell, Broadwell, Haswell, Baytrail. In this circle, 10 new bugs have been found (89596 89594 89668