Not a new type exposed to userspace, just a standard way to create
them since between range, bitmask and enum there's 3 different ways to
pull out a boolean prop.
Also add the kerneldoc for the recently added new prop types, which
Rob forgot all about.
v2: Fixup kerneldoc, spotted by Rob.
Cc: Ro
There's a race window (small for hpd, 10s large for polled outputs)
where userspace could sneak in with an unrelated connnector probe
ioctl call and eat the hotplug event (since neither the hpd nor the
poll code see a state change).
To avoid this, check whether the connector state changes in all o
On some chipset we try to avoid possibly invasive output detection
methods (like load detect which can cause flickering elsewhere) in the
output poll work. Drivers could hence return unknown when a previous
full ->detect call returned a different state.
This change will generate a hotplug event, f
On Tue, Jan 20, 2015 at 1:46 PM, Chris Wilson wrote:
> On Tue, Jan 20, 2015 at 12:53:35PM -0800, Kristian Høgsberg wrote:
>> On Tue, Jan 20, 2015 at 12:42 AM, Daniel Vetter wrote:
>> > My idea for all this would have been to create a per-thread execbuf
>> > relocation context with a hashtab to ma
On Wednesday 21 January 2015 03:31 AM, Rodrigo Vivi wrote:
Hi Sonika, for the login screen my guess is that blinking cursor
waiting for password blocks psr entry.
But I thought it is the psr exit which is taking time which is why it
takes time
to actually show up the characters
For test cases
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5616
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -2 353/353
Thanks for the explanation.
As soon as I get my GT3 back I do another round, but with your
explanations and with the code I've re-reviewed I'm confident
everything is right.
Thanks,
Rodrigo.
On Tue, Jan 20, 2015 at 5:10 PM, Gong, Zhipeng wrote:
>
>
>> -Original Message-
>> From: Rodrigo
> -Original Message-
> From: Rodrigo Vivi [mailto:rodrigo.v...@gmail.com]
> Sent: Wednesday, January 21, 2015 5:49 AM
> To: Gong, Zhipeng
> Cc: intel-gfx; Vivi, Rodrigo
> Subject: Re: [Intel-gfx] [PATCH 3/3] test/gem_dummy_reloc_loop: add tests for
> dual bsd ring
>
> On Mon, Jan 12, 201
> -Original Message-
> From: Rodrigo Vivi [mailto:rodrigo.v...@gmail.com]
> Sent: Wednesday, January 21, 2015 5:44 AM
> To: Gong, Zhipeng
> Cc: intel-gfx; Vivi, Rodrigo
> Subject: Re: [Intel-gfx] [PATCH 2/3] tests/gem_exec_params: check the invalid
> flags for dual bsd ring
>
> I couldn'
This is the infrastructure for DPMS ported to the atomic world.
Fundamental changes compare to legacy DPMS are:
- No more per-connector dpms state, instead there's just one per each
display pipeline. So if you clone either you have to unclone first
if you only want to switch off one screen, or
Cursor plane updates have historically been fully async and mutliple
updates batched together for the next vsync. And userspace relies upon
that. Since implementing a full queue of async atomic updates is a bit
of work lets just recover the cursor specific behaviour with a hint
flag and some hacks
This builds on top of the crtc->active infrastructure to implement
legacy DPMS. My choice of semantics is somewhat arbitrary, but the
entire pipe is enabled as along as one output is still enabled.
Of course it also clamps everything that's not ON to OFF.
v2: Fix spelling in one comment.
Signed-
Not a new type exposed to userspace, just a standard way to create
them since between range, bitmask and enum there's 3 different ways to
pull out a boolean prop.
Also add the kerneldoc for the recently added new prop types, which
Rob forgot all about.
Cc: Rob Clark
Signed-off-by: Daniel Vetter
Hi Sonika, for the login screen my guess is that blinking cursor
waiting for password blocks psr entry.
For test cases I started the test case enhancement but my psr work is
paused this month for bug maintainance. Any help is welcome.
I was planing also to take a look on new Paulo's fbc tests case
Sorry for the delay.
Also for v5:
Reviewed-by: Rodrigo Vivi
On Tue, Jan 13, 2015 at 4:36 PM, Daniel Vetter wrote:
> On Tue, Jan 13, 2015 at 08:48:24AM +0800, Zhipeng Gong wrote:
>> On Skylake GT3 we have 2 Video Command Streamers (VCS), which is
>> asymmetrical.
>> For example, HEVC GPU comman
for v2 as well:
Reviewed-by: Rodrigo Vivi
On Mon, Jan 12, 2015 at 4:48 PM, Zhipeng Gong wrote:
> This will let userland only try to use the new ring
> when the appropriate kernel is present
>
> v2: change the number to be consistent with upstream (Zhipeng)
>
> Signed-off-by: Zhipeng Gong
> Revi
On Mon, Jan 12, 2015 at 4:50 PM, Zhipeng Gong wrote:
> Signed-off-by: Zhipeng Gong
> ---
> tests/gem_dummy_reloc_loop.c | 18 ++
> 1 file changed, 18 insertions(+)
>
> diff --git a/tests/gem_dummy_reloc_loop.c b/tests/gem_dummy_reloc_loop.c
> index 335700d..5e0a10a 100644
> --- a
On Tue, Jan 20, 2015 at 12:53:35PM -0800, Kristian Høgsberg wrote:
> On Tue, Jan 20, 2015 at 12:42 AM, Daniel Vetter wrote:
> > My idea for all this would have been to create a per-thread execbuf
> > relocation context with a hashtab to map buffer pointers to execbuf index
> > and a bunch of array
I couldn't save my GT3 here for new tests, but on GT2 it fails:
$ sudo ./gem_exec_params
IGT-Version: 1.9-g85bc151 (x86_64) (Linux: 3.19.0-rc4+ x86_64)
Subtest control: SUCCESS (0.000s)
Test requirement not met in function __real_main58, file gem_exec_params.c:108:
Test requirement: !gem_has_bsd(f
On Tue, Jan 20, 2015 at 12:42 AM, Daniel Vetter wrote:
> On Mon, Jan 19, 2015 at 09:45:35PM -0800, Kristian Høgsberg wrote:
>> On Fri, Jan 16, 2015 at 8:23 PM, Daniel Vetter wrote:
>> > On Fri, Jan 16, 2015 at 05:46:00PM -0800, Kristian Høgsberg wrote:
>> >> The I915_EXEC_NO_RELOC flag lets us te
It seems in the past we have BDW with PCH not been propperly identified
and we force it to be LPT and we were warning !IS_HASWELL on propper
identification.
Now that products are out there we are receiveing logs with this incorrect WARN.
And also according to local tests on all production BDW her
On 20 January 2015 at 04:05, Matt Roper wrote:
> A very simple testcase to exercise nuclear pageflip. We'll definitely
> want to expand upon this in the future, but this is a good starting
> point to sanity check nuclear pageflip support.
Just a few comments from an i-g-t perspective: could you
Thanks Jani.
Please ignore this patch... I'm testing the propper clean on BDWs here
and submiting another patch,
On Tue, Jan 20, 2015 at 12:51 AM, Jani Nikula
wrote:
> On Mon, 19 Jan 2015, Rodrigo Vivi wrote:
>> We have BDW that PCH might not be propperly identified and we force it
>> to be LPT
Commit 82460d972 ("drm/i915: Rework ppgtt init to no require an aliasing
ppgtt") introduced a regression on Broadwell, triggering the following
IOMMU fault at startup:
vgaarb: device changed decodes:
PCI::00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem
dmar: DRHD: handling fault stat
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Mika Kuoppala
> Sent: Tuesday, January 13, 2015 9:32 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 2/2] drm/i915: Rename unpin_count to pin_count
>
> We increase
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Mika Kuoppala
> Sent: Tuesday, January 13, 2015 9:32 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 1/2] drm/i915: Balance context pinning on reset
> cleanup
>
> W
Ville Syrjälä writes:
> On Fri, Jan 09, 2015 at 06:47:41PM +, Dave Gordon wrote:
>> On 08/01/15 13:40, Mika Kuoppala wrote:
>> > i915_gem_validate_context() will check the engine->state to see if it can
>> > submit into a ringbuffer. But when we are releasing the context we leave
>> > the
>>
We just allocated the intel_ringbuffer with kzalloc. There
is no chance of the ringbuf->obj being other than NULL
so remove the redudant check.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_lrc.c | 29 +
1 file changed, 13 insertions(+), 16 deletions(-)
commit 939fd762083f988be271da8c96398178daf9baf0
Author: Mika Kuoppala
Date: Thu Jan 30 19:04:44 2014 +0200
drm/i915: Get rid of acthd based guilty batch search
Failed to cleanup properly as it made the head obsolete.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.h | 3 -
On Tue, Jan 20, 2015 at 4:26 PM, Matt Roper wrote:
> On Tue, Jan 20, 2015 at 10:44:06AM +0100, Daniel Vetter wrote:
>> On Thu, Jan 15, 2015 at 06:34:19PM -0800, Matt Roper wrote:
>> > Runtime state that can be manipulated via properties should now go in
>> > intel_plane_state instead so that it ca
On Tue, Jan 20, 2015 at 10:44:06AM +0100, Daniel Vetter wrote:
> On Thu, Jan 15, 2015 at 06:34:19PM -0800, Matt Roper wrote:
> > Runtime state that can be manipulated via properties should now go in
> > intel_plane_state instead so that it can be tracked as part of an atomic
> > transaction.
> >
>
Chris Wilson writes:
> Currently we initialise the rings, add the first context switch to the
> ring and execute our golden state then enable (aliasing or full) ppgtt.
> However, as we enable ppgtt using direct MMIO but load the PD using
> MI_LRI, we end up executing the context switch and golden
On Tue, 20 Jan 2015, Daniel Vetter wrote:
> On Mon, Jan 19, 2015 at 07:57:46PM -0800, Matt Roper wrote:
>> +module_param_named(nuclear, i915.nuclear, bool, 0600);
>
> module_param_named_debug please.
ITYM module_param_named_unsafe.
BR,
Jani.
--
Jani Nikula, Intel Open Source Technology Center
crtc->base.primary->fb was used everywhere. Use fb to temporarily point
there and don't forget to assign fb to its final destination at the end.
v2: Rebase on top of misc changes (mask of DSPSURF, PAGE_ALIGN)
Reviewed-By: Tvrtko Ursulin
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/in
Follow up of:
http://lists.freedesktop.org/archives/intel-gfx/2015-January/058607.html
With the following changes:
- Rebased on top of today's -nightly
- Added the r-b tags
--
Damien
Damien Lespiau (9):
drm/i915: Change plane_config to store a tiling_mode
drm/i915: Use a common func
This vfunc and related structure are only used for fast boot, so let's
rename them to not take them as general purpose ones.
v2: Fix conflicts caused by the introduction of struct intel_crtc_state
Reviewed-By: Tvrtko Ursulin (v1)
Suggested-by: Daniel Vetter
Signed-off-by: Damien Lespiau
---
d
Universal planes have changed a bit the register organization.
v2: Rebase on top of the latest drm-intel-nightly
v3: Use PLANE_SIZE to retrieve the fb size (Tvrtko)
Don't use BUG() (Tvrtko)
v4: Use MISSING_CASE (Daniel)
Reviewed-By: Tvrtko Ursulin
Signed-off-by: Damien Lespiau
---
driver
v2: Fix conflict caused by the introduction of struct intel_crtc_state
Reviewed-By: Tvrtko Ursulin (v1)
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/driver
Rather than having "tiled" meaning "is it X-tiled?" convert the field to
explicitely store the tiling mode. The code doesn't have to change much
as 1 is conveniently I915_TILING_X.
This is to accommodate future changes around tiling modes and scannout
buffers.
v2: Rebase on top of Ander's "Make i
We may as well try to be consistent everywhere and know the pipes by
their name.
Reviewed-By: Tvrtko Ursulin
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_display.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_displ
crtc->plane can only be different from crtc->pipe pre-Gen4. Don't use it
in new-ish code.
Reviewed-By: Tvrtko Ursulin
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_display.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/
If we need to change the fb height constraints, it sounds like a good
idea to have to do it in one place only.
v2: v2: Rebase on top of Ander's "Make intel_crtc->config a pointer"
Reviewed-By: Tvrtko Ursulin (v1)
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_display.c | 19 +
We will have a skl_ version shortly!
Reviewed-By: Tvrtko Ursulin
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_display.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 58
From: Jesse Barnes
Per latest PM programming guide.
v2: the wrong flavour of the function updating the ring frequency was
called, leading to dead locks (Tvrtko)
v3: Add GEN6_RP_MEDIA_IS_GFX to RP_CONTROL (Imre, done by Damien)
v4: Rebase on top of Chris'/Mika's forcewake series
Reviewed-b
Follow up of:
http://lists.freedesktop.org/archives/intel-gfx/2015-January/058542.html
With the following changes:
- Rebased on top of Chris'/Mika's forcewake series.
- gen6_gt_force_wake_{get,put}() has been renamed
- patch 4/4 isn't necessary anymore as it's handled generically by the
From: Zhe Wang
Enable coarse power gating for Gen9. This feature allows render and
media engine to enter RC6 independently. Policies are configured
together with RC6. This feature will only be enabled when RC6 is
enabled.
v2: Rebase after Chris'/Mika's forcewake change (Damien)
Reviewed-by: Dam
v2: Use the new function, gen6_init_rps_frequencies() (Damien)
Reviewed-by: Mika Kuoppala (v1)
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_pm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b221105.
Is somebody working on enhancing the psr testcase?
-Sonika
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter
Sent: Tuesday, January 20, 2015 3:20 PM
To: Jindal, Sonika
Cc: Daniel Vetter; intel-gfx; Vivi, Rodrigo
Subject: Re: [Intel-gfx] [PATC
On Tue, Jan 20, 2015 at 11:14:22AM +0100, Daniel Vetter wrote:
> On Fri, Jan 16, 2015 at 06:07:26PM +, Damien Lespiau wrote:
> > v2: Use the new function, gen6_init_rps_frequencies() (Damien)
> >
> > Reviewed-by: Mika Kuoppala (v1)
> > Signed-off-by: Damien Lespiau
>
> First two patches mer
Hi,
On 01/19/2015 06:44 PM, Damien Lespiau wrote:
Follow up of
http://lists.freedesktop.org/archives/intel-gfx/2014-October/054391.html
with:
- Remarks from Tvrtko on patch 8 addressed.
- Suggestion from Daniel implemented (patch 9)
All looks fine to me, you can add my r-b to the seri
Universal planes have changed a bit the register organization.
v2: Rebase on top of the latest drm-intel-nightly
v3: Use PLANE_SIZE to retrieve the fb size (Tvrtko)
Don't use BUG() (Tvrtko)
v4: Use MISSING_CASE (Daniel)
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_display.
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5609
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 353/353
On Mon, Jan 12, 2015 at 10:21:58AM -0800, Rodrigo Vivi wrote:
> Use cmdline variable for interactive debug instead of env var.
>
> v2: Make interactive-debug domain optional and use "all" when not set.
>
> Signed-off-by: Rodrigo Vivi
I went ahead and applied this one to igt.
-Daniel
> ---
> l
On Mon, Jan 19, 2015 at 07:57:46PM -0800, Matt Roper wrote:
> We don't have full atomic modeset support yet, but the "nuclear
> pageflip" subset of functionality (i.e., plane operations only) should
> be ready. Allow the user to force atomic on for debug purposes, or for
> fixed-purpose embedded d
On Fri, Jan 16, 2015 at 06:07:26PM +, Damien Lespiau wrote:
> v2: Use the new function, gen6_init_rps_frequencies() (Damien)
>
> Reviewed-by: Mika Kuoppala (v1)
> Signed-off-by: Damien Lespiau
First two patches merged, later two have conflicts. Can you please rebase?
Also the big rework fr
On Fri, Jan 16, 2015 at 03:57:51PM +, Damien Lespiau wrote:
> From: Satheeshakrishna M
>
> Adding new power doamins for AUX controllers
>
> v2: Added new power domains in power_domain_str per Imre's comment
>
> v3: Added AUX power domains to older platforms
>
> v4: Rebase on top of POWER_D
On Fri, Jan 16, 2015 at 11:34:42AM +0200, Mika Kuoppala wrote:
> From: Mika Kuoppala
>
> There are multiple forcewake domains in newer architectures.
> Rename 'i915_gen6_forcewake_count_info' debugfs entry to
> 'i915_forcewake_domains' to reflect this.
>
> Signed-off-by: Mika Kuoppala
Entire s
On Fri, Jan 16, 2015 at 11:34:40AM +0200, Mika Kuoppala wrote:
> @@ -356,14 +356,21 @@ void intel_uncore_sanitize(struct drm_device *dev)
> intel_disable_gt_powersave(dev);
> }
>
> -/*
> - * Generally this is called implicitly by the register read function.
> However,
> - * if some sequen
On Tue, Jan 20, 2015 at 11:46:57AM +0200, Ville Syrjälä wrote:
> On Tue, Jan 20, 2015 at 11:33:22AM +0200, Ander Conselvan de Oliveira wrote:
> > On 01/20/2015 11:22 AM, Daniel Vetter wrote:
> > > On Mon, Jan 19, 2015 at 03:51:47PM +0200, Ander Conselvan de Oliveira
> > > wrote:
> > >> @@ -13346,6
On Mon, Jan 19, 2015 at 05:10:58PM +0530, sonika wrote:
>
> On Saturday 17 January 2015 09:54 AM, Daniel Vetter wrote:
> >On Fri, Jan 16, 2015 at 02:07:26PM +0530, Sonika Jindal wrote:
> >>Mainly taking care of some register offsets, otherwise things are similar to
> >>hsw. Also, programming ddi a
On Thu, Jan 15, 2015 at 06:34:22PM -0800, Matt Roper wrote:
> drm_plane_helper_{update,disable} are not specific to primary planes;
> fix some copy/paste summaries to avoid confusion.
>
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Matt Roper
Applied to my topic/atomic-core branch.
Tha
On Thu, Jan 15, 2015 at 06:34:21PM -0800, Matt Roper wrote:
> Add a transitional helper for planes' .set_property() entrypoint,
> similar to what we already have for .update_plane() and
> .disable_plane(). This allows drivers that are still in the process of
> transitioning to implement and exerci
On Tue, Jan 20, 2015 at 11:33:22AM +0200, Ander Conselvan de Oliveira wrote:
> On 01/20/2015 11:22 AM, Daniel Vetter wrote:
> > On Mon, Jan 19, 2015 at 03:51:47PM +0200, Ander Conselvan de Oliveira wrote:
> >> Otherwise setting the rotation property will cause the primary plane to
> >> be disabled,
On Thu, Jan 15, 2015 at 06:34:19PM -0800, Matt Roper wrote:
> Runtime state that can be manipulated via properties should now go in
> intel_plane_state instead so that it can be tracked as part of an atomic
> transaction.
>
> Signed-off-by: Matt Roper
Imo we should move this to drm_plane_state s
On Fri, Jan 16, 2015 at 09:48:31AM +, Daniel, Thomas wrote:
> > -Original Message-
> > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
> > Of Nick Hoath
> > Sent: Thursday, January 15, 2015 1:11 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: daniel.vet...@
On Fri, Jan 16, 2015 at 03:48:56PM -0800, Matt Roper wrote:
> On Thu, Jan 15, 2015 at 02:55:26PM +0200, Ander Conselvan de Oliveira wrote:
> > The previous patch changed the config field in intel_crtc to a pointer,
> > but to keep the mechanical changes (done with spatch) separate from the
> > new
On Mon, Jan 19, 2015 at 03:43:57PM +0200, Ander Conselvan de Oliveira wrote:
> This adds a test that does a suspend/resume cycle between configuring
> a plane and getting the crc value for the pipe. The intention is to
> test if the user requested stated is restored properly, instead of
> being clo
On 01/20/2015 11:22 AM, Daniel Vetter wrote:
On Mon, Jan 19, 2015 at 03:51:47PM +0200, Ander Conselvan de Oliveira wrote:
Otherwise setting the rotation property will cause the primary plane to
be disabled, caused by having a 0x0 initial value.
v2: Rebase on top of the move to plane helpers.
C
On 01/20/2015 11:22 AM, Daniel Vetter wrote:
On Mon, Jan 19, 2015 at 03:51:47PM +0200, Ander Conselvan de Oliveira wrote:
Otherwise setting the rotation property will cause the primary plane to
be disabled, caused by having a 0x0 initial value.
v2: Rebase on top of the move to plane helpers.
C
On Tue, Jan 20, 2015 at 09:50:36AM +0100, Daniel Vetter wrote:
> On Tue, Jan 20, 2015 at 08:54:58AM +0530, Deepak S wrote:
> >
> > On Monday 19 January 2015 05:20 PM, ville.syrj...@linux.intel.com wrote:
> > >From: Ville Syrjälä
> > >
> > >On VLV/CHV the media well rc6 residency gets reported sep
On Tue, Jan 20, 2015 at 08:45:50AM +0530, Deepak S wrote:
>
> On Monday 19 January 2015 05:20 PM, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > CherryViewA0_iGfx_BIOS_DRIVER_PUNIT_spec_y14w28d5 tells us not to enable
> > the RP down timeout interrupt, and says that the time
On Mon, Jan 19, 2015 at 03:51:47PM +0200, Ander Conselvan de Oliveira wrote:
> Otherwise setting the rotation property will cause the primary plane to
> be disabled, caused by having a 0x0 initial value.
>
> v2: Rebase on top of the move to plane helpers.
>
> Cc: sta...@vger.kernel.org
> Bugzilla
On Thu, Jan 15, 2015 at 03:16:35PM -0800, Rodrigo Vivi wrote:
> Great!
>
> Although I'd prefer at intel_drrs.c.. ;)
>
> Reviewed-by: Rodrigo Vivi
>
> On Fri, Jan 9, 2015 at 12:56 PM, Vandana Kannan
> wrote:
> > Adding an overview of DRRS in general and the implementation for eDP DRRS.
> > Also
On Thu, Jan 15, 2015 at 03:24:04PM -0800, Rodrigo Vivi wrote:
> I didn't get how it shows different rates if the i915_drrs_status only
> shows if panel supports or not.
>
> Maybe the debugfs file could contain more info for each crtc connect,
> crtc info, if panel connected there supports, if it i
On Tue, Jan 20, 2015 at 08:37:21AM +0530, Deepak S wrote:
>
> On Monday 19 January 2015 03:14 PM, Daniel Vetter wrote:
> >On Fri, Jan 16, 2015 at 08:42:16PM +0530, deepa...@linux.intel.com wrote:
> >>From: Deepak S
> >>
> >>Starting with Cherryview, devices may have a varying number of EU for
> >
On Mon, 19 Jan 2015, Rodrigo Vivi wrote:
> We have BDW that PCH might not be propperly identified and we force it
> to be LPT. However when we correctly identify it is LPT we
> incorrectly WARN that this isn't a Haswell. For now we have many
> platforms out there we still need to force LPT so let
On Tue, Jan 20, 2015 at 08:54:58AM +0530, Deepak S wrote:
>
> On Monday 19 January 2015 05:20 PM, ville.syrj...@linux.intel.com wrote:
> >From: Ville Syrjälä
> >
> >On VLV/CHV the media well rc6 residency gets reported separately
> >from the render well, so add another file to sysfs so that we ca
On Tue, Jan 20, 2015 at 01:17:10AM -0600, Larry Finger wrote:
> Hi,
>
> I just discovered almost 100 of the following entries in my log:
>
> [drm:intel_uncore_check_errors [i915]] *ERROR* Unclaimed register before
> interrupt
>
> Those were accumulated in about 12 hours of operation. I also hav
On Mon, Jan 19, 2015 at 09:45:35PM -0800, Kristian Høgsberg wrote:
> On Fri, Jan 16, 2015 at 8:23 PM, Daniel Vetter wrote:
> > On Fri, Jan 16, 2015 at 05:46:00PM -0800, Kristian Høgsberg wrote:
> >> The I915_EXEC_NO_RELOC flag lets us tell the kernel that the offset we
> >> provide in the validate
On Mon, Jan 19, 2015 at 09:58:55PM -0800, Kristian Høgsberg wrote:
> On Sat, Jan 17, 2015 at 1:49 AM, Chris Wilson
> wrote:
> > On Sat, Jan 17, 2015 at 05:23:59AM +0100, Daniel Vetter wrote:
> >> On Fri, Jan 16, 2015 at 05:46:00PM -0800, Kristian Høgsberg wrote:
> >> > The I915_EXEC_NO_RELOC flag
On Mon, Jan 19, 2015 at 06:27:49PM +, Damien Lespiau wrote:
> On Fri, Oct 31, 2014 at 11:38:34AM +, Tvrtko Ursulin wrote:
> > >+ default:
> > >+ BUG();
> >
> > As some other people I also dislike BUGs very much. WARN and put no fb on
> > screen instead?
>
> Sure, removed the BUG
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