On recent emulator GTT entry setup for aub dump needs mem type as
GTT_ENTRY instead of NONLOCAL. NONLOCAL would write data in main
memory space which is wrong with new memory layout. GTT_ENTRY write
would setup GTT memory pool and other required internal buffers. With
this I can run aub dump on lat
Taking rotation into account while checking the plane
and adjusting the sizes accordingly.
v2: Adding parameter in the callers in the same patch(Matt)
Removing unnecessary code and allowing scaling(Ville)
Signed-off-by: Sonika Jindal
---
drivers/gpu/drm/drm_plane_helper.c | 44 ++
This is an important optimization for avoiding read-after-write (RAW)
stalls in the HiZ buffer. Certain workloads would run very slowly with
HiZ enabled, but run much faster with the "hiz=false" driconf option.
With this patch, they run at full speed even with HiZ.
Increases performance in OglVSI
Found by reading the HIZ_CHICKEN documentation.
Improves performance in a HiZ microbenchmark by around 50%.
Improves performance in OglZBuffer by around 18%.
Thanks to Chris Wilson for helping me figure out where to put this.
Signed-off-by: Kenneth Graunke
Reviewed-by: Ville Syrjälä
---
drive
This is an important optimization for avoiding read-after-write (RAW)
stalls in the HiZ buffer. Certain workloads would run very slowly with
HiZ enabled, but run much faster with the "hiz=false" driconf option.
With this patch, they run at full speed even with HiZ.
Improves performance in OglVSIn
On Tuesday 13 January 2015 07:02 PM, Ville Syrjälä wrote:
On Tue, Jan 13, 2015 at 06:03:39PM +0530, Sonika Jindal wrote:
Taking rotation into account while checking the plane
and adjusting the sizes accordingly.
Signed-off-by: Sonika Jindal
---
drivers/gpu/drm/drm_plane_helper.c | 79
On Tuesday 13 January 2015 11:42 PM, Matt Roper wrote:
On Tue, Jan 13, 2015 at 06:03:38PM +0530, Sonika Jindal wrote:
This adds another parameter rotation to drm_plane_helper_check_update.
This will enable this function to do to size updations based upon the rotation
if any.
Updated the calls t
I believe we could start this re-org by moving it out to intel_drrs.c
renaming functions and adding entry docbook entry.
But anyway this patch is right and doesn't seem to change anything
that is already working so free free to use:
Reviewed-by: Rodrigo Vivi
I'll continue the reviews tomorrow a
On Tue, Jan 13, 2015 at 2:26 PM, Daniel Vetter wrote:
> On Tue, Jan 13, 2015 at 02:24:54PM +, R, Durgadoss wrote:
>> Hi Rodrigo,
>>
>> >-Original Message-
>> >From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
>> >Of Rodrigo Vivi
>> >Sent: Monday, January 12, 2
On Tue, Jan 13, 2015 at 08:48:24AM +0800, Zhipeng Gong wrote:
> On Skylake GT3 we have 2 Video Command Streamers (VCS), which is asymmetrical.
> For example, HEVC GPU commands can be only dispatched to VCS1 ring.
> But userspace has no control when using VCS1 or VCS2. This patch introduces
> a mech
On Tue, Jan 13, 2015 at 09:19:04PM +, O'Rourke, Tom wrote:
> >Sent: Sunday, January 11, 2015 7:48 PM
> >To: Widawsky, Benjamin
> >Cc: Intel GFX
> >Subject: Re: [Intel-gfx] [PATCH] [v2] intel_frequency: A tool to manipulate
> >Intel
> >GPU frequency
> >
> >On Sun, Jan 11, 2015 at 07:35:21PM -08
On Tue, Jan 13, 2015 at 02:24:54PM +, R, Durgadoss wrote:
> Hi Rodrigo,
>
> >-Original Message-
> >From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
> >Of Rodrigo Vivi
> >Sent: Monday, January 12, 2015 11:45 PM
> >To: intel-gfx@lists.freedesktop.org
> >Cc: Vivi
On Tue, Jan 13, 2015 at 01:24:12PM +0200, Ville Syrjälä wrote:
> On Tue, Jan 13, 2015 at 12:34:06AM +0100, Daniel Vetter wrote:
> > On Mon, Jan 12, 2015 at 05:36:52PM +0200, Ander Conselvan de Oliveira wrote:
> > > Otherwise setting the rotation property will cause the primary plane to
> > > be dis
On Tue, Jan 13, 2015 at 09:48:51AM +, Gore, Tim wrote:
>
>
> > -Original Message-
> > From: daniel.vet...@ffwll.ch [mailto:daniel.vet...@ffwll.ch] On Behalf Of
> > Daniel Vetter
> > Sent: Monday, January 12, 2015 11:26 PM
> > To: Gore, Tim
> > Cc: Gordon, David S; intel-gfx@lists.freede
On Tue, Jan 13, 2015 at 11:53:22AM +, Michel Thierry wrote:
> On 1/5/2015 2:45 PM, Daniel Vetter wrote:
> >Aside: Should we only allocate the scratch_pt for !aliasing?
> The next patch version will have the changes.
> About the scratch_pt, I'm not sure if it's a requirement in gen6/7 (to point
>Sent: Sunday, January 11, 2015 7:48 PM
>To: Widawsky, Benjamin
>Cc: Intel GFX
>Subject: Re: [Intel-gfx] [PATCH] [v2] intel_frequency: A tool to manipulate
>Intel
>GPU frequency
>
>On Sun, Jan 11, 2015 at 07:35:21PM -0800, Ben Widawsky wrote:
>> WARNING: very minimally tested
>>
>> In general you
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 354/354
On Tue, Jan 13, 2015 at 10:23:55PM +0200, Ville Syrjälä wrote:
> On Tue, Jan 13, 2015 at 01:32:52PM +, Chris Wilson wrote:
> > Currently we are hitting the WARN inside
> > i915_gem_object_set_cache_level() as we can now have an unbound object
> > in the GTT write domain (due to 43566dedde54f9 "
On Tue, Jan 13, 2015 at 01:32:52PM +, Chris Wilson wrote:
> Currently we are hitting the WARN inside
> i915_gem_object_set_cache_level() as we can now have an unbound object
> in the GTT write domain (due to 43566dedde54f9 "drm/i915: Broaden
> application of set-domain(GTT)"). To avoid the warn
On Mon, Jan 12, 2015 at 06:07:26PM -0800, Ben Widawsky wrote:
> On Mon, Jan 12, 2015 at 06:09:12PM +, Dave Gordon wrote:
> > On 12/01/15 18:02, Ben Widawsky wrote:
> > > On Mon, Jan 12, 2015 at 02:02:34PM +0200, Ville Syrjälä wrote:
> > >> On Sun, Jan 11, 2015 at 07:14:57PM -0800, Ben Widawsky
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 354/354
On Tue, Jan 13, 2015 at 06:03:38PM +0530, Sonika Jindal wrote:
> This adds another parameter rotation to drm_plane_helper_check_update.
> This will enable this function to do to size updations based upon the rotation
> if any.
> Updated the calls to this function in i915 and drm. Rockchip driver al
Description of the 'state' parameter for intel_plane_destroy_state() was
missing and the intel_atomic_plane.c file section heading did not match
drm.tmpl.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 354/354
On Tue, 13 Jan 2015, Chris Wilson wrote:
> Currently we are hitting the WARN inside
> i915_gem_object_set_cache_level() as we can now have an unbound object
> in the GTT write domain (due to 43566dedde54f9 "drm/i915: Broaden
> application of set-domain(GTT)"). To avoid the warning, we need to trac
On 01/13/2015 12:08 AM, Daniel Vetter wrote:
> On Fri, Jan 9, 2015 at 1:50 PM, Jani Nikula wrote:
>> I have a slightly uneasy feeling about handing out drm_panel pointers
>> (both from here and of_drm_find_panel) without refcounting. If the panel
>> driver gets removed, whoever called the find fun
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 354/354 3
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Rodrigo Vivi
>Sent: Monday, January 12, 2015 11:45 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Vivi, Rodrigo
>Subject: [Intel-gfx] [PATCH 8/9] drm/i915: PSR: respect vbt time for link
>tra
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Rodrigo Vivi
>Sent: Monday, January 12, 2015 11:45 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Vivi, Rodrigo
>Subject: [Intel-gfx] [PATCH 7/9] drm/i915: PSR VLV/CHV: let's respect
>link_st
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Rodrigo Vivi
>Sent: Monday, January 12, 2015 11:45 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Vivi, Rodrigo
>Subject: [Intel-gfx] [PATCH 6/9] drm/i915: PSR link standby at debugfs
>
>It is
Hi Rodrigo,
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Rodrigo Vivi
>Sent: Monday, January 12, 2015 11:45 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Vivi, Rodrigo
>Subject: [Intel-gfx] [PATCH 3/9] drm/i915: PSR HSW/BDW: Fix invert
Add a parameter for the size of the act_upon array in the parse function
since its size cannot be calculated with ARRAY_SIZE from just the
pointer.
Cc: Ben Widawsky
Signed-off-by: Thomas Wood
---
tools/intel_gpu_frequency.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --g
intel_gpu_frequency was added in commit 5fb26d1 (intel_gpu_frequency: A
tool to manipulate Intel GPU frequency), but wasn't added to .gitignore.
Cc: Ben Widawsky
Signed-off-by: Thomas Wood
---
tools/.gitignore | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/.gitignore b/tools/.gitigno
drm_open_any always returns a valid file descriptor, so there is no need
to check the return value.
Signed-off-by: Thomas Wood
---
lib/drmtest.c | 6 +++---
lib/igt.cocci | 14 ++
tests/gem_alive.c | 2 --
tests/gem_flink_race.c| 2 --
tests/gem
On Tue, Jan 13, 2015 at 06:03:39PM +0530, Sonika Jindal wrote:
> Taking rotation into account while checking the plane
> and adjusting the sizes accordingly.
>
> Signed-off-by: Sonika Jindal
> ---
> drivers/gpu/drm/drm_plane_helper.c | 79
> ++--
> include/drm/
Currently we are hitting the WARN inside
i915_gem_object_set_cache_level() as we can now have an unbound object
in the GTT write domain (due to 43566dedde54f9 "drm/i915: Broaden
application of set-domain(GTT)"). To avoid the warning, we need to track
when we elided the clflush on a cacheable object
Signed-off-by: Sonika Jindal
---
drivers/gpu/drm/i915/intel_display.c |6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index f40288f..d19ed4b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
This adds another parameter rotation to drm_plane_helper_check_update.
This will enable this function to do to size updations based upon the rotation
if any.
Updated the calls to this function in i915 and drm. Rockchip driver also needs
to be updated.
Sonika Jindal (2):
drm: Adding rotation to d
Taking rotation into account while checking the plane
and adjusting the sizes accordingly.
Signed-off-by: Sonika Jindal
---
drivers/gpu/drm/drm_plane_helper.c | 79 ++--
include/drm/drm_plane_helper.h |3 +-
2 files changed, 77 insertions(+), 5 deletions
On 1/5/2015 2:45 PM, Daniel Vetter wrote:
On Tue, Dec 23, 2014 at 05:16:17PM +, Michel Thierry wrote:
From: Ben Widawsky
This patch continues on the idea from the previous patch. From here on,
in the steady state, PDEs are all pointing to the scratch page table (as
recommended in the spec)
From: Ben Widawsky
The current code will both potentially print a WARN, and setup part of
the PPGTT structure. Neither of these harm the current code, it is
simply for clarity, and to perhaps prevent later bugs, or weird
debug messages.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry
This new patchset addresses most of the comments from v2. It still teardowns
pagetables (which I plan to ammend shortly), but I think there were already
enough changes to justify it.
For GEN8, it has also been extended to work in logical ring submission (lrc)
mode, as it will be the preferred mode
From: Ben Widawsky
As we move toward dynamic page table allocation, it becomes much easier
to manage our data structures if break do things less coarsely by
breaking up all of our actions into individual tasks. This makes the
code easier to write, read, and verify.
Aside from the dissection of
Logic ring contexts need to know the PDPs when they are populated. With
dynamic page table allocations, these PDPs may not exist yet.
Check if PDPs have been allocated and use the scratch page if they do
not exist yet.
Before submission, update the PDPs in the logic ring context as PDPs
have been
From: Ben Widawsky
Instead of implementing the full tracking + dynamic allocation, this
patch does a bit less than half of the work, by tracking and warning on
unexpected conditions. The tracking itself follows which PTEs within a
page table are currently being used for objects. The next patch wi
From: Ben Widawsky
The page directory freer is left here for now as it's still useful given
that GEN8 still preallocates. Once the allocation functions are broken
up into more discrete chunks, we'll follow suit and destroy this
leftover piece.
v2: Match trace_i915_va_teardown params
v3: Multiple
From: Ben Widawsky
Start using gen8_for_each_pde macro to allocate page tables.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 54 -
drivers/gpu/drm/i915/i915_gem_gtt.h | 10 +++
2 files changed, 39 i
From: Ben Widawsky
The problem is we're going to switch to a new context, which could be
the default context. The plan was to use restore inhibit, which would be
fine, except if we are using dynamic page tables (which we will). If we
use dynamic page tables and we don't load new page tables, the
From: Ben Widawsky
These values are never quite useful for dynamic allocations of the page
tables. Getting rid of them will help prevent later confusion.
v2: Updated to use unmap_and_free_pd functions.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2)
---
drivers/gpu/drm/i915/i9
Traces for page directories and tables allocation/destroy and map/unmap.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem.c | 2 +
drivers/gpu/drm/i915/i915_gem_gtt.c | 17 ++
drivers/gpu/drm/i915/i915_trace.h | 115
3 files change
From: Ben Widawsky
In gen8, 32b PPGTT has always had one "pdp" (it doesn't actually have
one, but it resembles having one). The #define was confusing as is, and
using "PDPE" is a much better description.
sed -i 's/GEN8_LEGACY_PDPS/GEN8_LEGACY_PDPES/' drivers/gpu/drm/i915/*.[ch]
It also matches
From: Ben Widawsky
Now that we don't need to trace num_pd_pages, we may as well kill all
need for the PPGTT structure in the alloc_page_directorys. This is very useful
for when we move to 48b addressing, and the PDP isn't the root of the
page table structure.
The param is replaced with drm_devic
From: Ben Widawsky
When we do dynamic page table allocations for gen8, we'll need to have
more control over how and when we map page tables, similar to gen6.
In particular, DMA mappings for page directories/tables occur at allocation
time.
This patch adds the functionality and calls it at init,
From: Ben Widawsky
When we move to dynamic page allocation, keeping page_directory and pagetabs as
separate structures will help to break actions into simpler tasks.
To help transition the code nicely there is some wasted space in gen6/7.
This will be ameliorated shortly.
Following the x86 page
From: Ben Widawsky
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 9d998ec..8f76990 100644
---
From: Ben Widawsky
Like with gen6/7, we can enable bitmap tracking with all the
preallocations to make sure things actually don't blow up.
v2: Rebased to match changes from previous patches.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2)
---
drivers/gpu/drm/i915/i915_gem_gtt.
From: Ben Widawsky
We have some fanciness coming up. This patch just breaks out the logic
of context switch skip, pd load pre, and pd load post.
v2: Use new functions to replace the logic right away (Daniel)
Cc: Daniel Vetter
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2)
---
From: Ben Widawsky
Therefore we can do it from our general init function. Eventually, I
hope to have a lot more commonality like this. It won't arrive yet, but
this was a nice easy one.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 6 ++---
From: Ben Widawsky
This finishes off the dynamic page tables allocations, in the legacy 3
level style that already exists. Most everything has already been setup
to this point, the patch finishes off the enabling by setting the
appropriate function pointers.
Zombie tracking:
This could be a sepa
From: Ben Widawsky
This patch continues on the idea from the previous patch. From here on,
in the steady state, PDEs are all pointing to the scratch page table (as
recommended in the spec). When an object is allocated in the VA range,
the code will determine if we need to allocate a page for the
From: Ben Widawsky
Start using gen8_for_each_pdpe macro to allocate the page directories.
v2: Rebased after s/free_pt_*/unmap_and_free_pt/ change.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 43 ++---
From: Ben Widawsky
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_trace.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_trace.h
b/drivers/gpu/drm/i915/i915_trace.h
index 6058a01..f004d3d 100644
--
From: Ben Widawsky
Move the remaining members over to the new page table structures.
This can be squashed with the previous commit if desire. The reasoning
is the same as that patch. I simply felt it is easier to review if split.
v2: In lrc: s/ppgtt->pd_dma_addr[i]/ppgtt->pdp.page_directory[i].
The next patch in the series will require it for alloc_pt_single.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 29 -
1 file changed, 16 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/
From: Ben Widawsky
This patch was formerly known as, "Force pd restore when PDEs change,
gen6-7." I had to change the name because it is needed for GEN8 too.
The real issue this is trying to solve is when a new object is mapped
into the current address space. The GPU does not snoop the new mappi
From: Ben Widawsky
One important part of this patch is we now write a scratch page
directory into any unused PDP descriptors. This matters for 2 reasons,
first, we're not allowed to just use 0, or an invalid pointer, and second,
we must wipe out any previous contents from the last context.
The l
On Mon, Jan 12, 2015 at 06:14:31AM -0800, Rodrigo Vivi wrote:
> This reverts commit 5a0afd4b78ec23f27f5d486ac3d102c2e8d66bd7.
>
> Although timeout mode allows higher residency it impact badly on performance.
> I believe while we don't have a way to balance between performance and
We do though. We
On Tue, Jan 13, 2015 at 12:34:06AM +0100, Daniel Vetter wrote:
> On Mon, Jan 12, 2015 at 05:36:52PM +0200, Ander Conselvan de Oliveira wrote:
> > Otherwise setting the rotation property will cause the primary plane to
> > be disabled, caused by having a 0x0 initial value.
> >
> > Cc: sta...@vger.ke
> -Original Message-
> From: daniel.vet...@ffwll.ch [mailto:daniel.vet...@ffwll.ch] On Behalf Of
> Daniel Vetter
> Sent: Monday, January 12, 2015 11:26 PM
> To: Gore, Tim
> Cc: Gordon, David S; intel-gfx@lists.freedesktop.org; Wood, Thomas
> Subject: Re: [Intel-gfx] [PATCH i-g-t] tests/ge
On Mon, Jan 12, 2015 at 04:46:12PM -0800, Sean V Kelley wrote:
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA1
>
>
>
> On 01/09/2015 04:21 AM, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > My BSW has a nasty problem where it generates tons of spurious hpd
> > interrupt
We pin when we submit to execlist queue. Balance
the pinning when the submitted queue is cleaned on reset.
Cc: Dave Gordon
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem.c | 4
drivers/gpu/drm/i915/intel_lrc.c | 1 +
2 files changed, 5 insertions(+)
diff --git a/drivers/g
We increase it when we pin, so for the casual reader
rename it to cause less confusion.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_lrc.c | 12 ++--
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i9
> -Original Message-
> From: Ander Conselvan de Oliveira [mailto:conselv...@gmail.com]
> Sent: Tuesday, January 13, 2015 4:34 PM
> To: Jani Nikula; He, Shuang; Gao, Ethan; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Initialize primary plane src/dst
> coords
On 01/13/2015 10:17 AM, Jani Nikula wrote:
>
> Ander, please see if these results make sense.
>
> BR,
> Jani.
>
> On Tue, 13 Jan 2015, shuang...@intel.com wrote:
>> Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
>> shuang...@intel.com)
>> -Summ
Ander, please see if these results make sense.
BR,
Jani.
On Tue, 13 Jan 2015, shuang...@intel.com wrote:
> Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
> shuang...@intel.com)
> -Summary-
> Platform
If QUIRK_PIPEA_FORCE is necessary, intel_sanitize_crtc() might trigger
a mode set. In that case, if pipe A is disabled and pipe B is mapped to
plane B, that mode set happens before the mapping is fixed. Due to the
wrong state, the call to disable pipe B disables plane A (which is
already disabled)
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