Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 354/354
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 354/354
This test just display a frame on screen, waits for 1 second to enter DRRS
and displays another frame to exit DRRS.
TODO:- Notify the user about which refresh rate was used at different stages.
Signed-off-by: Vandana Kannan
---
tests/Makefile.sources | 1 +
tests/kms_drrs.c | 225 +++
Definition of VLV RR switch bit and corresponding toggling in
set_drrs function.
Signed-off-by: Vandana Kannan
Signed-off-by: Uma Shankar
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_dp.c | 10 --
2 files changed, 9 insertions(+), 2 de
For Broadwell, there is one instance of Transcoder MN values per transcoder.
For dynamic switching between multiple refreshr rates, M/N values may be
reprogrammed on the fly. Link N programming triggers update of all data and
link M & N registers and the new M/N values will be used in the next fram
Adding an overview of DRRS in general and the implementation for eDP DRRS.
Also, describing the functions related to eDP DRRS.
Signed-off-by: Vandana Kannan
---
Documentation/DocBook/drm.tmpl | 11 +
drivers/gpu/drm/i915/intel_dp.c | 95 +
2 files cha
From: Durgadoss R
This patch enables eDP DRRS for CHV by adding the
required IS_CHERRYVIEW() checks.
CHV uses the same register bit as VLV.
[Vandana]: Since CHV has 2 sets of M_N registers, it will follow the same code
path as gen < 8. Added CHV check in dp_set_m_n()
Signed-off-by: Durgadoss R
This patch series inserts DRRS into frontbuffer tracking mechanism.
1. Previous submission for this feature was designed considering only eDP
DRRS. In this series, apart from following fb tracking, changes have been made
to make structures generic so that it can be of use to any other code
additio
Calls have been added to invalidate/flush DRRS whenever invalidate/flush is
called as part of frontbuffer tracking.
Apart from calls as a result of GEM tracking to fb invalidate/flush, a
call has been added to invalidate fb obj from crtc_page_flip as well. This
is to track busyness through flip cal
Calling enable/disable DRRS when enable/disable DDI are called.
These functions are responsible for setup of drrs data (in enable) and
reset of drrs (in disable).
has_drrs is true when downclock_mode is found and SEAMLESS_DRRS is set in
the VBT. A check has been added for has_drrs in these function
Adding a debugfs entry to determine if DRRS is supported or not
Signed-off-by: Vandana Kannan
---
drivers/gpu/drm/i915/i915_debugfs.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index e515aad..
Add DRRS work function to trigger a switch to low refresh rate when activity
is detected on screen.
Signed-off-by: Vandana Kannan
---
drivers/gpu/drm/i915/intel_dp.c | 36
1 file changed, 28 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/int
Earlier, DRRS structures were specific to eDP (used only in intel_dp).
Since DRRS can be extended to other internal display types
(if the panel supports multiple RR), modifying structures
to be part of drm_i915_private and have a provision to add display related
structs like intel_dp.
Also, alignin
On 08/01/15 13:40, Mika Kuoppala wrote:
> i915_gem_validate_context() will check the engine->state to see if it can
> submit into a ringbuffer. But when we are releasing the context we leave the
> engine state to a non null value. Thus after a successful hang recovery
> we might mistakenly submit t
If the batch buffer is too large to fit into the aperture and we need a
GTT mapping for relocations, we currently fail. This only applies to a
subset of machines for a subset of environments, quite undesirable. We
can simply check after failing to insert the batch into the GTT as to
whether we only
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -31 363/364
On 09/01/15 11:09, Daniel, Thomas wrote:
> A previous commit enabled execlists by default:
>
>commit 27401d126b5b ("drm/i915/bdw: Enable execlists by default where
> supported")
>
> This allowed routine testing of execlists which exposed a regression when
> resuming from suspend. The ca
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -31 363/364
Hi,
Daniel Vetter writes:
> Ok, I've merged this one, since that means you at least won't get an
> -EINVAL. But you can't yet enable the feature in mesa since it's still
> no-opped out. Let's hope that v3 actually starts granting rights (but
> please don't encode that in any merge mesa patch bef
Building with the attached random configuration file,
drivers/gpu/drm/i915/intel_display.c: In function ‘assert_pll’:
drivers/gpu/drm/i915/intel_display.c:1027:2: error: implicit
declaration of function ‘__WARN_printf’
[-Werror=implicit-function-declaration]
I915_STATE_WARN(cur_state != state,
This gets rid of some annoying warnings and allows GNU make to parallelise more
parts of a deb-pkg build. The message is ...
make[3]: warning: jobserver unavailable: using -j1. Add `+' to parent make
rule.
... so I've added the '+' as suggested.
Signed-off-by: Dave Gordon
---
scripts/package
On Fri, Jan 09, 2015 at 10:56:16AM +0800, Zhenyu Wang wrote:
> On 2014.12.18 12:12:33 -0600, jeff.mc...@intel.com wrote:
> > diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
> > index 15dd01d..be38adf 100644
> > --- a/include/drm/i915_drm.h
> > +++ b/include/drm/i915_drm.h
> > @@ -340,6
On Fri, Jan 09, 2015 at 04:41:33PM +0200, Jani Nikula wrote:
> On Fri, 09 Jan 2015, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > intel_hpd_irq_handler() walks the passed in hpd[] array assuming it
> > contains HPD_NUM_PINS elements. Currently that's not true as we don't
> >
On Fri, 09 Jan 2015, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> 915 doens't support hotplug at all, so we shouldn't try to pretend
> otherwise in the SDVO code.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_sdvo.c | 3 +++
>
On Fri, 09 Jan 2015, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> If we determine that a specific port is eDP, don't register the HDMI
> connector/encoder for it. The reason being that we want to disable
> HPD interrupts for eDP ports when the display is off, but the presence
> o
On Fri, 09 Jan 2015, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> The dev_priv->display.hpd_irq_setup hook is optional, so we can move the
> I915_HAS_HOTPLUG() check out of i915_hpd_irq_setup() and only set up the
> hook when hotplug support is present.
>
> Signed-off-by: Ville S
On 8 January 2015 at 14:18, wrote:
> From: Tim Gore
>
> A recent change to igt_kms.c reqires HAVE_LINUX_KD_H to be set
> in order to pick up the kd.h header file.
Could you include a bit more detail about which commit introduced this
change and why?
>
> Signed-off-by: Tim Gore
> ---
> lib/A
On Fri, 09 Jan 2015, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> intel_hpd_irq_handler() walks the passed in hpd[] array assuming it
> contains HPD_NUM_PINS elements. Currently that's not true as we don't
> specify an explicit size for the arrays when initializing them. Avoid
>
On Fri, 02 Jan 2015, Shobhit Kumar wrote:
> Hi All
> Please find modifed set of patches. Sending as a separate thread as initial
> patches were a crude implementation to trigger discussion, but these have
> been
> tested and also do not need intel_soc_pmic_writeb/readb functionaly, but uses
> th
On Fri, 02 Jan 2015, Shobhit Kumar wrote:
> This allows for proper PPS during enable/disable of BYT-T platforms
> where these signals are routed through PMIC. Needs DRM_PANEL to be
> selected by default as well
>
> Signed-off-by: Shobhit Kumar
> ---
> drivers/gpu/drm/i915/Kconfig |
On Fri, 02 Jan 2015, Shobhit Kumar wrote:
> This driver provides support for the "crystal_cove_panel" cell device.
> On BYT-T pmic has to be used to enable/disable panel.
This needs to be sent to dri-devel.
With the comments below addressed, and with the disclaimer that I have
no idea about the
Reviewed-by: Ander Conselvan de Oliveira
On 12/23/2014 08:41 PM, Matt Roper wrote:
Switch plane handling to use the atomic plane helpers. This means that
rather than provide our own implementations of .update_plane() and
.disable_plane(), we expose the lower-level check/prepare/commit/cleanup
On Fri, 02 Jan 2015, Shobhit Kumar wrote:
> For scenarios where OF is not available, we can use panel identification by
> name.
>
> Signed-off-by: Shobhit Kumar
> ---
> drivers/gpu/drm/drm_panel.c | 18 ++
> include/drm/drm_panel.h | 3 +++
> 2 files changed, 21 insertions(+
Reviewed-by: Ander Conselvan de Oliveira
On 12/23/2014 08:41 PM, Matt Roper wrote:
A few of the sprite-related function names in i915 are very similar
(e.g., intel_enable_planes() vs intel_crtc_enable_planes()) and don't
make it clear whether they only operate on sprite planes, or whether
they
From: Ville Syrjälä
In order to toggle hpd support on/off per-connector during runtime, we
need to track the desired hpd state for each connector. Currently we're
being lazy and only setting up intel_connector->polled when we wish to
use polling instead of hpd, so a value of 0 can mean both "use
From: Ville Syrjälä
915 doens't support hotplug at all, so we shouldn't try to pretend
otherwise in the SDVO code.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_sdvo.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c
b/drivers/gpu/drm/i915
From: Ville Syrjälä
My BSW likes to generate tons of HPD interrupts while the eDP port is
disabled. I guess it leaves the HPD like floating and then stuff like
CPU activity can cause noise on the line leading to tons of spurious
interrupts.
To combat this, disable the relevant HPD interrupt when
From: Ville Syrjälä
The dev_priv->display.hpd_irq_setup hook is optional, so we can move the
I915_HAS_HOTPLUG() check out of i915_hpd_irq_setup() and only set up the
hook when hotplug support is present.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 42
From: Ville Syrjälä
intel_hpd_irq_handler() walks the passed in hpd[] array assuming it
contains HPD_NUM_PINS elements. Currently that's not true as we don't
specify an explicit size for the arrays when initializing them. Avoid
the out of bounds accesses by specifying the size for the arrays.
Cc
From: Ville Syrjälä
If we determine that a specific port is eDP, don't register the HDMI
connector/encoder for it. The reason being that we want to disable
HPD interrupts for eDP ports when the display is off, but the presence
of the extra HDMI connector would demand the HPD interrupt to remain
e
From: Ville Syrjälä
Handle things the same way when initializing hpd support and re-enabling
hpd interrupts after recovering from an interrupt storm. Later on we'll
share the same code also when togglind hpd on/off for inidividual eDP
connectors.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/dr
From: Ville Syrjälä
My BSW has a nasty problem where it generates tons of spurious hpd interrupts
when the eDP display is disabled. The best solution seems to be to disable hpd
for eDP ports when the port is disabled since we don't care about long hpds
anyway and short hpds are only relevant whil
Reviewed-by: Ander Conselvan de Oliveira
On 12/23/2014 08:41 PM, Matt Roper wrote:
Move the vblank evasion up from the low-level, hw-specific
update_plane() handlers to the general plane commit operation.
Everything inside commit should now be non-sleeping, so this brings us
closer to how vblan
Reviewed-by: Ander Conselvan de Oliveira
On 12/24/2014 05:59 PM, Matt Roper wrote:
Once we integrate our work into the atomic pipeline, plane commit
operations will need to happen with interrupts disabled, due to vblank
evasion. Our commit functions today include sleepable work, so those
opera
A previous commit enabled execlists by default:
commit 27401d126b5b ("drm/i915/bdw: Enable execlists by default where
supported")
This allowed routine testing of execlists which exposed a regression when
resuming from suspend. The cause was tracked down the to recent changes to the
ring
At Fri, 9 Jan 2015 10:18:45 +0100,
Daniel Vetter wrote:
>
> On Thu, Jan 08, 2015 at 05:54:12PM +0200, Imre Deak wrote:
> > This is v4 of [1] addressing the review comments from Takashi and Jani.
> >
> > [1]
> > http://lists.freedesktop.org/archives/intel-gfx/2014-December/056992.html
> >
> > Imr
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -31 363/364
On Thu, Jan 08, 2015 at 05:54:12PM +0200, Imre Deak wrote:
> This is v4 of [1] addressing the review comments from Takashi and Jani.
>
> [1]
> http://lists.freedesktop.org/archives/intel-gfx/2014-December/056992.html
>
> Imre Deak (6):
> drm/i915: add dev_to_i915 helper
> drm/i915: add compon
Hi all,
We're pleased to announce a public update to Intel Graphics Virtualization
Technology (Intel GVT-g, formerly known as XenGT). Intel GVT-g is a complete
vGPU solution with mediated pass-through, supported today on 4th generation
Intel Core(TM) processors with Intel Graphics processors
On Fri, 09 Jan 2015, Jeremiah Mahler wrote:
> Jani, all,
>
> On a Lenovo X1 Carbon if the display is off when suspend is entered
> it will be off when it is resumed. A key must be pressed to restore
> normal brightness.
Please file a bug on [1] and attach dmesg with drm.debug=14 set, from
boot t
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