On Wed, Dec 24, 2014 at 12:22:38AM -0500, Felix Miata wrote:
> 4 series onboard video rev 03 (G41)
> using DVI to HDMI cable on DVI motherboard connector, which Xorg reports as
> HDMI1
> Display is 1920x1080 LCD TV, using HDMI connector #4
> Rawhide
> kernel 3.18.1
> Xorg 1.16.3RC1
> xorg-x11-drv-
4 series onboard video rev 03 (G41)
using DVI to HDMI cable on DVI motherboard connector, which Xorg reports as
HDMI1
Display is 1920x1080 LCD TV, using HDMI connector #4
Rawhide
kernel 3.18.1
Xorg 1.16.3RC1
xorg-x11-drv-intel-2.99.917
1-connected and unconnected absent from Xorg.0.log
2-EDID pr
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 363/364
Once we integrate our work into the atomic pipeline, plane commit
operations will need to happen with interrupts disabled, due to vblank
evasion. Our commit functions today include sleepable work, so those
operations need to be split out and run either before or after the
atomic register programmi
Move the vblank evasion up from the low-level, hw-specific
update_plane() handlers to the general plane commit operation.
Everything inside commit should now be non-sleeping, so this brings us
closer to how vblank evasion will behave once we move over to atomic.
v2:
- Restore lost intel_crtc->act
A few of the sprite-related function names in i915 are very similar
(e.g., intel_enable_planes() vs intel_crtc_enable_planes()) and don't
make it clear whether they only operate on sprite planes, or whether
they also apply to all universal plane types. Rename a few functions to
be more consistent
Switch plane handling to use the atomic plane helpers. This means that
rather than provide our own implementations of .update_plane() and
.disable_plane(), we expose the lower-level check/prepare/commit/cleanup
entrypoints and let the DRM core implement update/disable for us using
those entrypoint
The userspace-requested plane coordinates are now always available via
plane->state.base (and the i915-adjusted values are stored in
plane->state), so we no longer use the coordinate fields in intel_plane
and can drop them.
Also, note that the error case for pageflip calls update_plane() to
progra
Updated based on review feedback from Ander.
Previous series is available here:
http://lists.freedesktop.org/archives/intel-gfx/2014-December/057598.html
Matt Roper (5):
drm/i915: Refactor work that can sleep out of commit (v6)
drm/i915: Move vblank evasion to commit (v4)
drm/i915: Clarif
From: Ben Widawsky
Start using gen8_for_each_pde macro to allocate page tables.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 54 -
drivers/gpu/drm/i915/i915_gem_gtt.h | 10 +++
2 files changed, 39 i
From: Ben Widawsky
This patch was formerly known as, "Force pd restore when PDEs change,
gen6-7." I had to change the name because it is needed for GEN8 too.
The real issue this is trying to solve is when a new object is mapped
into the current address space. The GPU does not snoop the new mappi
From: Ben Widawsky
Instead of implementing the full tracking + dynamic allocation, this
patch does a bit less than half of the work, by tracking and warning on
unexpected conditions. The tracking itself follows which PTEs within a
page table are currently being used for objects. The next patch wi
From: Ben Widawsky
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 9d998ec..8f76990 100644
---
From: Ben Widawsky
v2: Use WARN_ONs (Daniel)
Cc: Daniel Vetter
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_evict.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c
b/drivers/gpu/drm/i915/i915_gem_evi
From: Ben Widawsky
The page directory freer is left here for now as it's still useful given
that GEN8 still preallocates. Once the allocation functions are broken
up into more discrete chunks, we'll follow suit and destroy this
leftover piece.
v2: Match trace_i915_va_teardown params
v3: Multiple
From: Ben Widawsky
We have some fanciness coming up. This patch just breaks out the logic
of context switch skip, pd load pre, and pd load post.
v2: Use new functions to replace the logic right away (Daniel)
Cc: Daniel Vetter
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2)
---
From: Ben Widawsky
When we do dynamic page table allocations for gen8, we'll need to have
more control over how and when we map page tables, similar to gen6.
In particular, DMA mappings for page directories/tables occur at allocation
time.
This patch adds the functionality and calls it at init,
From: Ben Widawsky
Like with gen6/7, we can enable bitmap tracking with all the
preallocations to make sure things actually don't blow up.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 121 +---
drivers/gpu/
From: Ben Widawsky
This finishes off the dynamic page tables allocations, in the legacy 3
level style that already exists. Most everything has already been setup
to this point, the patch finishes off the enabling by setting the
appropriate function pointers.
Zombie tracking:
This could be a sepa
From: Ben Widawsky
These values are never quite useful for dynamic allocations of the page
tables. Getting rid of them will help prevent later confusion.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 --
drivers/gpu/drm/i915/i915_gem_gt
From: Ben Widawsky
Now that we don't need to trace num_pd_pages, we may as well kill all
need for the PPGTT structure in the alloc_pagedirs. This is very useful
for when we move to 48b addressing, and the PDP isn't the root of the
page table structure.
The param is replaced with drm_device, whic
From: Ben Widawsky
The problem is we're going to switch to a new context, which could be
the default context. The plan was to use restore inhibit, which would be
fine, except if we are using dynamic page tables (which we will). If we
use dynamic page tables and we don't load new page tables, the
From: Ben Widawsky
One important part of this patch is we now write a scratch page
directory into any unused PDP descriptors. This matters for 2 reasons,
first, we're not allowed to just use 0, or an invalid pointer, and second,
we must wipe out any previous contents from the last context.
The l
Logic ring contexts need to know the PDPs when they are populated. With
dynamic page table allocations, these PDPs may not exist yet.
Check if PDPs have been allocated and use the scratch page if they do
not exist yet.
Before submission, update the PDPs in the logic ring context as PDPs
have been
From: Ben Widawsky
Therefore we can do it from our general init function. Eventually, I
hope to have a lot more commonality like this. It won't arrive yet, but
this was a nice easy one.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 6 ++---
From: Ben Widawsky
As we move toward dynamic page table allocation, it becomes much easier
to manage our data structures if break do things less coarsely by
breaking up all of our actions into individual tasks. This makes the
code easier to write, read, and verify.
Aside from the dissection of
From: Ben Widawsky
This patch continues on the idea from the previous patch. From here on,
in the steady state, PDEs are all pointing to the scratch page table (as
recommended in the spec). When an object is allocated in the VA range,
the code will determine if we need to allocate a page for the
From: Ben Widawsky
Move the remaining members over to the new page table structures.
This can be squashed with the previous commit if desire. The reasoning
is the same as that patch. I simply felt it is easier to review if split.
v2: In lrc: s/ppgtt->pd_dma_addr[i]/ppgtt->pdp.pagedir[i].daddr/
From: Ben Widawsky
Start using gen8_for_each_pdpe macro to allocate the page directories.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 43 ++---
1 file changed, 31 insertions(+), 12 deletions(-)
diff --git
From: Ben Widawsky
When we move to dynamic page allocation, keeping pagedir and pagetabs as
separate structures will help to break actions into simpler tasks.
To help transition the code nicely there is some wasted space in gen6/7.
This will be ameliorated shortly.
v2: fixed mismatches after cl
From: Ben Widawsky
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_trace.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_trace.h
b/drivers/gpu/drm/i915/i915_trace.h
index 6058a01..f004d3d 100644
--
Addressing comments from v1.
For GEN8, it has also been extended to work in logical ring submission (lrc)
mode, as it will be the preferred mode of operation.
I also tried to update the lrc code at the same time the ppgtt refactoring
occurred, leaving only one patch that is exclusively for lrc.
T
From: Ben Widawsky
The current code will both potentially print a WARN, and setup part of
the PPGTT structure. Neither of these harm the current code, it is
simply for clarity, and to perhaps prevent later bugs, or weird
debug messages.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry
From: Ben Widawsky
In gen8, 32b PPGTT has always had one "pdp" (it doesn't actually have
one, but it resembles having one). The #define was confusing as is, and
using "PDPE" is a much better description.
sed -i 's/GEN8_LEGACY_PDPS/GEN8_LEGACY_PDPES/' drivers/gpu/drm/i915/*.[ch]
It also matches
On 12/16/2014 02:23 AM, Matt Roper wrote:
> The userspace-requested plane coordinates are now always available via
> plane->state.base (and the i915-adjusted values are stored in
> plane->state), so we no longer use the coordinate fields in intel_plane
> and can drop them.
>
> Also, note that the
On 12/16/2014 02:23 AM, Matt Roper wrote:
Switch plane handling to use the atomic plane helpers. This means that
rather than provide our own implementations of .update_plane() and
.disable_plane(), we expose the lower-level check/prepare/commit/cleanup
entrypoints and let the DRM core implement
From: Paulo Zanoni
Because there's no need for it. Just use a static structure with a
bool field to tell if it's in use or not. The big advantage here is
not saving kzalloc/kfree calls, it's cutting the ugly "failed to
allocate FBC work structure" code path: in this path we call
enable_fbc() dire
From: Paulo Zanoni
So check for this.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_fbc.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 80bdbde..8c6fb1d 100644
--- a/drivers
From: Paulo Zanoni
Make sure we're not gonna have weird races in really weird cases where
a lot of different CRTCs are doing rendering and modesets at the same
time.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_fbc.c | 80 +
From: Paulo Zanoni
We first set the threshold value when we're allocating the CFB, and
then later at {ilk,gen7}_fbc_enable() we increment it in case we're
using 16bpp. While that is correct, it is dangerous: if we rework the
code a little bit in a way that allows us to call intel_fbc_enable()
wit
From: Paulo Zanoni
With the current code we just reallocate the compressed FB at every
FBC update: we have X in one frame, then in the other frame we need X
again, but we check "needed < have" instead of "needed <= have".
There are still other problems with this code: we don't take the
threshold
From: Paulo Zanoni
We already had a few bugs in the past where FBC was compressing
nothing when it was enabled, which makes the feature quite useless.
Add this information on debugfs so the test suites can check for
regressions in this piece of the code.
Signed-off-by: Paulo Zanoni
---
drivers
From: Paulo Zanoni
This commit is just to make the intentions explicit: on HSW+ these
bits are MBZ, but since we only support plane A and the macro
evaluates to zero when plane A is the parameter, we're not fixing any
bug.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_fbc.c | 7 ++
From: Paulo Zanoni
Because that is probably not very a good idea: if we used the stolen
memory for more things, there could be a risk that someone would
"allocate" the memory that the HW is still using as the CFB while FBC
was still enabled.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915
From: Paulo Zanoni
We have dev_priv->fbc.size which is supposed to contain the compressed
FB size, but it is not: at find_compression_threshold() we try to
overallocate the CFB, but we don't consider this when we assign a
value to dev_priv->fbc.size. Since the correct CFB size should already
be s
From: Paulo Zanoni
Hi
Since the previous FBC series is already entirely reviewed, it's time to submit
a few more FBC patches to the mailing list. These patches just fix some simple
bugs and annoyances: nothing really major. I tested them on my BDW and they pass
the tests I have.
In theory we co
On Tue, Dec 23, 2014 at 10:14:15AM +, Zhang, Xiong Y wrote:
> > -Original Message-
> > From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
> > Sent: Tuesday, December 23, 2014 5:53 PM
> > To: Zhang, Xiong Y
> > Cc: intel-gfx@lists.freedesktop.org
> > Subject: Re: [Intel-gfx] [PATCH] ig
> -Original Message-
> From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
> Sent: Tuesday, December 23, 2014 5:53 PM
> To: Zhang, Xiong Y
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] igt: Correct the return value for drm
> short_buffer read
>
> On Tue, Dec 23,
On 12/16/2014 02:23 AM, Matt Roper wrote:
A few of the sprite-related function names in i915 are very similar
(e.g., intel_enable_planes() vs intel_crtc_enable_planes()) and don't
make it clear whether they only operate on sprite planes, or whether
they also apply to all universal plane types. R
On 12/16/2014 02:23 AM, Matt Roper wrote:
Move the vblank evasion up from the low-level, hw-specific
update_plane() handlers to the general plane commit operation.
Everything inside commit should now be non-sleeping, so this brings us
closer to how vblank evasion will behave once we move over to
On Tue, Dec 23, 2014 at 03:52:11PM +0800, Xiong Zhang wrote:
> After i915 commit:
> commit bd008e5b2953186fc0c6633a885ade95e7043800
> Author: Chris Wilson
> Date: Tue Oct 7 14:13:51 2014 +0100
>
> drm: Implement O_NONBLOCK support on /dev/dri/cardN
>
> the return value for drm short_buffer
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