On Fri, Dec 19, 2014 at 08:05:30PM +, Chris Wilson wrote:
> On Fri, Dec 19, 2014 at 06:34:07PM +, Chris Wilson wrote:
> > Just a patch a few days ago that to fix a very ontologically similar bug
> > for ivb+.
>
> Oh boy. I just double checked the error states from those bugs I marked
> as
On Fri, Dec 19, 2014 at 06:34:07PM +, Chris Wilson wrote:
> Just a patch a few days ago that to fix a very ontologically similar bug
> for ivb+.
Oh boy. I just double checked the error states from those bugs I marked
as ivb context restore hangs... So far I appear to have consistently
mislable
To end this particular thread, Daniel made a good point on IRC that his
intent is to blow away the contents of the page tables if we need to
swap, and then recreate them upon next use.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
___
Inte
On Fri, Dec 19, 2014 at 09:26:01AM -0800, Ben Widawsky wrote:
> On Fri, Dec 19, 2014 at 08:20:04AM +, Chris Wilson wrote:
> > On Thu, Dec 18, 2014 at 06:20:18PM -0800, Ben Widawsky wrote:
> > > From: Ben Widawsky
> > >
> > > The docs specify this needs to be set on HSW GT1 parts. I've impleme
We apply the RPS interrupt workaround on VLV everywhere except when
writing the mask directly during idling the GPU. For consistency do this
also there.
While at it also extend the code comment about affected platforms.
I couldn't reproduce the issue on VLV fixed by this workaround, by
removing th
In
commit dbea3cea69508e9d548ed4a6be13de35492e5d15
Author: Imre Deak
Date: Mon Dec 15 18:59:28 2014 +0200
drm/i915: sanitize RPS resetting during GPU reset
we disable RPS interrupts during GPU resetting, but don't apply the
necessary GEN6 HW workaround. This leads to a HW lockup during a
GEN8+ HW has the option to route PM interrupts to either the CPU or to
GT. For GEN8 this was already set correctly to routing to CPU, but not
for GEN9, so fix this. Note that when disabling RPS interrupts this was
set already correctly, though in that case it didn't matter much except
for the possi
On Fri, Dec 19, 2014 at 08:20:04AM +, Chris Wilson wrote:
> On Thu, Dec 18, 2014 at 06:20:18PM -0800, Ben Widawsky wrote:
> > From: Ben Widawsky
> >
> > The docs specify this needs to be set on HSW GT1 parts. I've implemented it
> > as
> > such since it should only be needed when using RC6,
In
commit dbea3cea69508e9d548ed4a6be13de35492e5d15
Author: Imre Deak
Date: Mon Dec 15 18:59:28 2014 +0200
drm/i915: sanitize RPS resetting during GPU reset
we disable RPS interrupts during GPU resetting, but don't apply the
necessary GEN6 HW workaround. This leads to a HW lockup during a
We apply the RPS interrupt workaround on VLV everywhere except when
writing the mask directly during idling the GPU. For consistency do this
also there.
While at it also extend the code comment about affected platforms.
I couldn't reproduce the issue on VLV fixed by this workaround, by
removing th
GEN8+ HW has the option to route PM interrupts to either the CPU or to
GT. For GEN8 this was already set correctly to routing to CPU, but not
for GEN9, so fix this. Note that when disabling RPS interrupts this was
set already correctly, though in that case it didn't matter much except
for the possi
Hi all,
New -testing cycle with cool stuff:
- plane handling refactoring from Matt Roper and Gustavo Padovan in prep for
atomic updates
- fixes and more patches for the seqno to request transformation from John
- docbook for fbc from Rodrigo
- prep work for dual-link dsi from Gaurav Signh
- crc
On Fri, Dec 19, 2014 at 10:44:34AM +0100, Daniel Vetter wrote:
> Hi Dave,
>
> drm-intel-next-2014-12-05:
> - dual-dsi enabling from Gaurav with prep work from Jani
> - reshuffling the ring init code to move towards a clean sw/hw state setup
> split
> - ring free space refactoring from Dave Gordon
Doh! The subject was meant to be RFC not PATCH.
On 19/12/2014 14:41, john.c.harri...@intel.com wrote:
From: John Harrison
The outstanding lazy request mechanism does not really work well with
a GPU scheduler. The scheduler expects each work packet, i.e. request
structure, to be a complete enti
From: John Harrison
The outstanding lazy request mechanism does not really work well with
a GPU scheduler. The scheduler expects each work packet, i.e. request
structure, to be a complete entity and to belong to one and only one
submitter. Whereas the whole lazy mechanism allows lots of work from
Atomic doesn't really work without universal planes anyway. But make
sure that evil userspace doesn't pull the kernel over the table
because we didn't consider a cornercase that just doesn't make sense,
just for safety.
v2: Just force ->universal_planes to the same value to avoid imposing
restrict
On Fri, Dec 19, 2014 at 02:09:32PM +0200, Ander Conselvan de Oliveira wrote:
> On 12/10/2014 04:53 PM, Ville Syrjälä wrote:
> > On Wed, Dec 10, 2014 at 02:53:01PM +0100, Daniel Vetter wrote:
> >> On Wed, Dec 10, 2014 at 11:13:28AM +, Chris Wilson wrote:
> >>> On Wed, Dec 10, 2014 at 11:23:44AM
On Fri, 2014-12-19 at 14:41 +0100, Daniel Vetter wrote:
> On Fri, Dec 19, 2014 at 02:51:57PM +0200, Imre Deak wrote:
> > In
> >
> > commit dbea3cea69508e9d548ed4a6be13de35492e5d15
> > Author: Imre Deak
> > Date: Mon Dec 15 18:59:28 2014 +0200
> >
> > drm/i915: sanitize RPS resetting during
On Fri, Dec 19, 2014 at 02:51:57PM +0200, Imre Deak wrote:
> In
>
> commit dbea3cea69508e9d548ed4a6be13de35492e5d15
> Author: Imre Deak
> Date: Mon Dec 15 18:59:28 2014 +0200
>
> drm/i915: sanitize RPS resetting during GPU reset
>
> we disable RPS interrupts during GPU resetting, but don'
On Fri, Dec 19, 2014 at 02:29:57PM +0100, Daniel Vetter wrote:
> On Fri, Dec 19, 2014 at 01:10:40PM +, Chris Wilson wrote:
> > On Fri, Dec 19, 2014 at 11:13:51AM +0100, Daniel Vetter wrote:
> > > On Fri, Dec 19, 2014 at 08:50:09AM +, Chris Wilson wrote:
> > > > On Fri, Dec 19, 2014 at 09:37
On Fri, Dec 19, 2014 at 02:51:56PM +0200, Imre Deak wrote:
> GEN8+ HW has the option to route PM interrupts to either the CPU or to
> GT. For GEN8 this was already set correctly to routing to CPU, but not
> for GEN9, so fix this. Note that when disabling RPS interrupts this was
> set already correc
On Fri, Dec 19, 2014 at 01:10:40PM +, Chris Wilson wrote:
> On Fri, Dec 19, 2014 at 11:13:51AM +0100, Daniel Vetter wrote:
> > On Fri, Dec 19, 2014 at 08:50:09AM +, Chris Wilson wrote:
> > > On Fri, Dec 19, 2014 at 09:37:52AM +0100, Daniel Vetter wrote:
> > > > On Fri, Dec 19, 2014 at 08:31
On Fri, Dec 19, 2014 at 12:32:23PM +, Dave Gordon wrote:
> On 18/12/14 20:44, Daniel Vetter wrote:
> > On Thu, Dec 18, 2014 at 09:40:51PM +0100, Daniel Vetter wrote:
> >> On Thu, Dec 18, 2014 at 05:10:00PM +, Michel Thierry wrote:
> >>> From: Ben Widawsky
> >>>
> >>> In gen8, 32b PPGTT has
On Fri, Dec 19, 2014 at 11:15:59AM +0100, Daniel Vetter wrote:
> On Fri, Dec 19, 2014 at 09:17:40AM +, Chris Wilson wrote:
> > On Fri, Dec 19, 2014 at 11:05:36AM +0200, Imre Deak wrote:
> > > On Fri, 2014-12-19 at 08:26 +, Chris Wilson wrote:
> > > > On Fri, Dec 19, 2014 at 12:14:00AM +0200
On Fri, Dec 19, 2014 at 11:13:51AM +0100, Daniel Vetter wrote:
> On Fri, Dec 19, 2014 at 08:50:09AM +, Chris Wilson wrote:
> > On Fri, Dec 19, 2014 at 09:37:52AM +0100, Daniel Vetter wrote:
> > > On Fri, Dec 19, 2014 at 08:31:03AM +, Chris Wilson wrote:
> > > > On Thu, Dec 18, 2014 at 10:16
GEN8+ HW has the option to route PM interrupts to either the CPU or to
GT. For GEN8 this was already set correctly to routing to CPU, but not
for GEN9, so fix this. Note that when disabling RPS interrupts this was
set already correctly, though in that case it didn't matter much except
for the possi
In
commit dbea3cea69508e9d548ed4a6be13de35492e5d15
Author: Imre Deak
Date: Mon Dec 15 18:59:28 2014 +0200
drm/i915: sanitize RPS resetting during GPU reset
we disable RPS interrupts during GPU resetting, but don't apply the
necessary GEN6 HW workaround. This leads to a HW lockup during a
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 364/364 3
> > > > If we were to be consistent, then we would pad in the GTT so that no
> > > > other object fitted in the full fenced region.
> > >
> > > Yes, I did that. In v2 I changed this (based on your feedback) so the
> > > padding happens only on old GENs with the POT constraint, since on
> new
> > >
On 12/19/2014 10:13 AM, Daniel Vetter wrote:
On Fri, Dec 19, 2014 at 08:50:09AM +, Chris Wilson wrote:
On Fri, Dec 19, 2014 at 09:37:52AM +0100, Daniel Vetter wrote:
On Fri, Dec 19, 2014 at 08:31:03AM +, Chris Wilson wrote:
On Thu, Dec 18, 2014 at 10:16:22PM +0100, Daniel Vetter wrote:
On 18/12/14 20:44, Daniel Vetter wrote:
> On Thu, Dec 18, 2014 at 09:40:51PM +0100, Daniel Vetter wrote:
>> On Thu, Dec 18, 2014 at 05:10:00PM +, Michel Thierry wrote:
>>> From: Ben Widawsky
>>>
>>> In gen8, 32b PPGTT has always had one "pdp" (it doesn't actually have
>>> one, but it resembles
Daniel Vetter writes:
> On Fri, Dec 19, 2014 at 11:53:21AM +0200, Imre Deak wrote:
>> In
>>
>> commit dbea3cea69508e9d548ed4a6be13de35492e5d15
>> Author: Imre Deak
>> Date: Mon Dec 15 18:59:28 2014 +0200
>>
>> drm/i915: sanitize RPS resetting during GPU reset
>>
>> we disable RPS interr
On 12/10/2014 04:53 PM, Ville Syrjälä wrote:
On Wed, Dec 10, 2014 at 02:53:01PM +0100, Daniel Vetter wrote:
On Wed, Dec 10, 2014 at 11:13:28AM +, Chris Wilson wrote:
On Wed, Dec 10, 2014 at 11:23:44AM +0100, Daniel Vetter wrote:
On Wed, Dec 10, 2014 at 08:17:11AM +, Chris Wilson wrote:
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 364/364 3
On Fri, Dec 19, 2014 at 11:53:21AM +0200, Imre Deak wrote:
> In
>
> commit dbea3cea69508e9d548ed4a6be13de35492e5d15
> Author: Imre Deak
> Date: Mon Dec 15 18:59:28 2014 +0200
>
> drm/i915: sanitize RPS resetting during GPU reset
>
> we disable RPS interrupts during GPU resetting, but don'
On Fri, Dec 19, 2014 at 09:17:40AM +, Chris Wilson wrote:
> On Fri, Dec 19, 2014 at 11:05:36AM +0200, Imre Deak wrote:
> > On Fri, 2014-12-19 at 08:26 +, Chris Wilson wrote:
> > > On Fri, Dec 19, 2014 at 12:14:00AM +0200, Imre Deak wrote:
> > > > On Thu, 2014-12-18 at 22:19 +0100, Daniel Ve
On Fri, Dec 19, 2014 at 08:50:09AM +, Chris Wilson wrote:
> On Fri, Dec 19, 2014 at 09:37:52AM +0100, Daniel Vetter wrote:
> > On Fri, Dec 19, 2014 at 08:31:03AM +, Chris Wilson wrote:
> > > On Thu, Dec 18, 2014 at 10:16:22PM +0100, Daniel Vetter wrote:
> > > > On Thu, Dec 18, 2014 at 05:09
In
commit dbea3cea69508e9d548ed4a6be13de35492e5d15
Author: Imre Deak
Date: Mon Dec 15 18:59:28 2014 +0200
drm/i915: sanitize RPS resetting during GPU reset
we disable RPS interrupts during GPU resetting, but don't apply the
necessary GEN6 HW workaround. This leads to a HW lockup during a
Hi Dave,
drm-intel-next-2014-12-05:
- dual-dsi enabling from Gaurav with prep work from Jani
- reshuffling the ring init code to move towards a clean sw/hw state setup split
- ring free space refactoring from Dave Gordon
- s/seqno/request/ rework from John Harrison
- psr support for vlv/chv from R
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 364/364 3
Atomic doesn't really work without universal planes anyway. But make
sure that evil userspace doesn't pull the kernel over the table
because we didn't consider a cornercase that just doesn't make sense,
just for safety.
Only requirement imposed on userspace by this is that it asks for
universal pl
On Wed, 10 Dec 2014, Gaurav K Singh wrote:
> For CHT changes are required for calculating the correct m,n & p with
> minimal error +/- for the required DSI clock, so that the correct dividor
> & ctrl values are written in cck regs for DSI. This patch has been tested
> on CHT RVP with 1200 x 1920 p
Hi Dave,
Next batch of atomic work. Most important is the propertification from Rob
and the nth iteration of the actual atomic ioctl originally from Ville.
Big differences compared to earlier revisions:
- Core properties are now fully handled by the core, drivers can only
handle driver-specific
Hi Dave,
A bit early for 3.20, but I'm out the next 2 weeks so figured I'll send
you my pull request already.
Misc drm patches with mostly polish patches from Thierry, with a bit of
generic mode validation from Ville and a few other oddball things.
Cheers, Daniel
The following changes since co
On Fri, Dec 19, 2014 at 11:05:36AM +0200, Imre Deak wrote:
> On Fri, 2014-12-19 at 08:26 +, Chris Wilson wrote:
> > On Fri, Dec 19, 2014 at 12:14:00AM +0200, Imre Deak wrote:
> > > On Thu, 2014-12-18 at 22:19 +0100, Daniel Vetter wrote:
> > > > On Thu, Dec 18, 2014 at 11:04:11PM +0200, Ville Sy
On Fri, 2014-12-19 at 08:26 +, Chris Wilson wrote:
> On Fri, Dec 19, 2014 at 12:14:00AM +0200, Imre Deak wrote:
> > On Thu, 2014-12-18 at 22:19 +0100, Daniel Vetter wrote:
> > > On Thu, Dec 18, 2014 at 11:04:11PM +0200, Ville Syrjälä wrote:
> > > > On Thu, Dec 18, 2014 at 09:37:37PM +0100, Dani
On Fri, Dec 19, 2014 at 09:37:52AM +0100, Daniel Vetter wrote:
> On Fri, Dec 19, 2014 at 08:31:03AM +, Chris Wilson wrote:
> > On Thu, Dec 18, 2014 at 10:16:22PM +0100, Daniel Vetter wrote:
> > > On Thu, Dec 18, 2014 at 05:09:57PM +, Michel Thierry wrote:
> > > > This new version tries to r
On Thu, Dec 18, 2014 at 02:43:45PM -0800, Bob Paauwe wrote:
> On Thu, 18 Dec 2014 21:31:43 +0100
> Daniel Vetter wrote:
>
> > On Thu, Dec 18, 2014 at 09:50:27AM -0800, Bob Paauwe wrote:
> > > +
> > > + /* Set the tiled buffer to all 0xff's */
> > > + memset(bo_tiled->virtual, 0xff, bo_tiled->size
On Fri, Dec 19, 2014 at 08:31:03AM +, Chris Wilson wrote:
> On Thu, Dec 18, 2014 at 10:16:22PM +0100, Daniel Vetter wrote:
> > On Thu, Dec 18, 2014 at 05:09:57PM +, Michel Thierry wrote:
> > > This new version tries to remove as many unnecessary changes as possible
> > > from
> > > the pre
On Thu, Dec 18, 2014 at 10:16:22PM +0100, Daniel Vetter wrote:
> On Thu, Dec 18, 2014 at 05:09:57PM +, Michel Thierry wrote:
> > This new version tries to remove as many unnecessary changes as possible
> > from
> > the previous RFC.
> >
> > For GEN8, it has also been extended to work in logi
On Fri, Dec 19, 2014 at 12:14:00AM +0200, Imre Deak wrote:
> On Thu, 2014-12-18 at 22:19 +0100, Daniel Vetter wrote:
> > On Thu, Dec 18, 2014 at 11:04:11PM +0200, Ville Syrjälä wrote:
> > > On Thu, Dec 18, 2014 at 09:37:37PM +0100, Daniel Vetter wrote:
> > > > On Thu, Dec 18, 2014 at 09:51:26AM -08
On Thu, Dec 18, 2014 at 06:20:18PM -0800, Ben Widawsky wrote:
> From: Ben Widawsky
>
> The docs specify this needs to be set on HSW GT1 parts. I've implemented it as
> such since it should only be needed when using RC6, but it can probably go
> anywhere.
>
> This patch fixes extremely reproducib
On Thu, 18 Dec 2014, shuang...@intel.com wrote:
> Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
> shuang...@intel.com)
> -Summary-
> Platform Delta drm-intel-nightly Series Applied
>
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