Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 364/364
On 12/05/2014 09:54 PM, Daniel Vetter wrote:
Yeah done a quick read-through of just the i915 bits too, same comment. I
guess this is just the first RFC and the redesign we've discussed about
already with xengt is in progress somewhere?
Yes, it's marching on with Xen now. The KVM implementation
CC Andy :)
On 12/05/2014 09:03 PM, Paolo Bonzini wrote:
On 05/12/2014 09:50, Gerd Hoffmann wrote:
A few comments on the kernel stuff (brief look so far, also
compile-tested only, intel gfx on my test machine is too old).
* Noticed the kernel bits don't even compile when configured as
mo
On 12/05/2014 04:50 PM, Gerd Hoffmann wrote:
A few comments on the kernel stuff (brief look so far, also
compile-tested only, intel gfx on my test machine is too old).
* Noticed the kernel bits don't even compile when configured as
module. Everything (vgt, i915, kvm) must be compiled into
Short version:
- Khronos face-to-face
- BYT performance work
Longer version:
Yet another Khronos face-to-face meeting. This was a special meeting
just for the gl_common working group to hammer out details of XGL (still
need a name!) so that we can at least have a chance of having a
provisional
ON these platforms we don't have hardware tracking working for any case.
So we need to fake this on software by forcing psr to exit on every
flush.
Manual tests indicated this was needed.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_psr.c | 6 ++
1 file changed, 2 insertions(+
Since active function on VLV immediately activate PSR let's give more
time for idleness.
v2: Rebase over intel_psr.c and fix typo.
v3: Revival: Manual tests indicated that this is needed. With a short delay
there is a huge
risk of getting blank screens when planes are being enabled.
Signed-o
This will allow manual tests when crc isn't available.
Signed-off-by: Rodrigo Vivi
---
tests/kms_psr_sink_crc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/kms_psr_sink_crc.c b/tests/kms_psr_sink_crc.c
index 98b60cf..ad440a8 100644
--- a/tests/kms_psr_sink_crc.c
+++
this will allow manual tests when crc isn't available.
Signed-off-by: Rodrigo Vivi
---
tests/kms_psr_sink_crc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/kms_psr_sink_crc.c b/tests/kms_psr_sink_crc.c
index 865ac70..155c25f 100644
--- a/tests/kms_psr_sink_crc.c
+++
This will allow manual tests when crc isn't available.
Signed-off-by: Rodrigo Vivi
---
tests/kms_psr_sink_crc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/kms_psr_sink_crc.c b/tests/kms_psr_sink_crc.c
index ad440a8..892bba6 100644
--- a/tests/kms_psr_sink_crc.c
this will allow manual tests when crc isn't available.
Signed-off-by: Rodrigo Vivi
---
tests/kms_psr_sink_crc.c | 29 +++--
1 file changed, 19 insertions(+), 10 deletions(-)
diff --git a/tests/kms_psr_sink_crc.c b/tests/kms_psr_sink_crc.c
index 892bba6..865ac70 100644
--
Sink CRC is the most reliable way to test PSR. However in some platforms
apparently auto generated packages force panel to keep calculating CRC
invalidating
our current sink crc check over debugfs.
So, this manual test help us to find possible gaps on this platforms where we
cannot
trust on sink
On 12/05/2014 05:23 AM, Imre Deak wrote:
On Fri, 2014-12-05 at 13:57 +0200, Jani Nikula wrote:
On Fri, 05 Dec 2014, Imre Deak wrote:
On Fri, 2014-12-05 at 10:37 +0200, Jani Nikula wrote:
On Fri, 05 Dec 2014, Clint Taylor wrote:
On 12/04/2014 11:08 AM, Clint Taylor wrote:
On 12/04/2014 12:4
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 364/364
On Thu, Dec 04, 2014 at 06:39:35PM +0200, Imre Deak wrote:
> As described in the code comment, I couldn't set the minimum RPS
> frequency on my BYT-M B0 to the minimum allowed as reported by Punit.
> Fix this by clamping the minimum value to the first one that was
> accepted on my machine. This fix
On Fri, 2014-12-05 at 23:16 +0200, Imre Deak wrote:
> On Fri, 2014-12-05 at 21:58 +0100, Daniel Vetter wrote:
> > On Thu, Dec 04, 2014 at 06:39:35PM +0200, Imre Deak wrote:
> > > As described in the code comment, I couldn't set the minimum RPS
> > > frequency on my BYT-M B0 to the minimum allowed a
On Fri, 2014-12-05 at 21:58 +0100, Daniel Vetter wrote:
> On Thu, Dec 04, 2014 at 06:39:35PM +0200, Imre Deak wrote:
> > As described in the code comment, I couldn't set the minimum RPS
> > frequency on my BYT-M B0 to the minimum allowed as reported by Punit.
> > Fix this by clamping the minimum va
On Fri, Dec 05, 2014 at 05:13:17PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Aim the dummy load to the current back buffer instead if the front
> buffer. Assuming the idea is to get the next flip to be stuck behind
> the dummy load?
Yeah that makes more sense. Ack on
On Fri, Dec 05, 2014 at 08:59:42PM +, Chris Wilson wrote:
> On Fri, Dec 05, 2014 at 09:56:18PM +0100, Daniel Vetter wrote:
> > On Thu, Dec 04, 2014 at 06:09:39PM +0200, Imre Deak wrote:
> > > When changing the sysfs GT min/max frequencies, the kernel won't
> > > explicitly change the current fr
On Fri, Dec 05, 2014 at 02:15:21PM +, Chris Wilson wrote:
> On Sandybridge+, the GPU provides the ERROR register for detecting page
> faults. Hook this up to our hangcheck so that we can dump the error
> state soon after such an event occurs. This would be better inside an
> interrupt handler,
On Fri, 2014-12-05 at 21:56 +0100, Daniel Vetter wrote:
> On Thu, Dec 04, 2014 at 06:09:39PM +0200, Imre Deak wrote:
> > When changing the sysfs GT min/max frequencies, the kernel won't
> > explicitly change the current frequency, unless it becomes out of bound
> > based on the new min/max values.
On Fri, Dec 05, 2014 at 04:23:56PM +, Chris Wilson wrote:
> On Fri, Dec 05, 2014 at 03:58:40PM +0100, Daniel Vetter wrote:
> > On Fri, Dec 05, 2014 at 02:38:46PM +, Chris Wilson wrote:
> > > On Fri, Dec 05, 2014 at 04:31:35PM +0200, Ville Syrjälä wrote:
> > > > On Fri, Dec 05, 2014 at 02:15
On Fri, Dec 05, 2014 at 09:56:18PM +0100, Daniel Vetter wrote:
> On Thu, Dec 04, 2014 at 06:09:39PM +0200, Imre Deak wrote:
> > When changing the sysfs GT min/max frequencies, the kernel won't
> > explicitly change the current frequency, unless it becomes out of bound
> > based on the new min/max v
On Thu, Dec 04, 2014 at 06:19:54PM -0800, shuang...@intel.com wrote:
> Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
> shuang...@intel.com)
> -Summary-
> Platform Delta drm-intel-nightly
On Thu, Dec 04, 2014 at 06:39:35PM +0200, Imre Deak wrote:
> As described in the code comment, I couldn't set the minimum RPS
> frequency on my BYT-M B0 to the minimum allowed as reported by Punit.
> Fix this by clamping the minimum value to the first one that was
> accepted on my machine. This fix
On Thu, Dec 04, 2014 at 06:09:39PM +0200, Imre Deak wrote:
> When changing the sysfs GT min/max frequencies, the kernel won't
> explicitly change the current frequency, unless it becomes out of bound
> based on the new min/max values. The test happens to work on non-VLV
> platforms because on those
On Sat, Dec 06, 2014 at 12:40:39AM +0530, Gaurav K Singh wrote:
> For dual link MIPI panels, SHUTDOWN packet needs to send to both Ports
> A & C during MIPI encoder disabling sequence. Similarly, TURN ON packet
> to be sent to both Ports during MIPI encoder enabling sequence.
>
> v2: Address revie
On Fri, Dec 05, 2014 at 09:48:03PM +0100, Daniel Vetter wrote:
> On Fri, Dec 05, 2014 at 01:49:36PM +, john.c.harri...@intel.com wrote:
> > From: John Harrison
> >
> > Added the request structure's 'uniq' identifier to the trace information.
> > Also
> > renamed the '_complete' trace event t
On Fri, Dec 05, 2014 at 01:49:36PM +, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> Added the request structure's 'uniq' identifier to the trace information. Also
> renamed the '_complete' trace event to '_notify' as it actually happens in the
> IRQ 'notify_ring()' function. The
On Fri, Dec 05, 2014 at 06:02:35PM +, John Harrison wrote:
> But yes, the reasoning why it crashes without the zero fill is correct.
> Dodgy context pointers that used to be ignored now get processed. Doing the
> zero fill keeps it all sane.
>
> On 05/12/2014 17:54, John Harrison wrote:
> >Thi
On 12/5/2014 11:18 PM, Siluvery, Arun wrote:
On 05/12/2014 17:36, Jani Nikula wrote:
On Fri, 05 Dec 2014, "Siluvery, Arun"
wrote:
On 05/12/2014 16:33, Singh, Gaurav K wrote:
On 12/4/2014 2:57 PM, Jani Nikula wrote:
On Thu, 04 Dec 2014, Gaurav K Singh wrote:
For dual link MIPI Panels, each
On Fri, Dec 05, 2014 at 01:49:33PM +, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> The display related patches earlier in this series were edited during merge to
> improve the request unreferencing. Specifically, the need for de-referencing
> at
> interrupt time was removed. Ho
On 12/5/2014 8:08 PM, Daniel Vetter wrote:
On Fri, Dec 05, 2014 at 06:20:43PM +0530, Singh, Gaurav K wrote:
On 12/4/2014 4:52 PM, Daniel Vetter wrote:
On Thu, Dec 04, 2014 at 11:14:01AM +0200, Jani Nikula wrote:
On Thu, 04 Dec 2014, Gaurav K Singh wrote:
This patch is in preparation of DSI
On Fri, Dec 05, 2014 at 10:30:47AM -0800, Jesse Barnes wrote:
> On Fri, 11 Apr 2014 15:55:17 +0200
> Daniel Vetter wrote:
>
> > Apparently stuff works that way on those machines.
> >
> > I agree with Chris' concern that this is a bit risky but imo worth a
> > shot in -next just for fun. Afaics a
We need to program both port registers during dual link enable path.
v2: Address review comments by Jani
- Used a for loop instead of do-while loop.
v3: Used for_each_dsi_port macro instead of for loop
v4: Renamed mode_hactive variable to mode_hdisplay
Signed-off-by: Gaurav K Singh
Signed-
On Fri, Dec 05, 2014 at 10:15:07AM +0200, Ander Conselvan de Oliveira wrote:
> Reviewed-by: Ander Conselvan de Oliveira
>
>
> On 12/04/2014 08:27 PM, Matt Roper wrote:
> > If we extend the commit_plane handlers for each plane type to be able to
> > handle fb=0, then we can easily implement plane
For dual link MIPI panels, SHUTDOWN packet needs to send to both Ports
A & C during MIPI encoder disabling sequence. Similarly, TURN ON packet
to be sent to both Ports during MIPI encoder enabling sequence.
v2: Address review comments by Jani
- Used a for loop instead of do-while loop.
v3: Us
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 364/364
On Fri, 11 Apr 2014 15:55:17 +0200
Daniel Vetter wrote:
> Apparently stuff works that way on those machines.
>
> I agree with Chris' concern that this is a bit risky but imo worth a
> shot in -next just for fun. Afaics all these machines have the pci
> resources allocated like that by the BIOS,
John Harrison writes:
> This is already part of the seqno/request patch series and has been
> right from the start. See email 'drm/i915: Zero fill the request structure'.
Indeed. Sorry for missing this one. My patch can be ignored.
But do you agree on failure path?
-Mika
> On 05/12/2014 17:5
But yes, the reasoning why it crashes without the zero fill is correct.
Dodgy context pointers that used to be ignored now get processed. Doing
the zero fill keeps it all sane.
On 05/12/2014 17:54, John Harrison wrote:
This is already part of the seqno/request patch series and has been
right f
This is already part of the seqno/request patch series and has been
right from the start. See email 'drm/i915: Zero fill the request structure'.
On 05/12/2014 17:54, Mika Kuoppala wrote:
Otherwise we might end up referencing uninitialized fields.
This is apparent when we try to cleanup the prea
Otherwise we might end up referencing uninitialized fields.
This is apparent when we try to cleanup the preallocated request
on ring reset, before any request has been submitted to the ring.
The request->ctx is foobar and we end up freeing the foobarness.
References: https://bugs.freedesktop.org/s
On 05/12/2014 17:36, Jani Nikula wrote:
On Fri, 05 Dec 2014, "Siluvery, Arun" wrote:
On 05/12/2014 16:33, Singh, Gaurav K wrote:
On 12/4/2014 2:57 PM, Jani Nikula wrote:
On Thu, 04 Dec 2014, Gaurav K Singh wrote:
For dual link MIPI Panels, each port needs half of pixel clock. Pixel overlap
On Fri, 05 Dec 2014, Ville Syrjälä wrote:
> On Fri, Dec 05, 2014 at 06:44:19PM +0200, Jani Nikula wrote:
>> On Fri, 05 Dec 2014, ville.syrj...@linux.intel.com wrote:
>> > From: Ville Syrjälä
>> >
>> > swap() will swap its two arguments while keeping the required
>> > tmp variable hidden. Makes fo
On Fri, 05 Dec 2014, "Siluvery, Arun" wrote:
> On 05/12/2014 16:33, Singh, Gaurav K wrote:
>>
>> On 12/4/2014 2:57 PM, Jani Nikula wrote:
>>> On Thu, 04 Dec 2014, Gaurav K Singh wrote:
For dual link MIPI Panels, each port needs half of pixel clock. Pixel
overlap
can be enabled if
On 12/5/2014 10:24 PM, Siluvery, Arun wrote:
On 05/12/2014 16:33, Singh, Gaurav K wrote:
On 12/4/2014 2:57 PM, Jani Nikula wrote:
On Thu, 04 Dec 2014, Gaurav K Singh wrote:
For dual link MIPI Panels, each port needs half of pixel clock.
Pixel overlap
can be enabled if needed by panel, then
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 364/364
On Fri, Dec 05, 2014 at 06:44:19PM +0200, Jani Nikula wrote:
> On Fri, 05 Dec 2014, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > swap() will swap its two arguments while keeping the required
> > tmp variable hidden. Makes for neater code.
> >
> > Signed-off-by: Ville Syrjäl
On Fri, Dec 05, 2014 at 04:26:23PM +, Chris Wilson wrote:
> On Fri, Dec 05, 2014 at 04:53:49PM +0200, Ville Syrjälä wrote:
> > On Fri, Dec 05, 2014 at 02:38:46PM +, Chris Wilson wrote:
> > > On Fri, Dec 05, 2014 at 04:31:35PM +0200, Ville Syrjälä wrote:
> > > > On Fri, Dec 05, 2014 at 02:15
On 05/12/2014 16:33, Singh, Gaurav K wrote:
On 12/4/2014 2:57 PM, Jani Nikula wrote:
On Thu, 04 Dec 2014, Gaurav K Singh wrote:
For dual link MIPI Panels, each port needs half of pixel clock. Pixel overlap
can be enabled if needed by panel, then in that case, pixel clock will be
increased for
On Fri, 05 Dec 2014, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> swap() will swap its two arguments while keeping the required
> tmp variable hidden. Makes for neater code.
>
> Signed-off-by: Ville Syrjälä
> ---
> lib/igt_aux.h | 6 ++
> 1 file changed, 6 insertions(+)
>
>
On 12/4/2014 2:57 PM, Jani Nikula wrote:
On Thu, 04 Dec 2014, Gaurav K Singh wrote:
For dual link MIPI Panels, each port needs half of pixel clock. Pixel overlap
can be enabled if needed by panel, then in that case, pixel clock will be
increased for extra pixels.
v2 : Address review comments
On Fri, Dec 05, 2014 at 03:46:54PM +0100, Daniel Vetter wrote:
> On Fri, Dec 05, 2014 at 01:14:40PM +, Chris Wilson wrote:
> > +static void assert_empty(int fd)
> > +{
> > + struct pollfd pfd = {fd, POLLIN };
> > + igt_assert(poll(&pfd, 1, 0) == 0);
> > +}
> > +
> > +static void generate_ev
On Fri, Dec 05, 2014 at 04:53:49PM +0200, Ville Syrjälä wrote:
> On Fri, Dec 05, 2014 at 02:38:46PM +, Chris Wilson wrote:
> > On Fri, Dec 05, 2014 at 04:31:35PM +0200, Ville Syrjälä wrote:
> > > On Fri, Dec 05, 2014 at 02:15:22PM +, Chris Wilson wrote:
> > > > Currently we initialise the r
On Fri, Dec 05, 2014 at 03:58:40PM +0100, Daniel Vetter wrote:
> On Fri, Dec 05, 2014 at 02:38:46PM +, Chris Wilson wrote:
> > On Fri, Dec 05, 2014 at 04:31:35PM +0200, Ville Syrjälä wrote:
> > > On Fri, Dec 05, 2014 at 02:15:22PM +, Chris Wilson wrote:
> > > > Currently we initialise the r
From: Ville Syrjälä
Try to tune the dummy load to ~1 second. The calibration happens the
first time dummy load is generated.
v2: Actually do the number of ops intended and
calibrate to 1 second and not 2
Signed-off-by: Ville Syrjälä
---
tests/kms_flip.c | 81 ++
From: Ville Syrjälä
Make the dummy load independent of the display resolution by using a
two fixed size dummy bos to generate the load. As a final step do
another copy from one of the dummy bos to the fb to make sure there's
a dependency between the dummy load and any subsequent operation on
the
From: Ville Syrjälä
Aim the dummy load to the current back buffer instead if the front
buffer. Assuming the idea is to get the next flip to be stuck behind
the dummy load?
Signed-off-by: Ville Syrjälä
---
tests/kms_flip.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
From: Ville Syrjälä
Try to tune the dummy load to ~1 second. The calibration happens the
first time dummy load is generated.
Signed-off-by: Ville Syrjälä
---
tests/kms_flip.c | 81
1 file changed, 70 insertions(+), 11 deletions(-)
diff
From: Ville Syrjälä
Pull the code to emit a single blit to a separate function.
Signed-off-by: Ville Syrjälä
---
tests/kms_flip.c | 47 ---
1 file changed, 28 insertions(+), 19 deletions(-)
diff --git a/tests/kms_flip.c b/tests/kms_flip.c
index e579
From: Ville Syrjälä
Found some open coded min()/max()/swap() macros.
Signed-off-by: Ville Syrjälä
---
tests/drv_hangman.c | 4 ++--
tests/eviction_common.c | 5 +
tests/gem_seqno_wrap.c | 5 +
tests/gem_stress.c | 7 ++-
tests/kms_flip.c| 12 +++-
5 fi
From: Ville Syrjälä
Replace open coded min/max/swap with the macro invocation.
Signed-off-by: Ville Syrjälä
---
lib/igt.cocci | 36
1 file changed, 36 insertions(+)
diff --git a/lib/igt.cocci b/lib/igt.cocci
index adebb31..0d337bf 100644
--- a/lib/igt.cocc
From: Ville Syrjälä
swap() will swap its two arguments while keeping the required
tmp variable hidden. Makes for neater code.
Signed-off-by: Ville Syrjälä
---
lib/igt_aux.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/lib/igt_aux.h b/lib/igt_aux.h
index 6c83c53..63e1b06 100644
---
Hi all,
New -testing cycle with cool stuff, first round for 3.20 - hah no typo this
time around in the version ;-)
- dual-dsi enabling from Gaurav with prep work from Jani
- reshuffling the ring init code to move towards a clean sw/hw state setup split
- ring free space refactoring from Dave Gordo
On Fri, Dec 05, 2014 at 02:38:46PM +, Chris Wilson wrote:
> On Fri, Dec 05, 2014 at 04:31:35PM +0200, Ville Syrjälä wrote:
> > On Fri, Dec 05, 2014 at 02:15:22PM +, Chris Wilson wrote:
> > > Currently we initialise the rings, add the first context switch to the
> > > ring and execute our go
On Fri, Dec 05, 2014 at 02:38:46PM +, Chris Wilson wrote:
> On Fri, Dec 05, 2014 at 04:31:35PM +0200, Ville Syrjälä wrote:
> > On Fri, Dec 05, 2014 at 02:15:22PM +, Chris Wilson wrote:
> > > Currently we initialise the rings, add the first context switch to the
> > > ring and execute our go
On Fri, Dec 05, 2014 at 01:14:40PM +, Chris Wilson wrote:
> +static void assert_empty(int fd)
> +{
> + struct pollfd pfd = {fd, POLLIN };
> + igt_assert(poll(&pfd, 1, 0) == 0);
> +}
> +
> +static void generate_event(int fd)
> +{
> + union drm_wait_vblank vbl;
> +
> + /* We assum
On Thu, Dec 04, 2014 at 05:25:56PM +0200, Ville Syrjälä wrote:
> On Thu, Dec 04, 2014 at 03:07:52PM +, Michel Thierry wrote:
> > We already have it for chv, but was missing for bdw.
> >
> > Signed-off-by: Michel Thierry
> > ---
> > drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
> > 1 file c
On Fri, Dec 05, 2014 at 04:31:35PM +0200, Ville Syrjälä wrote:
> On Fri, Dec 05, 2014 at 02:15:22PM +, Chris Wilson wrote:
> > Currently we initialise the rings, add the first context switch to the
> > ring and execute our golden state then enable (aliasing or full) ppgtt.
> > However, as we en
On Fri, Dec 05, 2014 at 06:20:43PM +0530, Singh, Gaurav K wrote:
>
> On 12/4/2014 4:52 PM, Daniel Vetter wrote:
> >On Thu, Dec 04, 2014 at 11:14:01AM +0200, Jani Nikula wrote:
> >>On Thu, 04 Dec 2014, Gaurav K Singh wrote:
> >>>This patch is in preparation of DSI dual link panels. For dual link
>
On Fri, Dec 05, 2014 at 02:15:22PM +, Chris Wilson wrote:
> Currently we initialise the rings, add the first context switch to the
> ring and execute our golden state then enable (aliasing or full) ppgtt.
> However, as we enable ppgtt using direct MMIO but load the PD using
> MI_LRI, we end up
When setting the calculated middle frequency value the test assumes that
the HW/kernel rounds this value according to a 50MHz step value. This is
not so at least on VLV/CHV, on my B0 BYT-M for example this step value
is 22MHz, so there the test will fail.
To fix this get the nearest supported valu
On Fri, Dec 05, 2014 at 03:23:59PM +0200, Imre Deak wrote:
> Hm, right I should have checked that first. And it could be also the
> reason why AZX_DCAPS_I915_POWERWELL was left out for everything but
> HSW/BDW. I will send a patch to fix that in i915.
Not terribly in favour of perpetuing that hack
On Fri, Dec 05, 2014 at 12:11:45PM +, Tvrtko Ursulin wrote:
> +struct i915_ggtt_view {
> + enum i915_ggtt_view_type type;
> +
> + struct sg_table *pages;
> +};
Minor nit on semantics, not really worth a resend (except when you need
one anyway because of the detailed review): Imo the sg
On Sandybridge+, the GPU provides the ERROR register for detecting page
faults. Hook this up to our hangcheck so that we can dump the error
state soon after such an event occurs. This would be better inside an
interrupt handler, but it serves a purpose here as it detects that our
initial context se
Currently we initialise the rings, add the first context switch to the
ring and execute our golden state then enable (aliasing or full) ppgtt.
However, as we enable ppgtt using direct MMIO but load the PD using
MI_LRI, we end up executing the context switch and golden render state
with an invalid P
On Fri, Dec 05, 2014 at 05:03:14AM -0800, Jeremiah Mahler wrote:
> Jani,
>
> On Fri, Dec 05, 2014 at 02:17:42PM +0200, Jani Nikula wrote:
> > Release struct_mutex if init_rings() fails.
> >
> > This is a regression introduced in
> > commit 35a57ffbb10840af219eeaf64718434242bb7c76
> > Author: Dani
On Fri, 2014-12-05 at 15:28 +0200, Imre Deak wrote:
> So far we only allowed HSW and BDW to request for the audio power
> domain, but it is also needed at least on VLV/CHV. There is no need
> for this restriction, since the power domain->power well mapping should
> take care of the distinctions bet
On Fri, Dec 05, 2014 at 09:50:21AM +0100, Gerd Hoffmann wrote:
> >
> > https://www.usenix.org/conference/atc14/technical-sessions/presentation/tian
>
> /me goes read this.
>
> A few comments on the kernel stuff (brief look so far, also
> compile-tested only, intel gfx on my test machine is t
From: John Harrison
Added the request structure's 'uniq' identifier to the trace information. Also
renamed the '_complete' trace event to '_notify' as it actually happens in the
IRQ 'notify_ring()' function. The intention is to add a new '_complete' trace
event which occurs when a request structu
From: John Harrison
For debugging purposes, it is useful to be able to uniquely identify a given
request structure as it works its way through the system. This becomes
especially tricky once the seqno value is lazily allocated as then the request
has nothing but its pointer to identify it for muc
From: John Harrison
There is a general theory that kzmalloc is better/safer than kmalloc, especially
for interesting data structures. This change updates the request structure
allocation to be zero filled.
Change-Id: I68715ef758025fab8db763941ef63bf60d7031e2
For: VIZ-4377
Signed-off-by: John Har
From: John Harrison
There is a general feeling that it is better to move away from using a simple
integer 'seqno' value to track batch buffer completion. Instead, the request
structure should be used. That provides for much more flexibility going
forwards. Especially which things like a GPU sched
From: John Harrison
The display related patches earlier in this series were edited during merge to
improve the request unreferencing. Specifically, the need for de-referencing at
interrupt time was removed. However, the resulting code did a 'deref(req) ; req
= NULL' sequence rather than using the
On Fri, Dec 05, 2014 at 03:32:30PM +0200, Mika Kuoppala wrote:
> Copy a block into a destination object with varying base offset
> into the destination and source. Put guard area before and after
> the blit target to see that it didn't touch memory out of
> blit boundaries.
This doesn't belong in
Copy a block into a destination object with varying base offset
into the destination and source. Put guard area before and after
the blit target to see that it didn't touch memory out of
blit boundaries.
References: https://bugs.freedesktop.org/show_bug.cgi?id=79053
Cc: Chris Wilson
Signed-off-by
So far we only allowed HSW and BDW to request for the audio power
domain, but it is also needed at least on VLV/CHV. There is no need
for this restriction, since the power domain->power well mapping should
take care of the distinctions between platforms.
Spotted-by: Jani Nikula
Signed-off-by: Imr
On Fri, 2014-12-05 at 13:57 +0200, Jani Nikula wrote:
> On Fri, 05 Dec 2014, Imre Deak wrote:
> > On Fri, 2014-12-05 at 10:37 +0200, Jani Nikula wrote:
> >> On Fri, 05 Dec 2014, Clint Taylor wrote:
> >> > On 12/04/2014 11:08 AM, Clint Taylor wrote:
> >> >> On 12/04/2014 12:41 AM, Jani Nikula wrot
On Fri, Dec 05, 2014 at 08:55:59AM +0800, weiyj...@163.com wrote:
> From: Wei Yongjun
>
> Add the missing unlock before return from function i915_gem_init_hw()
> in the error handling case.
>
> Signed-off-by: Wei Yongjun
Applied, thanks for the patch. Two minor comments:
- Please mention the c
Check that the more obvious userspace error conditions are handled by
the kernel, ideally without loss of data. These include nonblocking
waits, passing invalid buffers and passing buffers of the incorrect
length.
Signed-off-by: Chris Wilson
---
tests/.gitignore | 1 +
tests/Makefile.sou
On Tue, 02 Dec 2014, "Eoff, Ullysses A" wrote:
> bump
Talked about this with Daniel a while back, his take was, "preemptively
catering to bonghits userspace means we'll have less wiggle-room in the
future"
BR,
Jani.
>
>> -Original Message-
>> From: Intel-gfx [mailto:intel-gfx-boun...@l
On 05/12/2014 09:50, Gerd Hoffmann wrote:
> A few comments on the kernel stuff (brief look so far, also
> compile-tested only, intel gfx on my test machine is too old).
>
> * Noticed the kernel bits don't even compile when configured as
>module. Everything (vgt, i915, kvm) must be compiled
Jani,
On Fri, Dec 05, 2014 at 02:17:42PM +0200, Jani Nikula wrote:
> Release struct_mutex if init_rings() fails.
>
> This is a regression introduced in
> commit 35a57ffbb10840af219eeaf64718434242bb7c76
> Author: Daniel Vetter
> Date: Thu Nov 20 00:33:07 2014 +0100
>
> drm/i915: Only init
On Fri, 05 Dec 2014, Gaurav K Singh wrote:
> For Dual Link MIPI Panels, both Port A and Port C should be enabled
> during the MIPI encoder enabling sequence. Similarly, during the
> disabling sequence, both ports needs to be disabled.
>
> v2: Used for_each_dsi_port macro instead of for loop
>
> v3
On Fri, Nov 14, 2014 at 06:16:56PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> MI_STORE_DWORD_IMM length has been the same ever since gen4. Rename
> the define to avoid potential confusion if someone tries to use this
> on pre-gen8.
>
> Also correct the comment on MI_ME
On 12/4/2014 4:52 PM, Daniel Vetter wrote:
On Thu, Dec 04, 2014 at 11:14:01AM +0200, Jani Nikula wrote:
On Thu, 04 Dec 2014, Gaurav K Singh wrote:
This patch is in preparation of DSI dual link panels. For dual link
panels, few packets needs to be sent to Port A or Port C or both. Based
on the
Release struct_mutex if init_rings() fails.
This is a regression introduced in
commit 35a57ffbb10840af219eeaf64718434242bb7c76
Author: Daniel Vetter
Date: Thu Nov 20 00:33:07 2014 +0100
drm/i915: Only init engines once
Reported-by: Wei Yongjun
Signed-off-by: Jani Nikula
---
drivers/gpu
On Fri, 05 Dec 2014, Jeremiah Mahler wrote:
> There are other places in i915_gem_init_hw() where it returns without
> unlocking the mutex. Why is it only necessary here and not any of the
> other places?
There's probably some rebase/merge confusion going on. The following
patch is against drm-in
On Fri, 05 Dec 2014, Jeremiah Mahler wrote:
> There are other places in i915_gem_init_hw() where it returns without
> unlocking the mutex. Why is it only necessary here and not any of the
> other places?
There's probably some rebase/merge confusion going on. The following
patch is against drm-in
1 - 100 of 120 matches
Mail list logo
