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On Wed, Nov 19, 2014 at 05:47:14PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> Which means the list doesn't really need to know if the event is from
> user space or kernel space.
>
> The only place here where we have to break the abstraction is at
> drm_fops, when we're releasing all the
On Wed, Nov 19, 2014 at 05:47:11PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> It's supposed to contain all the information that is required for both
> kernel and user space vblank wait items, but not hold any information
> required by just one of them.
>
> For now, we just moved the str
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From: Wei Yongjun
Add the missing unlock before return from function i915_gem_init_hw()
in the error handling case.
Signed-off-by: Wei Yongjun
---
drivers/gpu/drm/i915/i915_gem.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gp
On Wed, Nov 19, 2014 at 05:47:10PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> This is going to be needed by i915.ko, and I guess other drivers could
> use it too.
You may want to explain what we plan to use this for in i915 so that
other driver developers will more easily see where it m
Mario Kleiner writes:
> Pageflips for Pixmap presents were not synchronized to vblank on
> drivers with support for PresentCapabilityAsync, due to some
> missing init for vblank->sync_flips. The PresentOptionAsync
> flag was completely ignored for pageflipped presents.
>
> Vsynced flips only work
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On 12/04/2014 11:08 AM, Clint Taylor wrote:
On 12/04/2014 12:41 AM, Jani Nikula wrote:
On Wed, 03 Dec 2014, Clint Taylor wrote:
On 12/03/2014 01:01 PM, Ville Syrjälä wrote:
On Wed, Dec 03, 2014 at 10:10:30AM -0800, clinton.a.tay...@intel.com
wrote:
From: Clint Taylor
Added PIPE C register
Let's be optimistic that for future platforms this will remain the same
and reorg a bit.
This reorg in if blocks instead of switch make life easier for future
platform support addition.
v2: Jani pointed out I was missing reg_830 for some gen3 platforms. So let's
make
this platforms subcases o
The current implementation of drm_read() faces a number of issues:
1. Upon an error, it consumes the event which may lead to the client
blocking.
2. Upon an error, it forgets about events already copied
3. If it fails to copy a single event with O_NONBLOCK it falls into a
infinite loop of reportin
On Mon, 1 Dec 2014 09:54:28 -0800
Jesse Barnes wrote:
> Partial revert of
>
> commit 206645910b9796bff13fcdb67bdca166b724ba62
> Author: Jesse Barnes
> Date: Wed Nov 5 14:26:09 2014 -0800
>
> drm/i915: check for audio and infoframe changes across mode sets
> v2
>
> References: https://b
On Thu, Dec 4, 2014 at 10:51 AM, Daniel Vetter wrote:
> On Thu, Dec 4, 2014 at 7:16 PM, John Stultz wrote:
>> On Thu, Dec 4, 2014 at 9:50 AM, Daniel Vetter wrote:
>>> On Thu, Dec 4, 2014 at 6:42 PM, John Stultz wrote:
Sigh. So you're going to make me write a separate patch that moves it ov
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On Dec 4, 2014 5:27 AM, "Jike Song" wrote:
>
> Hi all,
Hi,
>
> We are pleased to announce the first release of KVMGT project. KVMGT is
the implementation of Intel GVT-g technology, a full GPU virtualization
solution. Under Intel GVT-g, a virtual GPU instance is maintained for each
VM, with part o
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On 12/04/2014 12:41 AM, Jani Nikula wrote:
On Wed, 03 Dec 2014, Clint Taylor wrote:
On 12/03/2014 01:01 PM, Ville Syrjälä wrote:
On Wed, Dec 03, 2014 at 10:10:30AM -0800, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
Added PIPE C register support for CHV audio programming.
nak. The
On Thu, Dec 4, 2014 at 7:16 PM, John Stultz wrote:
> On Thu, Dec 4, 2014 at 9:50 AM, Daniel Vetter wrote:
>> On Thu, Dec 4, 2014 at 6:42 PM, John Stultz wrote:
>>> Sigh. So you're going to make me write a separate patch that moves it over?
>>
>> We've written it already, Imre posted the link to
If we extend the commit_plane handlers for each plane type to be able to
handle fb=0, then we can easily implement plane disable via the
update_plane handler. The cursor plane already works this way, and this
is the direction we need to go to integrate with the atomic plane
handler. We can now ki
On Thu, Dec 4, 2014 at 9:50 AM, Daniel Vetter wrote:
> On Thu, Dec 4, 2014 at 6:42 PM, John Stultz wrote:
>> Sigh. So you're going to make me write a separate patch that moves it over?
>
> We've written it already, Imre posted the link to the old discussion:
>
> https://lkml.org/lkml/2013/5/10/18
Greetings Daniel and the other maintainers,
I am wondering if you have access to the hardware spec for these drivers
supported by this header file. If you do
I would really appreciate the correct values for the registers pasted below as
the person who wrote this code,
stated he guessed them. Due
On Thu, Dec 4, 2014 at 6:42 PM, John Stultz wrote:
> On Thu, Dec 4, 2014 at 2:42 AM, Daniel Vetter wrote:
>> On Wed, Dec 03, 2014 at 11:07:08AM -0800, John Stultz wrote:
>>> On Wed, Dec 3, 2014 at 6:30 AM, Daniel Vetter wrote:
>>> > On Tue, Dec 02, 2014 at 08:54:13AM -0800, John Stultz wrote:
>>
On Thu, Dec 4, 2014 at 2:12 AM, Daniel Vetter wrote:
> We've lost the +1 required for correct timeouts in
>
> commit 5ed0bdf21a85d78e04f89f15ccf227562177cbd9
> Author: Thomas Gleixner
> Date: Wed Jul 16 21:05:06 2014 +
>
> drm: i915: Use nsec based interfaces
>
> Use ktime_get_raw_n
On Thu, Dec 4, 2014 at 2:42 AM, Daniel Vetter wrote:
> On Wed, Dec 03, 2014 at 11:07:08AM -0800, John Stultz wrote:
>> On Wed, Dec 3, 2014 at 6:30 AM, Daniel Vetter wrote:
>> > On Tue, Dec 02, 2014 at 08:54:13AM -0800, John Stultz wrote:
>> >> On Tue, Dec 2, 2014 at 8:35 AM, Chris Wilson
>> >>
On Wed, Nov 19, 2014 at 8:47 PM, Paulo Zanoni wrote:
>
> 2. How should the driver interface look like?
>
>a. All the possibilities are passed through the function call, so the
> drm.ko
> code needs to set the struct members itself.
>b. The caller already sets the struct members ins
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On Thu, Dec 04, 2014 at 04:18:39PM +, Chris Wilson wrote:
> On Thu, Dec 04, 2014 at 01:58:54PM +, Damien Lespiau wrote:
> > Here is a cheap way for this test to give consistent results. This
> > doesn't change the usefulness of this test, hopefully.
> >
> > Signed-off-by: Damien Lespiau
>
As described in the code comment, I couldn't set the minimum RPS
frequency on my BYT-M B0 to the minimum allowed as reported by Punit.
Fix this by clamping the minimum value to the first one that was
accepted on my machine. This fixes at least the pm_rpm basic-api and
min-max-config subtests.
Test
On Thu, Dec 04, 2014 at 06:09:40PM +0200, Imre Deak wrote:
> Atm the test assumes that the calculated middle frequency point is
> supported by the HW, but it's not so at least on VLV. On my B0
> BYT-M there is a 22MHz step between the allowed values, so the test will
> fail trying to set the calcul
On Thu, Dec 04, 2014 at 01:58:54PM +, Damien Lespiau wrote:
> Here is a cheap way for this test to give consistent results. This
> doesn't change the usefulness of this test, hopefully.
>
> Signed-off-by: Damien Lespiau
> ---
> tests/gem_bad_reloc.c | 8 +++-
> 1 file changed, 7 insertio
Atm the test assumes that the calculated middle frequency point is
supported by the HW, but it's not so at least on VLV. On my B0
BYT-M there is a 22MHz step between the allowed values, so the test will
fail trying to set the calculated middle freq that isn't aligned to
this.
To fix this get the n
At least on VLV when forcing a new GT frequency by writing to the
min/max freq sysfs entries the kernel doesn't wait until the new
frequency settles, so the subsequent readback check might fail. To fix
this wait until the current frequency is between the min/max values
using a 10ms timeout.
Signed
While checking my latest RPS patchset, this test was failing on VLV, so
I went ahead and fixed a couple of issues I found. With these fixes and
a related kernel change to fix the VLV minimum frequency value the
basic-api and min-max-config subtests are passing for me on VLV.
The reset and blocking
When changing the sysfs GT min/max frequencies, the kernel won't
explicitly change the current frequency, unless it becomes out of bound
based on the new min/max values. The test happens to work on non-VLV
platforms because on those the kernel resets the current frequency
unconditionally (to adjust
We already have it for chv, but was missing for bdw.
v2: Label WaForceEnableNonCoherent (Ville)
Cc: Ville Syrjälä
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/
On 12/4/2014 3:25 PM, Ville Syrjälä wrote:
On Thu, Dec 04, 2014 at 03:07:52PM +, Michel Thierry wrote:
We already have it for chv, but was missing for bdw.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/dri
On Thu, Dec 04, 2014 at 03:07:52PM +, Michel Thierry wrote:
> We already have it for chv, but was missing for bdw.
>
> Signed-off-by: Michel Thierry
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuff
We already have it for chv, but was missing for bdw.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 788e1b6..91ddcd1 100644
--
On Thu, 4 Dec 2014 12:21:01 +0100
Daniel Vetter wrote:
> On Wed, Dec 03, 2014 at 11:49:06AM -0800, Jesse Barnes wrote:
> > Expose an ioctl to create Android fences based on the Android sync point
> > infrastructure (which in turn is based on DMA-buf fences). Just a
> > sketch at this point, no t
On Thu, 2014-12-04 at 14:58 +0100, Daniel Vetter wrote:
> On Thu, Dec 04, 2014 at 02:59:32PM +0200, Imre Deak wrote:
> > Atm, we don't disable RPS interrupts and related work items before
> > resetting the GPU. This may interfere with the following GPU
> > initialization and cause RPS interrupts to
On Thu, Dec 04, 2014 at 01:58:54PM +, Damien Lespiau wrote:
> Here is a cheap way for this test to give consistent results. This
> doesn't change the usefulness of this test, hopefully.
>
> Signed-off-by: Damien Lespiau
And:
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85270
--
Here is a cheap way for this test to give consistent results. This
doesn't change the usefulness of this test, hopefully.
Signed-off-by: Damien Lespiau
---
tests/gem_bad_reloc.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/tests/gem_bad_reloc.c b/tests/gem_bad_reloc
On Thu, Dec 04, 2014 at 02:59:32PM +0200, Imre Deak wrote:
> Atm, we don't disable RPS interrupts and related work items before
> resetting the GPU. This may interfere with the following GPU
> initialization and cause RPS interrupts to show up in PM_IIR too early
> before calling gen6_enable_rps_in
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On Thu, Dec 4, 2014 at 1:17 PM, Tvrtko Ursulin
wrote:
> I looked at propagating errors from i915_vma_bind() out to callers and it is
> mostly all fine apart from the i915_gem_restore_gtt_mappings during
> i915_drm_resume.
Bummer.
> I don't see how this is fixable apart by going back and having s
Atm, we don't disable RPS interrupts and related work items before
resetting the GPU. This may interfere with the following GPU
initialization and cause RPS interrupts to show up in PM_IIR too early
before calling gen6_enable_rps_interrupts() (triggering a WARN there).
Solve this by disabling RPS
Paulo noticed that we don't enable RPS interrupts via PM_IER in
gen6_enable_rps_interrupts(). This wasn't a problem so far, since the
only place we disabled RPS interrupts was during system/runtime suspend
and after that we reenable all interrupts in the IRQ pre/postinstall
hooks.
In the next patc
This is v2 of patchset [1], with one issue fixed that was noticed by
Paulo. Patch 1/1 of the original patchset is already merged.
[1]
http://lists.freedesktop.org/archives/intel-gfx/2014-November/055969.html
Imre Deak (2):
drm/i915: move RPS PM_IER enabling to gen6_enable_rps_interrupts
drm/i
On Thu, Dec 4, 2014 at 12:29 PM, Chris Wilson wrote:
> It uses locked atomic operations, which are unnecessary for the very
> frequent is-complete checks (due to the nice ordering constraints of x86).
So let's look at the fastpaths:
- fence already signaled: Just a test_bit which amounts to a nor
On Thu, Dec 04, 2014 at 12:17:51PM +, Tvrtko Ursulin wrote:
> On 12/04/2014 10:59 AM, Daniel Vetter wrote:
> >On Thu, Dec 04, 2014 at 10:26:14AM +, Chris Wilson wrote:
> >>On Thu, Dec 04, 2014 at 10:19:09AM +, Tvrtko Ursulin wrote:
> >>>
> >>>On 12/04/2014 09:53 AM, Chris Wilson wrote:
On 12/04/2014 10:59 AM, Daniel Vetter wrote:
On Thu, Dec 04, 2014 at 10:26:14AM +, Chris Wilson wrote:
On Thu, Dec 04, 2014 at 10:19:09AM +, Tvrtko Ursulin wrote:
On 12/04/2014 09:53 AM, Chris Wilson wrote:
On Wed, Dec 03, 2014 at 02:59:25PM +, Tvrtko Ursulin wrote:
+void i915_vm
On Thu, 04 Dec 2014, Gaurav K Singh wrote:
> We need to program both port registers during dual link enable path.
>
> v2: Address review comments by Jani
> - Used a for loop instead of do-while loop.
>
> v3: Used for_each_dsi_port macro instead of for loop
>
> Signed-off-by: Gaurav K Singh
>
At Thu, 4 Dec 2014 11:21:47 +,
Chris Wilson wrote:
>
> On Thu, Dec 04, 2014 at 11:53:05AM +0100, Takashi Iwai wrote:
> > At Wed, 3 Dec 2014 18:31:45 +,
> > Chris Wilson wrote:
> > >
> > > On Wed, Dec 03, 2014 at 03:45:35PM +0100, Takashi Iwai wrote:
> > > > Hi,
> > > >
> > > > while chec
On Thu, 04 Dec 2014, Gaurav K Singh wrote:
> We need to program both port registers during dual link disable path.
>
> v2: Address review comments by Jani
> - Used a for loop instead of do-while loop.
>
> v3: Used for_each_dsi_port macro instead of for loop
>
> Signed-off-by: Gaurav K Singh
>
On Thu, Dec 04, 2014 at 12:05:34PM +0100, Daniel Vetter wrote:
> On Thu, Dec 04, 2014 at 09:13:21AM +, Chris Wilson wrote:
> > On Wed, Dec 03, 2014 at 11:49:07AM -0800, Jesse Barnes wrote:
> > > This simplifies the sync code quite a bit. I don't think we'll be able
> > > to get away with using
On Thu, 04 Dec 2014, Gaurav K Singh wrote:
> hactive, hfp, hbp, hsync needs to be halved for dual link MIPI Panels.
> Accordingly timing related mmio regs needs to be programmed for both MIPI
> Ports.
>
> v2: Address review comments by Jani
> - Used a for loop instead of do-while loop
>
> v3:
On Thu, 04 Dec 2014, Gaurav K Singh wrote:
> Instead of pipe configuration reg, cck reg to be used for checking whether
> DSI Pll is getting locked or not.
>
> Signed-off-by: Gaurav K Singh
> Signed-off-by: Shobhit Kumar
> ---
> drivers/gpu/drm/i915/intel_dsi_pll.c |5 +++--
> 1 file change
On Thu, Dec 04, 2014 at 11:14:01AM +0200, Jani Nikula wrote:
> On Thu, 04 Dec 2014, Gaurav K Singh wrote:
> > This patch is in preparation of DSI dual link panels. For dual link
> > panels, few packets needs to be sent to Port A or Port C or both. Based
> > on the portno from MIPI Sequence Block#5
On Thu, Dec 04, 2014 at 11:53:05AM +0100, Takashi Iwai wrote:
> At Wed, 3 Dec 2014 18:31:45 +,
> Chris Wilson wrote:
> >
> > On Wed, Dec 03, 2014 at 03:45:35PM +0100, Takashi Iwai wrote:
> > > Hi,
> > >
> > > while checking the reported bug about VT switch hang on openSUSE 13.2,
> > > I also
On Wed, Dec 03, 2014 at 11:49:06AM -0800, Jesse Barnes wrote:
> Expose an ioctl to create Android fences based on the Android sync point
> infrastructure (which in turn is based on DMA-buf fences). Just a
> sketch at this point, no testing has been done.
>
> There are a couple of goals here:
>
gem_gpgpu_fill was added in commit 4ec8479 (tests: Add gem_gpgpu_fill),
but wasn't added to .gitignore.
Cc: Zhenyu Wang
Signed-off-by: Thomas Wood
---
tests/.gitignore | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/.gitignore b/tests/.gitignore
index 6e6ab58..a846cb3 100644
--- a/tes
On Thu, 04 Dec 2014, Gaurav K Singh wrote:
> For Dual link MIPI Panels, dsipll clock for both DSI0 and DSI1 needs to be
> enabled.
>
> v2: Address review comments by Jani
> - Added wait time for PLL to be locked.
>
> v3: separate patch created for cck read for checking PLL to be locked
>
> Si
On Thu, Dec 04, 2014 at 12:58:40PM +0200, Ville Syrjälä wrote:
> On Wed, Dec 03, 2014 at 07:15:31PM +, Arun Siluvery wrote:
> > These w/a were recently identified while debugging another issue,
> > +WaClearFlowControlGpgpuContextSave:chv
> > +Wa4x4STCOptimizationDisable:chv
> >
> > For: VIZ-40
On Thu, Dec 04, 2014 at 09:13:21AM +, Chris Wilson wrote:
> On Wed, Dec 03, 2014 at 11:49:07AM -0800, Jesse Barnes wrote:
> > This simplifies the sync code quite a bit. I don't think we'll be able
> > to get away with using the core fence code's seqno support, since we'll
> > be moving away fr
On Wed, Dec 03, 2014 at 10:19:24PM +0200, Ville Syrjälä wrote:
> On Wed, Dec 03, 2014 at 05:33:24PM +, Damien Lespiau wrote:
> > When playing around with debugfs and a HSW machine I noticed that we
> > were displaying some garbled value in i915_ddb_info. This debugfs file
> > is only meaningful
On 3 December 2014 at 14:22, Daniel Vetter wrote:
> On Tue, Dec 02, 2014 at 05:15:37PM +, Thomas Wood wrote:
> > diff --git a/lib/igt_core.h b/lib/igt_core.h
> > index a258348..5c5ee25 100644
> > --- a/lib/igt_core.h
> > +++ b/lib/igt_core.h
> > @@ -512,16 +512,20 @@ bool igt_run_in_simulatio
On Wed, Dec 03, 2014 at 07:15:31PM +, Arun Siluvery wrote:
> These w/a were recently identified while debugging another issue,
> +WaClearFlowControlGpgpuContextSave:chv
> +Wa4x4STCOptimizationDisable:chv
>
> For: VIZ-4090
> Change-Id: I08d2176dec609396c3a7c2e48b2413e233799fc4
> Signed-off-by:
On Thu, Dec 04, 2014 at 10:26:14AM +, Chris Wilson wrote:
> On Thu, Dec 04, 2014 at 10:19:09AM +, Tvrtko Ursulin wrote:
> >
> > On 12/04/2014 09:53 AM, Chris Wilson wrote:
> > >On Wed, Dec 03, 2014 at 02:59:25PM +, Tvrtko Ursulin wrote:
> > >>+void i915_vma_bind(struct i915_vma *vma, e
On Thu, Dec 04, 2014 at 09:48:11AM +, Chris Wilson wrote:
> On Wed, Dec 03, 2014 at 02:59:24PM +, Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin
> >
> > Multiple GGTT VMAs per object will be introduced in the near future which
> > will
> > make it impossible to guarantee normal GGTT view
At Wed, 3 Dec 2014 18:31:45 +,
Chris Wilson wrote:
>
> On Wed, Dec 03, 2014 at 03:45:35PM +0100, Takashi Iwai wrote:
> > Hi,
> >
> > while checking the reported bug about VT switch hang on openSUSE 13.2,
> > I also could reproduce a similar issue as reported: namely, X hangs
> > when repeated
On 12/04/2014 10:39 AM, Chris Wilson wrote:
On Thu, Dec 04, 2014 at 10:30:30AM +, Tvrtko Ursulin wrote:
So personally you don't think it should be of any concern if a GGTT
VMA is at the head of the list, but it is not the same GGTT VMA
which you would find there in majority of cases?
Actu
On Thu, Dec 04, 2014 at 09:11:10AM +, Chris Wilson wrote:
> On Wed, Dec 03, 2014 at 03:16:09PM +0100, Daniel Vetter wrote:
> > On Tue, Dec 02, 2014 at 04:46:38PM +, Chris Wilson wrote:
> > > On Tue, Dec 02, 2014 at 04:19:43PM +0100, Daniel Vetter wrote:
> > > > /* Generate a semi-unique er
We've lost the +1 required for correct timeouts in
commit 5ed0bdf21a85d78e04f89f15ccf227562177cbd9
Author: Thomas Gleixner
Date: Wed Jul 16 21:05:06 2014 +
drm: i915: Use nsec based interfaces
Use ktime_get_raw_ns() and get rid of the back and forth timespec
conversions.
On Wed, Dec 03, 2014 at 11:07:08AM -0800, John Stultz wrote:
> On Wed, Dec 3, 2014 at 6:30 AM, Daniel Vetter wrote:
> > On Tue, Dec 02, 2014 at 08:54:13AM -0800, John Stultz wrote:
> >> On Tue, Dec 2, 2014 at 8:35 AM, Chris Wilson
> >> wrote:
> >> > On Tue, Dec 02, 2014 at 04:36:22PM +0100, Dani
On Thu, 04 Dec 2014, Gaurav K Singh wrote:
> For dual link MIPI panels, SHUTDOWN packet needs to send to both Ports
> A & C during MIPI encoder disabling sequence. Similarly, TURN ON packet
> to be sent to both Ports during MIPI encoder enabling sequence.
>
> v2: Address review comments by Jani
>
On Thu, Dec 04, 2014 at 10:30:30AM +, Tvrtko Ursulin wrote:
>
> On 12/04/2014 10:17 AM, Chris Wilson wrote:
> >On Thu, Dec 04, 2014 at 10:02:19AM +, Tvrtko Ursulin wrote:
> >>
> >>On 12/04/2014 09:48 AM, Chris Wilson wrote:
> >>>On Wed, Dec 03, 2014 at 02:59:24PM +, Tvrtko Ursulin wrot
On 12/04/2014 10:17 AM, Chris Wilson wrote:
On Thu, Dec 04, 2014 at 10:02:19AM +, Tvrtko Ursulin wrote:
On 12/04/2014 09:48 AM, Chris Wilson wrote:
On Wed, Dec 03, 2014 at 02:59:24PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Multiple GGTT VMAs per object will be introduced in t
On Thu, Dec 04, 2014 at 10:19:09AM +, Tvrtko Ursulin wrote:
>
> On 12/04/2014 09:53 AM, Chris Wilson wrote:
> >On Wed, Dec 03, 2014 at 02:59:25PM +, Tvrtko Ursulin wrote:
> >>+void i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
> >>+ u32 flags)
> >>+{
>
On 12/04/2014 09:53 AM, Chris Wilson wrote:
On Wed, Dec 03, 2014 at 02:59:25PM +, Tvrtko Ursulin wrote:
+void i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
+ u32 flags)
+{
+ struct sg_table *pages = i915_ggtt_view_pages(vma);
+
+ if (pag
On Thu, Dec 04, 2014 at 10:02:19AM +, Tvrtko Ursulin wrote:
>
> On 12/04/2014 09:48 AM, Chris Wilson wrote:
> >On Wed, Dec 03, 2014 at 02:59:24PM +, Tvrtko Ursulin wrote:
> >>From: Tvrtko Ursulin
> >>
> >>Multiple GGTT VMAs per object will be introduced in the near future which
> >>will
On 12/04/2014 09:48 AM, Chris Wilson wrote:
On Wed, Dec 03, 2014 at 02:59:24PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Multiple GGTT VMAs per object will be introduced in the near future which will
make it impossible to guarantee normal GGTT view is at the head of the list.
Purpose
Hi Dave,
Fixes for 3.20. I did stick the gen3/4 reset work from Ville in because we
have an awful lot of gen4 mesa hangs, and with this reset should also work
on vintage i965g/gm (we already have reset for g4x/gen4.5). So should help
to appease users suffering from these hangs. Otherwise all over.
On Wed, Dec 03, 2014 at 02:59:25PM +, Tvrtko Ursulin wrote:
> +void i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
> +u32 flags)
> +{
> + struct sg_table *pages = i915_ggtt_view_pages(vma);
> +
> + if (pages && !IS_ERR(pages)) {
> + vm
On Wed, Dec 03, 2014 at 02:59:24PM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Multiple GGTT VMAs per object will be introduced in the near future which will
> make it impossible to guarantee normal GGTT view is at the head of the list.
>
> Purpose of this patch is to break this assu
On Thu, 04 Dec 2014, Gaurav K Singh wrote:
> For dual link MIPI Panels, each port needs half of pixel clock. Pixel overlap
> can be enabled if needed by panel, then in that case, pixel clock will be
> increased for extra pixels.
>
> v2 : Address review comments by Jani
> - Removed the bit mas
Hi Dave -
Silence some pch fifo underrun reports and panel locking backtraces,
both cc: stable.
BR,
Jani.
The following changes since commit 009d0431c3914de64666bec0d350e54fdd59df6a:
Linux 3.18-rc7 (2014-11-30 16:42:27 -0800)
are available in the git repository at:
git://anongit.freedes
On Thu, 04 Dec 2014, Gaurav K Singh wrote:
> For Dual Link MIPI Panels, both Port A and Port C should be enabled
> during the MIPI encoder enabling sequence. Similarly, during the
> disabling sequence, both ports needs to be disabled.
>
> v2: Used for_each_dsi_port macro instead of for loop
>
> v3
On Thu, 04 Dec 2014, Gaurav K Singh wrote:
> This patch is in preparation of DSI dual link panels. For dual link
> panels, few packets needs to be sent to Port A or Port C or both. Based
> on the portno from MIPI Sequence Block#53, these sequences needs to be
> sent accordingly.
>
> v2: Addressed
On Wed, Dec 03, 2014 at 11:49:07AM -0800, Jesse Barnes wrote:
> This simplifies the sync code quite a bit. I don't think we'll be able
> to get away with using the core fence code's seqno support, since we'll
> be moving away from simple seqno comparisions with the scheduler and
> preemption, but
On Thu, 04 Dec 2014, Gaurav K Singh wrote:
> This patch is in preparation for the DSI dual link
> port enable and disable related changes.
>
> Signed-off-by: Gaurav K Singh
> Signed-off-by: Shobhit Kumar
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 43
> +++
On Wed, Dec 03, 2014 at 03:16:09PM +0100, Daniel Vetter wrote:
> On Tue, Dec 02, 2014 at 04:46:38PM +, Chris Wilson wrote:
> > On Tue, Dec 02, 2014 at 04:19:43PM +0100, Daniel Vetter wrote:
> > > /* Generate a semi-unique error code. The code is not meant to have
> > > meaning, The
> > > @@ -
On Thu, Dec 04, 2014 at 08:10:22AM +, Chris Wilson wrote:
> If I understand correctly, the fence timeline are indeed per-ring, but
> here you set them up (and name them) on a per-engine basis.
On reflection, the timeline are per-fd, so using the engine name is not
confusing after all.
-Chris
On Wed, 03 Dec 2014, Clint Taylor wrote:
> On 12/03/2014 01:01 PM, Ville Syrjälä wrote:
>> On Wed, Dec 03, 2014 at 10:10:30AM -0800, clinton.a.tay...@intel.com wrote:
>>> From: Clint Taylor
>>>
>>> Added PIPE C register support for CHV audio programming.
>>
>> nak. The offset between the pipes lo
On Wed, Dec 03, 2014 at 11:49:06AM -0800, Jesse Barnes wrote:
> Expose an ioctl to create Android fences based on the Android sync point
> infrastructure (which in turn is based on DMA-buf fences). Just a
> sketch at this point, no testing has been done.
>
> There are a couple of goals here:
>
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