[Intel-gfx] [PATCH 1/9] drm/i915: New functions added for enabling & disabling MIPI Port Ctrl reg

This patch is in preparation for the DSI dual link port enable and disable related changes. Signed-off-by: Gaurav K Singh Signed-off-by: Shobhit Kumar --- drivers/gpu/drm/i915/intel_dsi.c | 43 -- 1 file changed, 32 insertions(+), 11 deletions(-) diff --gi

[Intel-gfx] [PATCH 4/9] drm/i915: Pixel Clock changes for DSI dual link

For dual link MIPI Panels, each port needs half of pixel clock. Pixel overlap can be enabled if needed by panel, then in that case, pixel clock will be increased for extra pixels. v2 : Address review comments by Jani - Removed the bit mask used for ->dual_link - Used DSI instead of MIPI

[Intel-gfx] [PATCH 3/9] drm/i915: Add support for port enable/disable for dual link configuration

For Dual Link MIPI Panels, both Port A and Port C should be enabled during the MIPI encoder enabling sequence. Similarly, during the disabling sequence, both ports needs to be disabled. v2: Used for_each_dsi_port macro instead of for loop Signed-off-by: Gaurav K Singh Signed-off-by: Shobhit Kuma

[Intel-gfx] [PATCH 5/9] drm/i915: Dual link needs Shutdown and Turn on packet for both ports

For dual link MIPI panels, SHUTDOWN packet needs to send to both Ports A & C during MIPI encoder disabling sequence. Similarly, TURN ON packet to be sent to both Ports during MIPI encoder enabling sequence. v2: Address review comments by Jani - Used a for loop instead of do-while loop. v3: Us

[Intel-gfx] [PATCH 0/9] BYT DSI Dual Link Support

Hi, These set of patches build on top of the existing DSI Video mode support to enable dual link MIPI panels with high resolutions. These patches have been tested on a 25x16 panel and works well. v2: Commit message added to all patches. All review comments of Jani, Nikula have been addressed in t

[Intel-gfx] [PATCH 2/9] drm/i915: Added port as parameter to the functions which does read/write of DSI Controller

This patch is in preparation of DSI dual link panels. For dual link panels, few packets needs to be sent to Port A or Port C or both. Based on the portno from MIPI Sequence Block#53, these sequences needs to be sent accordingly. Signed-off-by: Gaurav K Singh --- drivers/gpu/drm/i915/intel_dsi_cm

[Intel-gfx] [PATCH 6/9] drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link

For Dual link MIPI Panels, dsipll clock for both DSI0 and DSI1 needs to be enabled. v2: Address review comments by Jani - Added wait time for PLL to be locked. Signed-off-by: Gaurav K Singh Signed-off-by: Shobhit Kumar --- drivers/gpu/drm/i915/intel_dsi_pll.c |9 ++--- 1 file chan

[Intel-gfx] [PATCH 8/9] drm/i915: Update the DSI disable path to support dual link panel disabling

We need to program both port registers during dual link disable path. v2: Address review comments by Jani - Used a for loop instead of do-while loop. v3: Used for_each_dsi_port macro instead of for loop Signed-off-by: Gaurav K Singh Signed-off-by: Shobhit Kumar --- drivers/gpu/drm/i915/in

[Intel-gfx] [PATCH 7/9] drm/i915: MIPI Timings related changes for dual link

hactive, hfp, hbp, hsync needs to be halved for dual link MIPI Panels. Accordingly timing related mmio regs needs to be programmed for both MIPI Ports. v2: Address review comments by Jani - Used a for loop instead of do-while loop v3: Used for_each_dsi_port macro instead of for loop Signed-o

[Intel-gfx] [PATCH 9/9] drm/i915: Update the DSI enable path to support dual link panel enabling

We need to program both port registers during dual link enable path. v2: Address review comments by Jani - Used a for loop instead of do-while loop. v3: Used for_each_dsi_port macro instead of for loop Signed-off-by: Gaurav K Singh Signed-off-by: Shobhit Kumar --- drivers/gpu/drm/i915/int