On 09/24/2014 10:42 AM, Eoff, Ullysses A wrote:
>> -Original Message-
>> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
>> Of Jani Nikula
>> Sent: Wednesday, September 24, 2014 10:08 AM
>> To: Hans de Goede; Joe Konno; intel-gfx@lists.freedesktop.org
>> Subject
On Fri, 2014-11-07 at 18:42 -0200, Paulo Zanoni wrote:
> 2014-11-05 16:48 GMT-02:00 Imre Deak :
> > While fixing [1] I noticed that we can simplify a couple of things in
> > the RPS enabling/disabling code. So I did that and also fixed one WARN
> > that we can hit with some of the pm_rpm subtests.
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate
BYT: pass/total=347/348->348/348
PNV: pass/total=326/328->328
On Fri, Nov 07, 2014 at 05:45:01PM +, daniele.ceraolospu...@intel.com wrote:
> +/**
> + * DOC: execlist_submit_context tracepoint
> + *
> + * These tracepoint are used to track the contexts that are submitted to the
> + * ring. An mm switch is automatically performed by the GPU during the
> co
On Fri, Nov 07, 2014 at 02:25:38PM -0800, O'Rourke, Tom wrote:
> On Fri, Nov 07, 2014 at 10:41:26AM +, Chris Wilson wrote:
> > On Wed, Nov 05, 2014 at 05:31:34PM -0800, Tom.O'rou...@intel.com wrote:
> > > From: Tom O'Rourke
> > >
> > > Updated gen6|8_enable_rps() for Haswell and Broadwell
> >
