On Tue, Oct 28, 2014 at 7:20 AM, Jani Nikula wrote:
> In the interest of reducing magic numbers and having to cross check with
> the specs all the time.
>
> Signed-off-by: Jani Nikula
> ---
> include/drm/drm_edid.h | 102
> +
> 1 file changed, 102
Dear Daniel,
thank you for the support in #intel-...@irc.freenode.net and the patch.
As already commented in the bug report #84682, there are some typos.
Am Dienstag, den 04.11.2014, 15:29 +0100 schrieb Daniel Vetter:
> Fastboot in its current incarnation assumes that the pfit isn't
> relevatn f
On Mon, Nov 3, 2014 at 3:59 AM, Daniel Vetter wrote:
> On Thu, Oct 30, 2014 at 10:52:39AM +0200, Jani Nikula wrote:
>> On Wed, 29 Oct 2014, Rodrigo Vivi wrote:
>> > Oh, I was going to review the rest... but based on this comment I
>> > guess I might wait for a new v2 series right?
>>
>> No, I thi
On Tue, Nov 4, 2014 at 11:30 PM, Sean Paul wrote:
>> diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
>> index 89829ae58e97..ea0ef43b19e1 100644
>> --- a/Documentation/DocBook/drm.tmpl
>> +++ b/Documentation/DocBook/drm.tmpl
>> @@ -996,6 +996,10 @@ int max_width, max_he
Reviewed-by: Rodrigo Vivi
On Tue, Nov 4, 2014 at 12:30 AM, Jani Nikula wrote:
> There's some serious confusion regarding ELD valid bit that gets set and
> cleared back and forth etc. Rewrite it all based on the documented audio
> codec enable/disable sequences.
>
> v3: replace vblank wait with a
On Tue, Nov 04, 2014 at 04:51:41AM -0800, Rodrigo Vivi wrote:
> From: Deepak S
>
> Higher RC6 residency is observed using timeout mode
> instead of EI mode. It's Recommended to use TO Method for RC6.
>
[TOR:] My comments on the previous version of this patch are at
http://lists.freedesktop.org/a
On Tue, Nov 4, 2014 at 5:07 PM, Daniel Vetter wrote:
> Some differences compared to Rob's patches again:
> - Dropped the committed and checked booleans. Checking will be
> internally enforced by always calling ->atomic_check before
> ->atomic_commit. And async handling needs to be solved diffe
Add the skeleton framework for supporting automation for Displayport compliance
testing. This patch adds the necessary framework for the source device to
appropriately respond to test automation requests from a sink device.
V2:
- Addressed previous mailing list feedback
- Fixed compilation issue (
On Sun, Nov 02, 2014 at 02:19:20PM +0100, Daniel Vetter wrote:
> This is the first cut of atomic helper code. As-is it's only useful to
> implement a pure atomic interface for plane updates.
>
> Later patches will integrate this with the crtc helpers so that full
> atomic updates are possible. We a
On Tue, Nov 04, 2014 at 03:17:35PM -0700, Todd Previte wrote:
> These counters are used for Displayort compliance testing to detect error
> conditions when executing tests 4.2.2.4 and 4.2.2.5 in the Displayport Link
> CTS specificaiton. They determine whether to use the preferred/requested
> mode o
From: Armin Reese
This commit synchronizes the intel_renderstate_genx.c files in
the kernel source tree with those produced by the 'make states'
command invoking null_state_gen. Replaced manually-added
copyright headers from a previous commit.
Signed-off-by: Armin Reese
---
drivers/gpu/drm/i9
On Tue, Nov 04, 2014 at 03:12:27PM -0700, Todd Previte wrote:
> >Does it really need to be uint8_t? I see on patch 7 that you don't
> >really write this value to a place that only accepts uint8_t-sized
> >arguments, so I fear that if we get 256 NACKs or DEFERs we may end up
> >doing the wrong thing
These counters are used for Displayort compliance testing to detect error
conditions when executing tests 4.2.2.4 and 4.2.2.5 in the Displayport Link
CTS specificaiton. They determine whether to use the preferred/requested
mode or the failsafe mode during these tests.
V2:
- Addressed previous revi
To address previous feedback, I'll quote below and answer.
It would be nice if you could cite on the commit message the name of
the specification and the name of the test(s) that use it.
Done. For reference, in the Displayport Link CTS spec, tests 4.2.2.4 and
4.2.2.5 are the ones that use the
Currently there is no way to implement async flips using atomic, that
essentially requires us to be able to cancel pending requests
mid-flight.
To be able to do that (and I guess we want this since vblank synced
updates whic opportunistically cancel still pending updates seem to be
wanted) we'd ne
Well, except page_flip since that requires async commit, which isn't
there yet.
For the functions which changes planes there's a bit of trickery
involved to keep the fb refcounting working. But otherwise fairly
straight-forward atomic updates.
The property setting functions are still a bit incomp
Some differences compared to Rob's patches again:
- Dropped the committed and checked booleans. Checking will be
internally enforced by always calling ->atomic_check before
->atomic_commit. And async handling needs to be solved differently
because the current scheme completely side-steps ww m
From: Brad Volkin
This test has a few checks that batch buffer addresses in the error
state match the expected address for the userspace supplied batch.
But the batch buffer copy piece of the command parser means that
the logged addresses are actually _supposed_ to be different. So
skip just th
On 10/28/2014 1:15 AM, Daniel Vetter wrote:
On Wed, Oct 22, 2014 at 08:10:40AM -0700, Todd Previte wrote:
On 10/16/2014 11:27 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
There's no point in checking if the data lanes came out of reset after
link training. If the data lanes a
So my original plan was that the drm core refcounts framebuffers like
with the legacy ioctls. But that doesn't work for a bunch of reasons:
- State objects might live longer than until the next fb change
happens for a plane. For example delayed cleanup work only happens
_after_ the pageflip io
On Tue, Nov 04, 2014 at 10:30:37PM +0100, Daniel Vetter wrote:
> On Tue, Nov 04, 2014 at 03:31:07PM -0500, Sean Paul wrote:
> > On Sun, Nov 02, 2014 at 02:19:19PM +0100, Daniel Vetter wrote:
> > > +drm_atomic_set_crtc_for_connector(struct drm_connector_state *conn_state,
> > > + struct drm_crtc *c
Some differences compared to Rob's patches again:
- Dropped the committed and checked booleans. Checking will be
internally enforced by always calling ->atomic_check before
->atomic_commit. And async handling needs to be solved differently
because the current scheme completely side-steps ww m
On Tue, Nov 04, 2014 at 03:31:07PM -0500, Sean Paul wrote:
> On Sun, Nov 02, 2014 at 02:19:19PM +0100, Daniel Vetter wrote:
> > +drm_atomic_set_crtc_for_connector(struct drm_connector_state *conn_state,
> > + struct drm_crtc *crtc)
> > +{
> > + struct drm_crtc_state *crtc_state;
> > +
> > + crtc_s
On Sun, Nov 02, 2014 at 02:19:17PM +0100, Daniel Vetter wrote:
> I've forgotten to do this in:
>
> commit cb597bb3a2fbfc871cc1c703fb330d247bd21394
> Author: Daniel Vetter
> Date: Sun Jul 27 19:09:33 2014 +0200
>
> drm: trylock modest locking for fbdev panics
>
> Oops, fix this asap.
>
> In m
On Sun, Nov 02, 2014 at 02:19:14PM +0100, Daniel Vetter wrote:
> Just a bit of OCD cleanup on headers - this function isn't the core
> interface any more but just a helper for drivers who haven't yet
> transitioned to universal planes. Put the declaration at the right
> spot and sprinkle necessary
On Sun, Nov 02, 2014 at 02:19:19PM +0100, Daniel Vetter wrote:
> Some differences compared to Rob's patches again:
> - Dropped the committed and checked booleans. Checking will be
> internally enforced by always calling ->atomic_check before
> ->atomic_commit. And async handling needs to be sol
On Sun, Nov 02, 2014 at 02:19:18PM +0100, Daniel Vetter wrote:
> Heavily based upon Rob Clark's atomic series.
> - Dropped the connctor state from the crtc state, instead opting for a
nit: s/connctor/connector/
> full-blown connector state. The only thing it has is the desired
> crtc, but dri
This is another drm-intel-collector updated notice:
http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=drm-intel-collector
Here goes the update list in order for better reviewers assignment:
Patch drm/i915: Check the minimum pitch for the user framebuffer - Reviewer:
Patch drm/i915: M
From: Deepak S
Higher RC6 residency is observed using timeout mode
instead of EI mode. It's Recommended to use TO Method for RC6.
Signed-off-by: Deepak S
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_pm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/dri
Similar to:
commit 02c9f7e3cfe76a7f54ef03438c36aade86cc1c8b
Author: Kenneth Graunke
Date: Mon Jan 27 14:20:16 2014 -0800
drm/i915: Add the WaCsStallBeforeStateCacheInvalidate:bdw workaround.
On Broadwell, any PIPE_CONTROL with the "State Cache Invalidate" bit set
must be preceded
From: Zhipeng Gong
On Broadwell GT3 we have 2 Video Command Streamers (VCS), but userspace
has no control when using VCS1 or VCS2. This patch introduces a mechanism
to avoid the default ping-pong mode and use one specific ring through
execution flag.
v2: fix whitespace (Rodrigo)
Signed-off-by:
From: Chris Wilson
Compute the smallest pitch required for a linear framebuffer and assert
that the user has declared a pitch that meets that minimum requirement.
Signed-off-by: Chris Wilson
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_display.c | 11 +++
1 file changed,
To be used for a Workaroud. Similar to:
commit 884ceacee308f0e4616d0c933518af2639f7b1d8
Author: Kenneth Graunke
Date: Sat Jun 28 02:04:20 2014 +0300
drm/i915: Refactor Broadwell PIPE_CONTROL emission into a helper.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_lrc.c | 35 ++
From: Chris Wilson
Currently objects for which the hardware needs a contiguous physical
address are allocated a shadow backing storage to satisfy the contraint.
This shadow buffer is not wired into the normal obj->pages and so the
physical object is incoherent with accesses via the GPU, GTT and C
From: Chris Wilson
Sometimes we wish to tweak how an individual context behaves. Since we
always create a context for every filp, this means that individual
processes can fine tune their behaviour even if they do not explicitly
create a context.
The first example parameter here is to enable mult
From: Zhipeng Gong
This will let userland only try to use the new ring
when the appropriate kernel is present
Signed-off-by: Zhipeng Gong
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_dma.c | 3 +++
include/uapi/drm/i915_drm.h | 1 +
2 files changed, 4 insertions(+)
diff --gi
From: Chris Wilson
Pineview requires this. But this changes the debug API...
References: https://bugs.freedesktop.org/show_bug.cgi?id=82280
Signed-off-by: Chris Wilson
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_debugfs.c | 7 +++
1 file changed, 7 insertions(+)
diff --git
From: Chris Wilson
This will allow us to set per-file, or even per-context, periods in the
future.
Signed-off-by: Chris Wilson
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.h | 5 +
drivers/gpu/drm/i915/i915_gem.c | 3 ++-
drivers/gpu/drm/i915/i915_gem_cont
These patches got listed to -collector but got a huge conflict. If it
is still relevant please rebase it.
Also my bikeshed is to findo better names to help on differentiate
them at least.
On Wed, Sep 24, 2014 at 5:02 AM, Michel Thierry
wrote:
> Following the legacy ring submission example, updat
just a warn/heads-up: I had listed this one for -collector but got a
conflict because skl latency retrieval didn't get merged yet.
On Fri, Sep 5, 2014 at 5:53 AM, Damien Lespiau wrote:
> Ville had 2 comments on the SKL memory latency patch that are better addressed
> as separate patches on top.
>
On Tue, Nov 04, 2014 at 03:14:04PM +, Tvrtko Ursulin wrote:
>
> On 11/04/2014 02:31 PM, Chris Wilson wrote:
> >Running __mmu_notifier_register() is surprisingly expensive, so let's
> >not do that unless we have to.
>
> Affects some program startup or what? What is the cost? I would add
> some
On Fri, Oct 31, 2014 at 5:27 AM, Rodrigo Vivi
wrote:
>
> Global GTT doesn't have pat_sel[2:0] so it always point to pat_sel = 000;
> So the only way to avoid screen corruptions is setting PAT 0 to Uncached.
>
> MOCS can still be used though. But if userspace is trusting PTE for
> cache selection t
From: Armin Reese
The new 'i915_context_dump' file generates a hex dump of the
entire logical context DRM object. It is useful for
validating the contents of the default context set up by
the golden state batch buffer.
v1 - Reuse function i915_dump_lrc() instead of i915_context_status().
Separa
v2: minor conflict in i915_debugfs.c
v3: Rebase on top of the for_each_pipe() change adding dev_priv as first
argument.
v4: minor conflict in the i915_debugfs_files array
v5: minor conflict in the i915_debugfs_files array
Reviewed-by: Ville Syrjälä
Signed-off-by: Damien Lespiau
---
drivers/
From: Vandana Kannan
According to the updated Bspec, The mailbox response data is not currently
accounting for memory read latency. Add 2 microseconds to the result for
each level.
This patch adds 2us to latency of level 0 for all cases and
for all other levels (1-7) only if latency[level] > 0.
From: Zhe Wang
Implement common forcewake functions shared by Gen9 features.
v2: Make the focewake_{get,put} functions static (Mika)
Small coding style fix in the function definition (Damien)
Reviewed-by: Mika Kuoppala
Signed-off-by: Zhe Wang (v1)
Signed-off-by: Damien Lespiau (v2)
Signe
From: Pradeep Bhat
This patch provides the implementation for reading the pipe wm HW
state.
v2: Incorporated Damien's review comments and also made modifications
to incorporate the plane/cursor split.
v3: No need to ident a line that was fitting 80 chars
Return early instead of indentin
When we write new values for the DDB allocation and WM parameters, we now
need to trigger the double buffer update for the pipe to take the new
configuration into account.
As the DDB is a global resource shared between planes, enabling or
disabling one plane will result in changes for all planes t
To align with the ilk WM code and because it makes sense to test against
the upper bounds as soon as possible on variables that are bigger than
the number of bits in the register, let's move the maximum checks from
skl_compute_wm_results() to skl_compute_plane_wm().
v2: Leave the result values to
Reviewed-by: Ville Syrjälä
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_pm.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 41cfb26..176e9ef 100644
--- a/drivers/gpu/drm/i915/i
To correctly flush the new DDB allocation we need to know about the pipe
allocation layout inside the DDB in order to sequence the re-allocation
to not cause a newly allocated pipe to fetch from a space that was
previously allocated to another pipe.
This patch preserves the per-pipe (start,end) al
Ville suggested that we should use the same semantics as C arrays to
reduce the number of those pesky +1/-1 in the allocation code.
This patch leaves the debugfs file as is, showing the internal DDB
allocation structure, not the values written in the registers.
v2: Remove the test on ->end in skl
This logically belongs to the WM state, so do it there.
Reviewed-by: Ville Syrjälä
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_pm.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm
v2: Don't check DDB on pre-SKL platforms
Don't check DDB state on disabled pipes
v3: Squash "Expose skl_ddb_get_hw_state()"
Reviewed-by: Ville Syrjälä
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/i915_drv.h | 9 +++
drivers/gpu/drm/i915/intel_display.c | 51
From: Pradeep Bhat
This patch defines SKL specific PLANE_WM Watermark registers. It also
defines macros to get the addresses of different LP levels within a pipe.
v2: Reworked the register definitions and associated macros to make it more
generic and be able to use for_each_pipe in values co
Reviewed-by: Ville Syrjälä
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_pm.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ec7b86b..d0dbd65 100644
--- a/drivers/gpu/drm/i915/
v2: Fix the 3rd plane/cursor logic (Pradeep Bhat)
v3: Fix one-by-one error in the DDB allocation code
v4: Rebase on top of the skl_pipe_pixel_rate() argument change
v5: Replace the available/start/end output parameters of
skl_ddb_get_pipe_allocation_limits() by a single ddb entry constify
a
v2: Adapt to the planes/cursor split
Reviewed-by: Ville Syrjälä
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/i915_reg.h | 16
drivers/gpu/drm/i915/intel_pm.c | 9 +
2 files changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/
The DDB allocation code managed to split in two the compute functions.
Bring back skl_compute_transition_wm() and skl_compute_linetime_wm()
with their little friends.
Reviewed-by: Ville Syrjälä
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_pm.c | 44 -
From: Zhe Wang
Configure and enable RC6 for Gen9.
v2: Rebase on top of BDW rc6 support (Damien)
Reviewed-by: Mika Kuoppala
Signed-off-by: Zhe Wang
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_pm.c | 52 -
1 file changed, 51 insertions(
From: Pradeep Bhat
This patch reads the memory latency values for all the 8 levels for
SKL. These values are needed for the Watermark computation.
v2: Incorporated the review comments from Damien on register
indentation.
v3: Updated the code to use the sandybridge_pcode_read for reading
From: Pradeep Bhat
This patch implements the watermark algorithm and its necessary
functions. Two function pointers skl_update_wm and
skl_update_sprite_wm are provided. The skl_update_wm will update
the watermarks for the crtc provided as an argument and then
checks for change in DDB allocation f
We now need to allocate space in the DDB for planes being scanned out
ourselves. The data structure to represent an allocation mirrors what
we'll need to write in the registers later on: (start, end).
We add that allocation datat to the skl_wm_values structure as part of
the values to program the
What we're talking about here is the DDB allocation (in blocks). That's
more descriptive than 'max_page_buff_alloc'.
Reviewed-by: Ville Syrjälä
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_pm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/d
We can reduce the indentation level by continuing early.
Reviewed-by: Ville Syrjälä
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_pm.c | 42 -
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b
Reviewed-by: Ville Syrjälä
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 84e8cdb..cf84b6d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+
We're going to add a new step, let's not hide the copy of the new WM
state inside one inner function, but as a 1st level operation in the WM
update.
v2: Split the staging results structure to not exceed the 1Kb stack
allocation in skl_update_wm()
Reviewed-by: Ville Syrjälä
Signed-off-by: Dam
v2: Use the gen >= 9 in the debugfs file condition (Ville)
Reviewed-by: Ville Syrjälä
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/i915_debugfs.c | 76 ++---
1 file changed, 62 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debug
From: Vandana Kannan
According to updated BSpec, If level 1 or any higher level has a value of 0x00,
that level and any higher levels are unused and the associated watermark
registers must not be enabled.
This patch checks for latency 0 for level >=1 and does not enable WM
corresponding to level
The transition WMs code was doing a shortcut and the values were copied
from the WM0 ones at compute_wm_results() time. Going forward, we want
to compute them like the other WMs and resolve their final register
values in the same way as well.
This patch does just that and isolate the transtion WM
We might as well try to push a few more patches while waiting for the next
batch of reviews. Here's the WM code and 2 bonus patches around forcewake and
rc6.
The attentive reader will notice the lack of r-b tag for:
"drm/i915/skl: Make res_blocks/lines intermediate values 32 bits"
This patch do
From: Pradeep Bhat
This patch defines the structures needed for computation of
watermarks of pipes and planes for SKL.
v2: Incorporated Damien's review comments and removed unused fields
in structs for future features like rotation, drrs and scaling.
The skl_wm_values struct is now made
On Tue, Nov 04, 2014 at 02:30:14AM -0800, Daniel Vetter wrote:
> On Mon, Nov 03, 2014 at 11:19:42AM -0800, bradley.d.vol...@intel.com wrote:
> > + flags |= I915_DISPATCH_SECURE;
>
> I've forgotten one: You must have a full ppgtt check here since the
> binding for aliasing ppgtt i
On Tue, Nov 04, 2014 at 01:40:05PM +0100, Daniel Vetter wrote:
> On Tue, Nov 4, 2014 at 1:21 PM, Ville Syrjälä
> wrote:
> >> > drm/i915: Refactor vlv_display_irq_uninstall()
> >>
> >> Except this, I think consens is that we don't need it?
> >
> > No, it's needed by the later patches. Trying to r
On Tue, Nov 04, 2014 at 02:17:59AM -0800, Daniel Vetter wrote:
> On Mon, Nov 03, 2014 at 11:19:42AM -0800, bradley.d.vol...@intel.com wrote:
> > From: Brad Volkin
> >
> > This patch sets up all of the tracking and copying necessary to
> > use batch pools with the command parser and dispatches the
On 11/4/2014 12:54 PM, Daniel Vetter wrote:
On Tue, Oct 07, 2014 at 06:10:56PM +0100, Michel Thierry wrote:
This is based on the first 55 patches of Ben's 48b addressing work, taking
into consideration the latest changes in (mainly aliasing) ppgtt rules.
Because of these changes in the tree, th
From: Satheeshakrishna M
This patch implements SKL DPLL programming that includes:
- DPLL allocation
- wide range PLL calculation and programming
- DP link rate programming
- DDI to DPLL mapping
v2: Incorporated following changes
- Added vfunc for function
It's not implemented yet, so no point in running the test really.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=68638
Signed-off-by: Daniel Vetter
---
tests/prime_nv_test.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tests/prime_nv_test.c b/tests/prime_nv_test.c
index 8211cd6f
From: Satheeshakrishna M
v2: Fixup compilation due to the removal of the intel_ddi_dpll_id enum.
And add a fixme about the abuse of pipe_config here.
v3: Rebase on top of the hsw_ddi_clock_get() rename (Damien)
v4: Modified as per review comments from Paulo
Signed-off-by: Satheeshakrishna M (
From: Satheeshakrishna M
Modify the implementation to query DPLL attached to a SKL port.
v2: Rebase on top of the run-time PM on DPMS series (Damien)
v3: Modified as per review comments from Paulo
Signed-off-by: Satheeshakrishna M
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel
From: Satheeshakrishna M
This patch defines the necessary SKL registers for implementing the
new clocking mechanism.
v2: Addressed review comments by Damien
- Added code comment
- Introduced enum for WRPLL values
v3: Rebase on top of nightly (minor conflict in i915_reg.h)
v4: U
From: Satheeshakrishna M
Determine programmed cd clock for SKL.
v2: Fix the LCPLL1 enable warning logic
v3: Rebase over the hsw pll rework.
v4: Rebase on top of the per-platform split (Damien)
v5: Modified as per review comments from Paulo
Signed-off-by: Satheeshakrishna M
Signed-off-by: Da
On Mon, Sep 22, 2014 at 03:25:30PM -0300, Paulo Zanoni wrote:
> 2014-09-04 8:27 GMT-03:00 Damien Lespiau :
> > From: Satheeshakrishna M
> >
> > Adding structure/enum for SKL clocking implementation.
> >
> > v2: Addressed Damien's comment
> > - Removed internal structure from this header fi
Signed-off-by: Thomas Wood
---
lib/igt_kms.c | 39 +--
tests/gem_flink_race.c | 9 ++---
tests/kms_flip.c | 11 +--
tests/kms_sink_crc_basic.c | 4 +++-
tests/pm_rpm.c | 3 +--
tests/prime_self_import.c |
On 11/04/2014 02:31 PM, Chris Wilson wrote:
Running __mmu_notifier_register() is surprisingly expensive, so let's
not do that unless we have to.
Affects some program startup or what? What is the cost? I would add some
notes in the commit for future reference.
Signed-off-by: Chris Wilson
-
On Tue, 04 Nov 2014, Daniel Vetter wrote:
> There's quite a few bug reports with error states where the error
> reasons makes just about no sense at all. Like dying on tlbs for a
> display plane that's not even there. Also users don't really report a
> lot of bad side effects generally, just the e
There's quite a few bug reports with error states where the error
reasons makes just about no sense at all. Like dying on tlbs for a
display plane that's not even there. Also users don't really report a
lot of bad side effects generally, just the error states.
Furthermore we don't even enable thes
On Tue, Nov 04, 2014 at 02:31:29PM +, Chris Wilson wrote:
> +static drm_intel_bo *
> +check_bo_alloc_userptr(drm_intel_bufmgr *bufmgr,
> +const char *name,
> +void *addr,
> +uint32_t tiling_mode,
> +uint32_t stride,
Running __mmu_notifier_register() is surprisingly expensive, so let's
not do that unless we have to.
Signed-off-by: Chris Wilson
---
intel/intel_bufmgr_gem.c | 114 +++
1 file changed, 65 insertions(+), 49 deletions(-)
diff --git a/intel/intel_bufmgr_
Fastboot in its current incarnation assumes that the pfit isn't
relevatn for the state and that it can be disabled without restarting
the crtc. Unfortunately that's not the case on gen2/3 - it upsets the
hw and results in a black screen.
Worse, the way the current fastboot hack is structure we can
On 03/11/14 20:59, Chris Wilson wrote:
> On Mon, Nov 03, 2014 at 01:29:04PM +, Dave Gordon wrote:
>> Fixes to both the LRC and the legacy ringbuffer code to correctly
>> calculate and update the available space in a ring.
>>
>> The logical ring code was updating the software ring 'head' value
>
On Tue, Nov 04, 2014 at 01:44:47PM +0100, Daniel Vetter wrote:
> On Wed, Oct 08, 2014 at 08:13:33AM +0100, Chris Wilson wrote:
> > On Tue, Oct 07, 2014 at 06:10:56PM +0100, Michel Thierry wrote:
> > > This is based on the first 55 patches of Ben's 48b addressing work, taking
> > > into consideratio
On Tue, Oct 07, 2014 at 06:10:56PM +0100, Michel Thierry wrote:
> This is based on the first 55 patches of Ben's 48b addressing work, taking
> into consideration the latest changes in (mainly aliasing) ppgtt rules.
>
> Because of these changes in the tree, the first 17 patches of the original
> se
2014-11-03 8:29 GMT-02:00 Daniel Vetter :
> On Tue, Oct 28, 2014 at 11:20:37AM -0200, Paulo Zanoni wrote:
>> 2014-05-19 11:19 GMT-03:00 :
>> > From: Ville Syrjälä
>> >
>> > On pre-HSW we have two encoders per digital port: one HDMI, one DP.
>> > However they are the same physical port in hardware
On Wed, Oct 08, 2014 at 08:13:33AM +0100, Chris Wilson wrote:
> On Tue, Oct 07, 2014 at 06:10:56PM +0100, Michel Thierry wrote:
> > This is based on the first 55 patches of Ben's 48b addressing work, taking
> > into consideration the latest changes in (mainly aliasing) ppgtt rules.
> >
> > Because
When constructing a batchbuffer, it is sometimes crucial to know the
largest hole into which we can fit a fenceable buffer (for example when
handling very large objects on gen2 and gen3). This depends on the
fragmentation of pinned buffers inside the aperture, a question only the
kernel can easily
On Tue, Nov 4, 2014 at 1:21 PM, Ville Syrjälä
wrote:
>> > drm/i915: Refactor vlv_display_irq_uninstall()
>>
>> Except this, I think consens is that we don't need it?
>
> No, it's needed by the later patches. Trying to replace the vlv/chv
> uninstall() hooks with reset() is best left for another
On Mon, Nov 03, 2014 at 05:38:59PM +0100, Daniel Vetter wrote:
> On Thu, Oct 30, 2014 at 07:42:49PM +0200, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > After enabling the pipe-a power well on CHV I noticed that hpd and
> > interrupts
> > didn't work too well anymore. The
On Mon, 2014-11-03 at 20:30 +, Chris Wilson wrote:
> On Mon, Nov 03, 2014 at 05:05:55PM +0100, Daniel Vetter wrote:
> > On Thu, Oct 30, 2014 at 04:39:37PM +, Tvrtko Ursulin wrote:
> > > From: Tvrtko Ursulin
> > >
> > > It will be used by other call sites shortly.
> > >
> > > Signed-off-b
On Tue, Nov 04, 2014 at 11:15:16AM +, Tvrtko Ursulin wrote:
>
> On 11/03/2014 05:29 PM, Daniel Vetter wrote:
> >On Mon, Nov 3, 2014 at 6:20 PM, Tvrtko Ursulin
> > wrote:
> >>I did not like your idea, well I did not think it is feasible - as in easily
> >>doable, of stealing the DMA addresses s
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