use_mmio_flip() makes sure we only enable MMIO flips on gen5+. So we
don't need to take into account older devices.
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_display.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_di
OCD kicks in again...
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_display.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 07440ad..dd071c6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+
SKL will specialize it.
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 17 +
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
in
Nothing special to note. We mirror what is done for other platforms, but
using the SKL plane registers.
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_display.c | 26 +-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate
BYT: pass/total=270/271->270/271
PNV: pass/total=271/271->271
In XenGT, GPU power management is controlled by host i915
driver, so there is no need to provide virtualized GPU PM
support. In the future it might be useful to gather VM
input for freq boost, but now let's disable it simply.
Signed-off-by: Yu Zhang
Signed-off-by: Jike Song
---
drivers/gpu/drm/
2014-10-14 16:32 GMT-03:00 Ville Syrjälä :
> On Tue, Oct 14, 2014 at 02:05:42PM -0300, Paulo Zanoni wrote:
>> From: Paulo Zanoni
>>
>> When I look at BSpec, and at cursor_size_ok() (from the Kernel's
>> intel_display.c), I see that only 845g and i865g support non-square
>> displays, so SKIP the te
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate
BYT: pass/total=271/271->270/271
PNV: pass/total=269/271->271
This allows us to calculate the full pipe config before we do any mode
setting work.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c | 40 ++--
1 file changed, 29 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.
On Tue, May 27, 2014 at 09:33:09PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> During a GPU reset we need to get pending page flip cleared out
> since the ring contents are gone and flip will never complete
> on its own. This used to work until the mmio vs. CS flip race
From: Daniele Ceraolo Spurio
These tracepoints are useful for observing the creation and
destruction of Full PPGTTs.
v4: add DOC information
v5: pull the DOC in drm.tmpl
Signed-off-by: Daniele Ceraolo Spurio
---
Documentation/DocBook/drm.tmpl | 13 ++
drivers/gpu/drm/i915/i915_ge
So that we gain more fine grained control how we want
to do the recovery. The aim is to grab the gpu state and
skip everything related to recovery.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.h | 9 -
drivers/gpu/drm/i915/i915_irq.c | 28 +++-
On Thu, Oct 23, 2014 at 6:07 PM, Siluvery, Arun
wrote:
> On 23/10/2014 16:51, Daniel Vetter wrote:
>>
>> On Thu, Oct 23, 2014 at 04:29:30PM +0100, Arun Siluvery wrote:
>>>
>>> We would want to apply some of the workarounds based on a condition to a
>>> particular platform or Gen but we may not kno
out from i915_capture_error_state so that it can
be reused when we want to grab only the gpu state without
any errors.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gpu_error.c | 41 +++
1 file changed, 27 insertions(+), 14 deletions(-)
diff --git a/
On Mon, Oct 20, 2014 at 01:29:59PM +, Daniel, Thomas wrote:
> > -Original Message-
> > From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
> > Sent: Monday, October 20, 2014 2:11 PM
> > To: Daniel, Thomas
> > Cc: intel-gfx@lists.freedesktop.org; shuang...@linux.intel.com
> > Subject: R
From: Sonika Jindal
This allows the cursor plane to be updated the same way as primary and sprites,
and same set_property handler is used for all of these planes.
v2 (by Matt Roper): Rework to apply to latest di-nightly codebase. The
switch to split check/commit plane programming change
CC David for notifying the patch update:
Add the missing v2 changelog:
Take David's comment: add mmap support, remove the MMAP_IOCTL and add
MMAP_OFFSET_IOCTL
Take David's comment: remove postclose() and move code to preclose()
Take David's comment: set NULL to set_busid
On Thu, Oct 23, 2014 at 01:01:28PM +0200, Gerd Hoffmann wrote:
> Hi,
>
> > Stuf like driver load/unload, suspend/resume, runtime pm and gpu reset are
> > already supre-fragile as-is. Every time we change something in there, a
> > bunch of related things fall apart. With vgt we'll have even more
On Thu, Oct 23, 2014 at 10:58:59AM -0200, Paulo Zanoni wrote:
> 2014-10-23 10:50 GMT-02:00 Daniel Vetter :
> > Hi Tood,
> >
> > Paulo already mentioned it, so I'll just rehash quickly: I think the
> > points from the internal pre-review first need to be address before we can
> > dig into details. I
From: Armin Reese
This patch includes the Gen9 batch buffer to generate
a 'golden context' for that product family.
Signed-off-by: Armin Reese
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_gem_render_state.c | 2 +
drivers/gpu/drm/i915/intel_rendersta
On Thu, Oct 23, 2014 at 03:28:24PM +0800, Yu Zhang wrote:
Empty commit messages aren't good. Even for really simple refactoring
please explain in 1-2 sentences the motivation for the patch, since the
change itself doesn't really say that. For this one I've added something
while merging.
> Signed-
Signed-off-by: Chris Wilson
---
lib/igt_aux.c| 69
lib/igt_aux.h| 4 +++
tests/gem_evict_alignment.c | 15 ++
tests/gem_evict_everything.c | 15 ++
4 files changed, 103 insertions(+)
diff --git a/lib/i
On Wed, Sep 10, 2014 at 06:17:04PM +0300, Imre Deak wrote:
> We already disable everything during S4 freeze, except the PCI device
> itself. There is no reason why we couldn't disable that too and doing
> so allows us to unify these handlers in the next patch with the
> corresponding S3 suspend/res
On Tue, 21 Oct 2014, Daniel Vetter wrote:
> On Tue, Oct 21, 2014 at 12:00:30PM +0530, Singh, Gaurav K wrote:
>>
>> On 9/24/2014 2:57 PM, Jani Nikula wrote:
>> >On Wed, 24 Sep 2014, Gaurav K Singh wrote:
>> >>Signed-off-by: Gaurav K Singh
>> >>Signed-off-by: Shobhit Kumar
>> >>---
>> >> driver
On Wed, 22 Oct 2014, Eric Paris wrote:
> That's really serious. Looking now.
Indeed its serious. And it's even more serious as this masterpiece of
assembly wreckage was pulled in via your tree w/o having an acked-by
one of the x86 maintainers.
> On Wed, 2014-10-22 at 16:08 -0200, Paulo Zanoni w
Regression from:
commit be4710a541b517b5f8663448bffed5656d59b47b
Author: Thomas Wood
Date: Fri Oct 10 11:20:35 2014 +0100
lib: add common min and max macros
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85218
Tested-by: Guo Jinxian
Signed-off-by: Mika Kuoppala
---
lib/igt_aux.
2014-10-09 12:38 GMT-03:00 Todd Previte :
> These counters are used for Displayort complinace testing to detect error
> conditions
> when executing certain compliance tests. Currently these are used in the EDID
> tests
> to determine if the video mode needs to be set to the preferred mode or the
On Wed, Oct 22, 2014 at 08:27:50PM +0800, Yu, Zhang wrote:
>
>
> On 10/22/2014 12:40 AM, Daniel Vetter wrote:
> >On Thu, Oct 16, 2014 at 02:24:27PM +0800, Yu Zhang wrote:
> >>In the virtualized environment, forcewake operations are not
> >>necessory for the driver, because mmio accesses will be t
On Tue, 21 Oct 2014 16:49:37 +0200
Daniel Vetter wrote:
> On Thu, Oct 09, 2014 at 12:57:44PM -0700, Jesse Barnes wrote:
> > From: Kristian Høgsberg
> >
> > Like mode_equal but w/o the clock checks. Useful for checking if modes
> > are close enough to re-use to avoid a boot time mode set for ex
> -Original Message-
> From: He, Shuang
> Sent: Monday, October 20, 2014 9:47 PM
> To: He, Shuang; intel-gfx@lists.freedesktop.org; Daniel, Thomas
> Subject: RE: [Intel-gfx] [PATCH] drm/i915/bdw: Clean up execlist queue items
> in
>
> Tested-By: PRC QA PRTS (Patch Regression Test System C
Write HWS_PGA address even in execlists mode as the global hardware status
page is still required. This address was previously uninitialized and
HWSP writes would clobber whatever buffer happened to reside at GGTT
address 0.
Issue: VIZ-2020
Signed-off-by: Thomas Daniel
---
drivers/gpu/drm/i915/
On Mon, Oct 20, 2014 at 06:20:09PM +0530, Vandana Kannan wrote:
> Moving timestamp values to intel_panel as part of moving all refs of PPS to
> intel_panel.
>
> Signed-off-by: Vandana Kannan
On second though, how does the code still work before applying patch 6&7?
Presuming I've not read this th
On Thu, Oct 09, 2014 at 08:38:01AM -0700, Todd Previte wrote:
> Add the skeleton framework for supporting automation for Displayport
> compliance
> testing. This patch adds the necessary framework for the source device to
> appropriately
> respond to test automation requests from a sink device.
>
From: Ander Conselvan de Oliveira
Currently we program just DPSCNTR and DSPSTRIDE directly from the ring
interrupt handler, which is fine since the hardware guarantees that
those are update atomically. When we have atomic page flips we'll want
to be able to update also the offset registers, and t
On Thu, Oct 16, 2014 at 12:39:29PM -0700, Todd Previte wrote:
>
> On 10/16/2014 10:46 AM, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Sometimes we seem to get utter garbage from DPCD reads. The resulting
> > buffer is filled with the same byte, and the operation completed
Signed-off-by: Thomas Wood
---
configure.ac | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure.ac b/configure.ac
index 9cdd202..03e856d 100644
--- a/configure.ac
+++ b/configure.ac
@@ -201,7 +201,7 @@ fi
AM_CONDITIONAL(BUILD_TESTS, [test "x$BUILD_TESTS" = xyes])
AC_DE
On 10/16/2014 10:46 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Turning vdd on/off can generate a long hpd pulse on eDP ports. In order
to handle hpd we would need to turn on vdd to perform aux transfers.
This would lead to an endless cycle of
"vdd off -> long hpd -> vdd on ->
On Mon, Oct 06, 2014 at 03:15:10PM +0100, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> For: VIZ-4377
> Signed-off-by: john.c.harri...@intel.com
> ---
> drivers/gpu/drm/i915/i915_debugfs.c|6 +--
> drivers/gpu/drm/i915/i915_drv.h|6 +--
> drivers/gpu/drm/
On Mon, Oct 06, 2014 at 03:15:13PM +0100, john.c.harri...@intel.com wrote:
> From: John Harrison
To thin commit message.
Also I wonder whethere we should track the olr state more explicitly in
the request structure instead of jumping through all these hoops. And
explicit olr state for a request
Hi
On Thu, Oct 16, 2014 at 3:39 PM, Cheng, Yao wrote:
> Accepted :) I will update the patch to implement the mmap interface and
> remove the legacy MMAP_IOCTL.
> BTW I didn't see a field to get mmap_offset in struct drm_gem_open, I guess
> something like a new "GET_MMAP_OFFSET_IOCTL" need be a
Ville found that the sequencing I had to re-program the DDB wasn't quite
correct and so this is an attempt to do better.
This series reworks patch:
[PATCH 78/89] drm/i915/skl: Flush the WM configuration
of the initial SKL Stage 1 series. The core of the issue is now documented in a
comment, so
The DDB allocation code managed to split in two the compute functions.
Bring back skl_compute_transition_wm() and skl_compute_linetime_wm()
with their little friends.
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_pm.c | 44 -
1 file changed
On Wed, Oct 15, 2014 at 10:48:34AM +0100, Nick Hoath wrote:
> The first pass implementation of execlists required a backpointer to the
> context to be held
> in the intel_ringbuffer. However the context pointer is available higher in
> the call stack.
> Remove the backpointer from the ring buffer
On Tue, Oct 14, 2014 at 08:50:35AM -0700, Sean V Kelley wrote:
> On Tue, Oct 14, 2014 at 4:53 AM, Thierry Reding
> wrote:
> > On Mon, Oct 13, 2014 at 08:15:00PM +0800, Yao Cheng wrote:
> >> drm/ipvr is a new GEM driver for baytrail's vxd392, which accelerates VP8
> >> video decoding.
> >> The dri
The first pass implementation of execlists required a backpointer to the
context to be held
in the intel_ringbuffer. However the context pointer is available higher in the
call stack.
Remove the backpointer from the ring buffer structure and instead pass it down
through the
call stack.
Signed-of
On 13/10/14 02:09, Dave Airlie wrote:
So in this example 268 megabytes have been lost.
This isn't RAM, its address space mapping, its not really a leak at all.
It really doesn't matter whether it is ram or mapping; its a resource leak
that causes the system to OOM and panic.
hey I was try
The Displayport Link Layer Compliance Testing Specification 1.2 rev 1.1
specifies that
repeated AUX transactions after a failure (no response / invalid response) must
have
a minimum delay of 400us before the resend can occur. Tests 4.2.1.1 and 4.2.1.2
are two
tests that require this specifically
On 10/09/2014 12:11 PM, Daniel Vetter wrote:
On Wed, Oct 08, 2014 at 06:32:21PM +0300, Ander Conselvan de Oliveira wrote:
From: Ander Conselvan de Oliveira
This shouldn't change the behavior of those functions, since they are
called after the new_config is made effective and that points to the
On Thu, Oct 09, 2014 at 08:13:18AM -0700, Jesse Barnes wrote:
> Gets the detect code (which may take awhile) out of the resume path,
> speeding things up a bit.
>
> v2: use a delayed work queue instead (Daniel)
> v3: cancel delayed work at unload and suspend time (Jesse)
> v4: make delayed work co
From: John Harrison
For: VIZ-4377
Signed-off-by: john.c.harri...@intel.com
---
drivers/gpu/drm/i915/i915_gem.c |1 -
drivers/gpu/drm/i915/intel_lrc.c|1 +
drivers/gpu/drm/i915/intel_ringbuffer.c |1 +
3 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drive
Reading timestamp register using I915_READ64 returns incorrect value
containing only 32-bits of usable timestamp on x86_64.
Let's use I915_READ64_2x32 to expose missing bits and swap dwords to
stay compatible with old userspace.
v2: Renamed macro used for swapping dwords to be more like swab.h
mac
On Tue, Oct 07, 2014 at 06:01:10PM +0300, Ville Syrjälä wrote:
> On Tue, Oct 07, 2014 at 05:47:52PM +0300, Ville Syrjälä wrote:
> > On Wed, Sep 24, 2014 at 02:20:25PM -0300, Gustavo Padovan wrote:
> > > From: Gustavo Padovan
> > >
> > > Move check inside intel_crtc_cursor_set_obj() to
> > > intel_
On Tue, Oct 07, 2014 at 01:06:32PM +0300, Ville Syrjälä wrote:
> > + $(top_srcdir)/lib/libintel_tools.la \
>
> top_builddir
Yes, caught it just before merging :) good eye though!
--
Damien
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.o
On 09/26/2014 09:28 AM, Ville Syrjälä wrote:
On Thu, Sep 25, 2014 at 09:26:36AM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
HDMI audio clock config was incorrectly choosing the default for
pixel doubled interlaced modes. The table was missing pixel clock
values 13.500 (27.000)
2014-10-01 11:47 GMT-03:00 Rodrigo Vivi :
> Avoid to expose RC6 and RC6pp to the platforms that doesn't support it.
> So powertop can be changed to show RC6p and RC6pp only on the platforms
> they are available.
>
> v2: Simplify by merging RC6p and RC6pp groups and respect the spec that
> mentions
From: Ben Widawsky
In gen8, 32b PPGTT has always had one "pdp" (it doesn't actually have
one, but it resembles having one). The #define was confusing as is, and
using "PDPE" is a much better description.
sed -i 's/GEN8_LEGACY_PDPS/GEN8_LEGACY_PDPES/' drivers/gpu/drm/i915/*.[ch]
Signed-off-by: B
On Wed, Sep 24, 2014 at 02:20:28PM -0300, Gustavo Padovan wrote:
> From: Gustavo Padovan
>
> We need to get hdisplay and vdisplay in a few places so create a
> helper to make our job easier.
>
> Suggested-by: Ville Syrjälä
> Signed-off-by: Gustavo Padovan
> ---
> drivers/gpu/drm/drm_crtc.c
2014-10-07 16:58 GMT-03:00 Ville Syrjälä :
> On Tue, Oct 07, 2014 at 04:11:10PM -0300, Paulo Zanoni wrote:
>> From: Paulo Zanoni
>>
>> We were missing the pipe B/C vblank bits! Take a look at
>> gen8_de_irq_postinstall for a comparison.
>>
>> This should fix a bunch of IGT tests.
>>
>> There are a
On Wed, 08 Oct 2014, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> We were missing the pipe B/C vblank bits! Take a look at
> gen8_de_irq_postinstall for a comparison.
>
> This should fix a bunch of IGT tests.
>
> There are a few more things we could improve on this code, but this
> should be the
2014-10-07 11:06 GMT-03:00 Rodrigo Vivi :
> Avoid to expose RC6 and RC6pp to the platforms that doesn't support it.
> So powertop can be changed to show RC6p and RC6pp only on the platforms
> they are available.
>
> v2: Simplify by merging RC6p and RC6pp groups and respect the spec that
> mentions
On Mon, Oct 06, 2014 at 05:11:57PM +0100, Tvrtko Ursulin wrote:
>
> Hi all,
>
> We need to refactor the current code a bit to allow parameters like
> plane rotation and framebuffer tiling mode be taken into account when
> calculating display watermarks.
>
> I looked into this code a bit and am
From: Ville Syrjälä
We need to access the gunit mailbox when changing the cdclk frequency.
Currently we update the power wells only after chancing cdclk, so the
device might be suspended when we have to frob it. Grab a runtime PM
reference to make sure it's awake.
Signed-off-by: Ville Syrjälä
-
From: Gustavo Padovan
We can't let visible set true while the fb is null, some places of
the code only check for visible to base its decisions.
Signed-off-by: Gustavo Padovan
---
drivers/gpu/drm/drm_plane_helper.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/drm_pla
From: Gustavo Padovan
The fb check introduced to drm_plane_helper_check_update() just make this
check impossible to branch in.
Signed-off-by: Gustavo Padovan
---
drivers/gpu/drm/i915/intel_display.c | 21 +
1 file changed, 5 insertions(+), 16 deletions(-)
diff --git a/driv
On Thu, Oct 23, 2014 at 08:52:59AM -0700, Volkin, Bradley D wrote:
> On Thu, Oct 23, 2014 at 05:31:12AM -0700, Daniel Vetter wrote:
> > On Wed, Oct 22, 2014 at 09:04:32AM -0700, Volkin, Bradley D wrote:
> > > [snip]
> > >
> > > On Tue, Oct 21, 2014 at 08:50:33AM -0700, Daniel Vetter wrote:
> > > >
On Fri, Oct 24, 2014 at 02:51:35PM +0100, Gustavo Padovan wrote:
> From: Gustavo Padovan
>
> Merge it into the plane update_plane() callback and make other
> users use the update_plane() functions instead.
>
> The fb != crtc->cursor->fb was already inside intel_crtc_cursor_set_obj()
> so we fold
On Fri, Oct 24, 2014 at 04:39:29PM +0200, Daniel Vetter wrote:
> On Fri, Oct 24, 2014 at 12:11:11PM +0100, Chris Wilson wrote:
> > Userspace cares about whether or not swizzling depends on the page
> > address for its direct access into bound objects. Extend the get_tiling
> > ioctl to report the p
On Fri, Oct 24, 2014 at 02:51:34PM +0100, Gustavo Padovan wrote:
> From: Gustavo Padovan
>
> There is no point in flipping a buffer for a disabled crtc.
That thing doesn't actually flip but just signal the frontbuffer
tracking code that either has just flipped or is going to real soon now
(tm).
Hi all,
New -testing cycle with cool stuff:
- suspend/resume/freeze/thaw unification from Imre
- wa list improvements from Mika&Arun
- display pll precomputation from Ander Conselvan, this removed the last
->mode_set callbacks, a big step towards implementing atomic modesets
- more kerneldoc for
On Fri, Oct 24, 2014 at 04:43:08PM +0200, Daniel Vetter wrote:
> On Fri, Oct 24, 2014 at 01:09:08PM +0100, Chris Wilson wrote:
> > On Fri, Oct 24, 2014 at 12:42:33PM +0100, Tvrtko Ursulin wrote:
> > > From: Tvrtko Ursulin
> > >
> > > If these flags are on the object level it will be more difficul
On Fri, Oct 24, 2014 at 01:09:08PM +0100, Chris Wilson wrote:
> On Fri, Oct 24, 2014 at 12:42:33PM +0100, Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin
> >
> > If these flags are on the object level it will be more difficult to allow
> > for multiple VMAs per object.
> >
> > v2: Simplification
On Fri, Oct 24, 2014 at 04:28:50PM +0200, Daniel Vetter wrote:
> On Tue, May 27, 2014 at 09:33:09PM +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > During a GPU reset we need to get pending page flip cleared out
> > since the ring contents are gone and flip will never
On Fri, Oct 24, 2014 at 12:11:11PM +0100, Chris Wilson wrote:
> Userspace cares about whether or not swizzling depends on the page
> address for its direct access into bound objects. Extend the get_tiling
> ioctl to report the physical swizzling value in addition to the logical
> swizzling value so
On Fri, Oct 24, 2014 at 02:23:35PM +0100, Gustavo Padovan wrote:
> 2014-10-07 Ville Syrjälä :
>
> > On Wed, Sep 24, 2014 at 02:20:26PM -0300, Gustavo Padovan wrote:
> > > From: Gustavo Padovan
> > >
> > > Merge it into the plane update_plane() callback and make other
> > > users use the update_p
Hi Dave,
Ok, new attempt, this time around with full ppgtt disabled again.
drm-intel-next-2014-10-03:
- first batch of skl stage 1 enabling
- fixes from Rodrigo to the PSR, fbc and sink crc code
- kerneldoc for the frontbuffer tracking code, runtime pm code and the basic
interrupt enable/disabl
On Fri, Oct 24, 2014 at 02:59:44PM +0100, Gustavo Padovan wrote:
> 2014-10-07 Ville Syrjälä :
>
> > On Wed, Sep 24, 2014 at 02:20:32PM -0300, Gustavo Padovan wrote:
> > > From: Gustavo Padovan
> > >
> > > After some refactor intel_primary_plane_setplane() does the same
> > > as intel_pipe_set_ba
On Fri, Oct 24, 2014 at 04:23:22PM +0300, Jani Nikula wrote:
> On Fri, 06 Jun 2014, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > My Fujitsu-Siemens Lifebook S6010 definitely has a VGA connector, but
> > the VBT says different. Ignore the VBT for 830M since it seems such
> >
2014-10-07 Ville Syrjälä :
> On Wed, Sep 24, 2014 at 02:20:32PM -0300, Gustavo Padovan wrote:
> > From: Gustavo Padovan
> >
> > After some refactor intel_primary_plane_setplane() does the same
> > as intel_pipe_set_base() so we can get rid of it and replace the calls
> > with intel_primary_plane
From: Gustavo Padovan
Take out the pin_fb code so commit phase can't fail anymore.
Signed-off-by: Gustavo Padovan
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 35 ++-
1 file changed, 26 insertions(+), 9 deletions(-)
diff --git a/driver
From: Gustavo Padovan
Use the macros makes the code cleaner and it also checks for a NULL fb.
Signed-off-by: Gustavo Padovan
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_sprite.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/inte
From: Gustavo Padovan
take out pin_fb code so the commit phase can't fail anymore.
Signed-off-by: Gustavo Padovan
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_sprite.c | 63 +++--
1 file changed, 40 insertions(+), 23 deletions(-)
diff --git a/driv
From: Gustavo Padovan
There is no point in flipping a buffer for a disabled crtc.
Signed-off-by: Gustavo Padovan
---
drivers/gpu/drm/i915/intel_display.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_d
From: Gustavo Padovan
Merge it into the plane update_plane() callback and make other
users use the update_plane() functions instead.
The fb != crtc->cursor->fb was already inside intel_crtc_cursor_set_obj()
so we fold intel_crtc_cursor_set_obj() inside intel_commit_cursor_plane()
and merge both
2014-10-07 Ville Syrjälä :
> On Wed, Sep 24, 2014 at 02:20:26PM -0300, Gustavo Padovan wrote:
> > From: Gustavo Padovan
> >
> > Merge it into the plane update_plane() callback and make other
> > users use the update_plane() functions instead.
> >
> > The fb != crtc->cursor->fb was already insid
On Fri, 06 Jun 2014, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> My Fujitsu-Siemens Lifebook S6010 definitely has a VGA connector, but
> the VBT says different. Ignore the VBT for 830M since it seems such
> old machines would generally have a VGA connector.
>
> This is a regress
On Fri, Oct 24, 2014 at 01:40:35PM +0100, Chris Wilson wrote:
> On Wed, May 28, 2014 at 01:10:55PM +0100, Chris Wilson wrote:
> > On Tue, May 27, 2014 at 09:33:09PM +0300, ville.syrj...@linux.intel.com
> > wrote:
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > b/drivers/gpu/drm/i915
On Wed, May 28, 2014 at 01:10:55PM +0100, Chris Wilson wrote:
> On Tue, May 27, 2014 at 09:33:09PM +0300, ville.syrj...@linux.intel.com wrote:
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 94ac51f..cb9dd8e 100644
> > --- a/drivers/gpu/dr
On Fri, Oct 24, 2014 at 12:42:33PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> If these flags are on the object level it will be more difficult to allow
> for multiple VMAs per object.
>
> v2: Simplification and cleanup after code review comments (Chris Wilson).
>
> Signed-off-by: T
From: Tvrtko Ursulin
With multiple VMA per object and per address space we need some sort of
key to distinguish between then for which there is a new 'id' field.
Old API which does not know or care about this will use a default id.
I have tried to identify all places which assume there can only
From: Tvrtko Ursulin
If these flags are on the object level it will be more difficult to allow
for multiple VMAs per object.
v2: Simplification and cleanup after code review comments (Chris Wilson).
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c
Userspace cares about whether or not swizzling depends on the page
address for its direct access into bound objects. Extend the get_tiling
ioctl to report the physical swizzling value in addition to the logical
swizzling value so that userspace can accurately determine when it is
possible for manua
Hi,
Luxmark (both 2.0/2.1) works fine on my IVB machine. The back trace
you provided below doesn't indicate it's a beignet related problem.
It hadn't enter beignet domain and just crashed in luxmark internal.
On Fri, Oct 24, 2014 at 12:04:29PM +0300, Vasily Khoruzhick wrote:
> Hi Zhigang,
>
> Lu
On Fri, 2014-10-24 at 10:51 +0200, Daniel Vetter wrote:
> On Thu, Oct 23, 2014 at 07:23:23PM +0300, Imre Deak wrote:
> > We already disable everything during S4 freeze, except the PCI device
> > itself. There is no reason why we couldn't disable that too and doing
> > so allows us to unify these ha
On Fri, Oct 24, 2014 at 10:48:43AM +0200, Daniel Vetter wrote:
> On Fri, Oct 24, 2014 at 08:30:56AM +, Daniel, Thomas wrote:
> >
> >
> > > -Original Message-
> > > From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
> > > Vetter
> > > Sent: Friday, October 24, 2014
On Fri, Oct 24, 2014 at 10:40:10AM +0200, Daniel Vetter wrote:
> - Polish for Akash' patch according to Chris' review. Commit message also
> needs to gain the performance data. And we need to have a "does PAT
> work" test I think like Chris suggested.
Done, see v2 I sent. Commit message contai
On Thu, Oct 23, 2014 at 07:23:14PM +0300, Imre Deak wrote:
> This is v2 of [1]. I addressed Chris' and Ville's comments in it and
> rebased it against the latest -nightly kernel.
>
> [1]
> http://lists.freedesktop.org/archives/intel-gfx/2014-September/052199.html
>
> Imre Deak (14):
> drm/i915:
On Thu, Oct 23, 2014 at 08:35:24PM +0300, Mika Kuoppala wrote:
> because it is handy to direct bug reporters to do things like:
> 'grep -i suspend /sys/kernel/debug/dri/0/i915_gpu_state'
>
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 42
> ++
On Thu, Oct 23, 2014 at 07:23:23PM +0300, Imre Deak wrote:
> We already disable everything during S4 freeze, except the PCI device
> itself. There is no reason why we couldn't disable that too and doing
> so allows us to unify these handlers in the next patch with the
> corresponding S3 suspend/res
On Fri, Oct 24, 2014 at 08:30:56AM +, Daniel, Thomas wrote:
>
>
> > -Original Message-
> > From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
> > Vetter
> > Sent: Friday, October 24, 2014 9:15 AM
> > To: Daniel, Thomas
> > Cc: intel-gfx@lists.freedesktop.org; shua
On Thu, Oct 23, 2014 at 04:03:56PM +0530, akash.g...@intel.com wrote:
> From: Akash Goel
>
> This patch provides support to create uncached virtual mappings for a Gem
> object. It intends to provide the same funtionality of 'mmap_gtt' interface
> without the constraints of a limited aperture spac
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