Some of the Thinkpads' firmware will issue a backlight change request
through i915 operation region unconditionally on AC plug/unplug, the
backlight level used is arbitrary and thus should be ignored. This is
handled by commit 0b9f7d93ca61 (ACPI / i915: ignore firmware requests
for backlight change
On 09/26/2014 03:58 AM, Rafael J. Wysocki wrote:
> On Thursday, September 25, 2014 11:15:35 AM Aaron Lu wrote:
>> Hi Hans,
>>
>> Thanks for following up and explaining the situation to Pali.
>>
>> On 09/25/2014 02:21 AM, Pali Rohár wrote:
>>> On Wednesday 24 September 2014 16:34:21 Hans de Goede wr
bdw_sw_turbo is been enabled unconditionally and it is causing gpu to be busted.
GT freq stays on max value even when it is on idle or with screen off.
And if this isn't actually the case it is at least breaking the current rps API.
So let's let it disabled by default for now until it is properly
On Thursday, September 25, 2014 11:15:35 AM Aaron Lu wrote:
> Hi Hans,
>
> Thanks for following up and explaining the situation to Pali.
>
> On 09/25/2014 02:21 AM, Pali Rohár wrote:
> > On Wednesday 24 September 2014 16:34:21 Hans de Goede wrote:
> >> Ok, so the dell-laptop interface is just an
On Thursday, September 25, 2014 04:27:58 PM Wolfram Sang wrote:
>
> --Bn2rw/3z4jIqBvZU
> Content-Type: text/plain; charset=us-ascii
> Content-Disposition: inline
> Content-Transfer-Encoding: quoted-printable
>
> On Thu, Sep 25, 2014 at 09:22:01AM -0500, Felipe Balbi wrote:
> > On Thu, Sep 25, 201
As far as I can tell, the patch series (1->3) looks good. I was wondering how
the copyright header will be handled. Is that to be added manually later on?
Thanks,
Armin
-Original Message-
From: Mika Kuoppala [mailto:mika.kuopp...@linux.intel.com]
Sent: Wednesday, September 24, 2014 5:
-Original Message-
From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
Sent: Tuesday, September 23, 2014 12:31 AM
To: Shah, Suketu J
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915: WaRsClearFWBitsAtReset - WA for
blitter, render and media forcewake
2014-09-25 14:58 GMT-03:00 Jesse Barnes :
> This moved around on SKL, so we need to make sure we read/write the
> correct regs.
>
> v2: fixup WIN_POS offsets (Paulo)
> zero out WIN_POS reg at disable time (Paulo)
Reviewed-by: Paulo Zanoni
>
> Signed-off-by: Jesse Barnes
> Signed-off-by: Dam
This moved around on SKL, so we need to make sure we read/write the
correct regs.
v2: fixup WIN_POS offsets (Paulo)
zero out WIN_POS reg at disable time (Paulo)
Signed-off-by: Jesse Barnes
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/i915_reg.h | 12 +++
drivers/gpu/drm/
On Thu, Sep 25, 2014 at 10:36 AM, Paulo Zanoni wrote:
> 2014-09-24 19:16 GMT-03:00 Rodrigo Vivi :
> > Let's make sure PSR is propperly disabled before to re-enabled it.
> >
> > According to Spec, after disabled PSR CTL, the Idle state might occur
> > up to 24ms, that is one full frame time (1/ref
2014-09-24 20:50 GMT-03:00 Rodrigo Vivi :
> The sw cache clean on BDW is a tempoorary workaround because we cannot
> set cache clean on blt ring with risk of hungs. So we are doing the cache
> clean on sw.
> However we are doing much more than needed. Not only when using blt ring.
> So, with this
2014-09-24 19:16 GMT-03:00 Rodrigo Vivi :
> Let's make sure PSR is propperly disabled before to re-enabled it.
>
> According to Spec, after disabled PSR CTL, the Idle state might occur
> up to 24ms, that is one full frame time (1/refresh rate),
> plus SRD exit training time (max of 6ms),
> plus SRD
From: Clint Taylor
Haswell and later silicon has added a new pixel replication register
to the pipe timings for each transcoder. Now in addition to the
DPLL_A_MD register for the pixel clock double, we also need to write
to the TRANS_MULT_n (0x6002c) register to double the pixel data. Writing
to
That was a fast fix. Looks good now.
Reviewed-by: Arthur Runyan
v2: Arthur noticed I was changing the wrong bit.
Cc: Arthur Runyan
Cc: Paulo Zanoni
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_ddi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/g
BDW display - DP buffer translation values changed to give better margin.
Further change to entry 6; set dword 0 bit 31=1.
Both changes were approved already but this one didn't landed BSpec yet
this is why it is in a separated patch. Making reviewer's life easier.
Also alowing separated tests an
You updated FDI entry 6 here, but Predator r74080 is just DP entry 6. I'll
find out if FDI needs a similar change.
Cc: Arthur Runyan
Cc: Paulo Zanoni
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_ddi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers
From: Clint Taylor
HDMI audio clock config was incorrectly choosing the default for
pixel doubled interlaced modes. The table was missing pixel clock
values 13.500 (27.000) and 13.513 (27.027). Luckily the default N
value for 25.200 is the same N value for both 27MHz pixel clocks,
a warning messa
Hi all,
I've a 1440p display with a non-sufficient/corrupt EDID. I'm running
3.17.0-997-lowlatency #201409192205 from
http://kernel.ubuntu.com/~kernel-ppa/mainline/drm-intel-next/ and this
intel driver on Ubuntu 12.04 LTS, on a Thinkpad T420:
"Module intel: vendor="X.Org Foundation"
[ 9.541]
On Wed, Sep 24, 2014 at 10:46:17PM +0200, Rafael J. Wysocki wrote:
> On Wednesday, September 24, 2014 03:15:58 PM Felipe Balbi wrote:
> > On Wed, Sep 24, 2014 at 10:28:07PM +0200, Rafael J. Wysocki wrote:
> > > On Wednesday, September 24, 2014 09:44:50 PM Vinod Koul wrote:
> > > > This patch series
On Thu, Sep 25, 2014 at 09:22:01AM -0500, Felipe Balbi wrote:
> On Thu, Sep 25, 2014 at 01:27:18PM +0530, Vinod Koul wrote:
> > On Wed, Sep 24, 2014 at 03:32:19PM -0500, Felipe Balbi wrote:
> > > > > > OK, I guess this is as good as it gets.
> > > > > >
> > > > > > What tree would you like it go t
On Wed, Sep 24, 2014 at 10:28:07PM +0200, Rafael J. Wysocki wrote:
> On Wednesday, September 24, 2014 09:44:50 PM Vinod Koul wrote:
> > This patch series adds a simple macro pm_runtime_last_busy_and_autosuspend()
> > which invokes pm_runtime_mark_last_busy() and pm_runtime_put_autosuspend()
> > seq
On Thu, Sep 25, 2014 at 01:27:18PM +0530, Vinod Koul wrote:
> On Wed, Sep 24, 2014 at 03:32:19PM -0500, Felipe Balbi wrote:
> > > > > OK, I guess this is as good as it gets.
> > > > >
> > > > > What tree would you like it go through?
> > > >
> > > > Do we really need this new helper ? I mean, the
Looks good
Reviewed-by: Arthur Runyan
Cc: Arthur Runyan
Cc: Paulo Zanoni
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_ddi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index ba1103f
From: Daniele Ceraolo Spurio
These tracepoints are useful for observing the creation and
destruction of Full PPGTTs.
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 4
drivers/gpu/drm/i915/i915_trace.h | 40 +
2 files
On Thu, Sep 25, 2014 at 07:48:34AM -0700, Jesse Barnes wrote:
> Damien, did you want to make these changes as part of your re-post or
> should I send an updated patch to replace this one?
I wasn't planning to go through this one but let the author works for
his commit :)
--
Damien
__
On Tue, 23 Sep 2014 17:50:29 -0300
Paulo Zanoni wrote:
> 2014-09-04 8:27 GMT-03:00 Damien Lespiau :
> > From: Jesse Barnes
> >
> > This moved around on SKL, so we need to make sure we read/write the
> > correct regs.
> >
> > Signed-off-by: Jesse Barnes
> > Signed-off-by: Damien Lespiau
> > ---
On Thursday 25 September 2014 05:15:35 Aaron Lu wrote:
> Hi Hans,
>
> Thanks for following up and explaining the situation to Pali.
>
> On 09/25/2014 02:21 AM, Pali Rohár wrote:
> > On Wednesday 24 September 2014 16:34:21 Hans de Goede wrote:
> >> Ok, so the dell-laptop interface is just an obsol
On Thursday 25 September 2014 07:09 PM, Jani Nikula wrote:
On Thu, 25 Sep 2014, Shobhit Kumar wrote:
On Wednesday 24 September 2014 03:02 PM, Jani Nikula wrote:
On Wed, 24 Sep 2014, Gaurav K Singh wrote:
+ do {
Please never use a do-while when a regular for loop will do.
Hmm, ok bu
"Volkin, Bradley D" writes:
> On Wed, Sep 24, 2014 at 05:50:30AM -0700, Mika Kuoppala wrote:
>> In null/golden context there are multiple state commands where
>> the actual state is always zero. For more compact batch representation
>> add a macro which just emits command and the rest of the stat
On Thu, 25 Sep 2014, Shobhit Kumar wrote:
> On Wednesday 24 September 2014 03:02 PM, Jani Nikula wrote:
>> On Wed, 24 Sep 2014, Gaurav K Singh wrote:
>>> + do {
>>
>> Please never use a do-while when a regular for loop will do.
>
> Hmm, ok but reasoning ? Point here is that anyway we have to do
On Thu, Sep 25, 2014 at 01:43:31PM +0100, Tvrtko Ursulin wrote:
>
> On 09/25/2014 01:05 PM, Mika Kuoppala wrote:
> >Damien Lespiau writes:
> >
> >>On Thu, Sep 25, 2014 at 11:17:00AM +0100, Tvrtko Ursulin wrote:
> >>>From: Tvrtko Ursulin
> >>>
> >>>Write and reads following the block changed use
On Thu, Sep 25, 2014 at 03:00:53PM +0200, Jacek Danecki wrote:
> On 09/25/14 14:26, Chris Wilson wrote:
> > If we apply the fix in the kernel we break the
> > one user of it in beignet but fix all the existing users of mesa.
>
> Are you talking about fix in kernel which will provide 36 bits GPU ti
On 09/25/14 14:26, Chris Wilson wrote:
> The problem is that beignet already works around the broken hw read
> whereas mesa does not.
There is workaround in mesa already:
static uint64_t
ilo_get_timestamp(struct pipe_screen *screen)
{
struct ilo_screen *is = ilo_screen(screen);
union {
On Wednesday 24 September 2014 03:02 PM, Jani Nikula wrote:
On Wed, 24 Sep 2014, Gaurav K Singh wrote:
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi_cmd.c | 35 ++
1 file changed, 23 insertions(+), 12 deletio
On Wednesday 24 September 2014 02:31 PM, Daniel Vetter wrote:
On Wed, Sep 24, 2014 at 02:16:49PM +0530, Gaurav K Singh wrote:
Hi,
These set of patches build on top of the existing DSI Video mode support to
enable dual link MIPI panels with high resolutions. These patches have been
tested on a 25
On 09/25/2014 01:05 PM, Mika Kuoppala wrote:
Damien Lespiau writes:
On Thu, Sep 25, 2014 at 11:17:00AM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Write and reads following the block changed use engine specific use counters
and unless that is matched here force wake use counting goes
Rodrigo Vivi writes:
> This WA affect BDW GT3 E and F steppings.
>
> Signed-off-by: Rodrigo Vivi
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +-
> 2 files changed, 6 insertions(+), 1 deletion(-)
>
> diff
On Mon, Sep 22, 2014 at 06:22:53PM +0200, Jacek Danecki wrote:
> Current implementation of reading GPU timestamp is broken.
> It returns lower 32 bits shifted by 32 bits ( instead of
> ).
> Below change is adding possibility to read hi part of that register
> separ
Damien Lespiau writes:
> On Thu, Sep 25, 2014 at 11:17:00AM +0100, Tvrtko Ursulin wrote:
>> From: Tvrtko Ursulin
>>
>> Write and reads following the block changed use engine specific use counters
>> and unless that is matched here force wake use counting goes bad. Same
>> force wake is attempte
On Thu, Sep 25, 2014 at 11:17:00AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Write and reads following the block changed use engine specific use counters
> and unless that is matched here force wake use counting goes bad. Same
> force wake is attempted to be taken twice which leads
From: Tvrtko Ursulin
Write and reads following the block changed use engine specific use counters
and unless that is matched here force wake use counting goes bad. Same
force wake is attempted to be taken twice which leads to at least time outs.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/dr
As we use WC updates of the PTE, we are responsible for notifying the
hardware when to flush its TLBs. Do so after we zap all the PTEs before
suspend (and the BIOS tries to read our GTT).
Fixes a regression from
commit 828c79087cec61eaf4c76bb32c222fbe35ac3930
Author: Ben Widawsky
Date: Wed Oct
Bob Wang writes:
> On 09/24/2014 02:36 PM, Mika Kuoppala wrote:
>> Damien Lespiau writes:
>>
>>> From: Zhe Wang
>>>
>>> For MMIO registers which are shadowed, force wake is not needed to
>>> write to these registers.
>>>
>>> v2: Rebase on top of nightly (Damien)
>>>
>>> Signed-off-by: Zhe Wang
As we use WC updates of the PTE, we are responsible for notifying the
hardware when to flush its TLBs. Do so after we zap all the PTEs before
suspend (and the BIOS tries to read our GTT).
Fixes a regression from
commit 828c79087cec61eaf4c76bb32c222fbe35ac3930
Author: Ben Widawsky
Date: Wed Oct
On Thu, Sep 18, 2014 at 01:52:15PM +0200, Daniel Vetter wrote:
> On Thu, Sep 18, 2014 at 07:03:32AM +0100, Chris Wilson wrote:
> > As we use WC updates of the PTE, we are responsible for notifying the
> > hardware when to flush its TLBs. Do so after we zap all the PTEs before
> > suspend (and the B
On Wed, Sep 24, 2014 at 03:32:19PM -0500, Felipe Balbi wrote:
> > > > OK, I guess this is as good as it gets.
> > > >
> > > > What tree would you like it go through?
> > >
> > > Do we really need this new helper ? I mean, the very moment when we
> > > decide to implement ->runtime_idle() we will
On Wed, Sep 24, 2014 at 10:28:07PM +0200, Rafael J. Wysocki wrote:
>
> OK, I guess this is as good as it gets.
>
> What tree would you like it go through?
Since rest of the patches are dependent upon 1st patch which should go thru
your tree, we should merge this thru your tree
Thanks
--
~Vinod
Bob Wang writes:
> On 09/22/2014 04:11 PM, Mika Kuoppala wrote:
>> Damien Lespiau writes:
>>
>>> From: Zhe Wang
>>>
>>> Enable multi-engine forcewake for Gen9.
>>>
>>> v2: Rebase on top of nightly
>>> Move the register range definitions to intel_uncore.c
>>> Whitespace fixes
>>>
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