On Tue, Sep 23, 2014 at 03:50:25PM -0700, Joe Konno wrote:
> From: Joe Konno
>
> Improper integer division-- truncated rather than rounded-- in the
That's confusing. It reads that you are converting to using truncated,
rather than to rounding.
> scale() function causes actual_brightness != brig
On Tue, 2014-09-23 at 15:50 -0700, Joe Konno wrote:
> From: Joe Konno
>
> Improper integer division-- truncated rather than rounded-- in the
> scale() function causes actual_brightness != brightness. This (partial)
> work-around should be sufficient for a majority of use-cases, but it is
> by no
From: Joe Konno
Improper integer division-- truncated rather than rounded-- in the
scale() function causes actual_brightness != brightness. This (partial)
work-around should be sufficient for a majority of use-cases, but it is
by no means a complete solution.
TODO: Determine how best to scale "u
2014-09-16 20:19 GMT-03:00 Rodrigo Vivi :
> We don't need to setup everything else if it doesn't match all conditions.
Reviewed-by: Paulo Zanoni
>
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_dp.c | 10 ++
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff -
I had tried options but didn't liked because I was unable to list subtests...
so I gave back to env var...
But now I see that I was probably forgetting igt_subtest_init_parse_opts()
Thanks
Acked/Reviewed-by: Rodrigo Vivi
From: Daniel Vetter [daniel.vet
2014-09-16 20:19 GMT-03:00 Rodrigo Vivi :
> psr_enabled is already by itself a setup once so let's put the W/As there and
> rename old setup once to setup_vsc.
Yeah, I prefer the new way too.
Reviewed-by: Paulo Zanoni
>
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_dp.c | 1
2014-09-04 8:27 GMT-03:00 Damien Lespiau :
> From: Jesse Barnes
>
> This moved around on SKL, so we need to make sure we read/write the
> correct regs.
>
> Signed-off-by: Jesse Barnes
> Signed-off-by: Damien Lespiau
> ---
> drivers/gpu/drm/i915/i915_reg.h | 13
> drivers/gpu/drm/i
Hi,
On 09/23/2014 10:06 PM, Pali Rohár wrote:
Hello,
after big changes in acpi video/i915 code I cannot change display
brightness on my Dell Latitude E6440 with kernel 3.17-rc6. With
kernel 3.13 everything worked fine.
More information about this problem:
For configuring brightness on Dell la
To be used for a Workaroud. Similar to:
commit 884ceacee308f0e4616d0c933518af2639f7b1d8
Author: Kenneth Graunke
Date: Sat Jun 28 02:04:20 2014 +0300
drm/i915: Refactor Broadwell PIPE_CONTROL emission into a helper.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_lrc.c | 35 ++
Similar to:
commit 02c9f7e3cfe76a7f54ef03438c36aade86cc1c8b
Author: Kenneth Graunke
Date: Mon Jan 27 14:20:16 2014 -0800
drm/i915: Add the WaCsStallBeforeStateCacheInvalidate:bdw workaround.
On Broadwell, any PIPE_CONTROL with the "State Cache Invalidate" bit set
must be preceded
2014-09-04 8:27 GMT-03:00 Damien Lespiau :
> A few bits have changed in MI_DISPLAY_FLIP to accomodate the new planes.
> DE_RRMR seems to have kept its plane flip bits backward compatible.
>
> v2: Rebase on top of nightly
> v2: Rebase on top of nightly (minor conflict in i915_reg.h)
>
> Signed-off-b
2014-09-04 8:27 GMT-03:00 Damien Lespiau :
> From: Vandana Kannan
>
> The eDP WA to stop link train based on port type is for HSW/BDW, not
> required for SKL+.
> Suggested by Satheesh
>
> v2: Simplified the check befoe stop_link_train. Suggested by Satheesh.
>
> v3: stop_link_train need not be cal
2014-09-04 8:27 GMT-03:00 Damien Lespiau :
> v2: rebase on top of the hw state flattening.
Reviewed-by: Paulo Zanoni
>
> Signed-off-by: Damien Lespiau
> ---
> drivers/gpu/drm/i915/intel_display.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
From: Clint Taylor
Haswell and later silicon has added a new pixel replication register
to the pipe timings for each transcoder. Now in addition to the
DPLL_A_MD register for the pixel clock double, we also need to write to
the TRANS_MULT_n (0x6002c) register to double the pixel data. Writing
to
2014-09-04 8:27 GMT-03:00 Damien Lespiau :
> From: Satheeshakrishna M
>
> This patch implements SKL DPLL programming that includes:
> - DPLL allocation
> - wide range PLL calculation and programming
> - DP link rate programming
> - DDI to DPLL mapping
>
> v2: Incorp
On 09/23/14 10:37, Daniel Vetter wrote:
> On Mon, Sep 22, 2014 at 06:22:53PM +0200, Jacek Danecki wrote:
>> Current implementation of reading GPU timestamp is broken.
>> It returns lower 32 bits shifted by 32 bits ( instead of
>> ).
>> Below change is adding possibi
On Tue, Sep 23, 2014 at 12:41:56PM -0300, Gustavo Padovan wrote:
> 2014-09-23 Ville Syrjälä :
>
> > On Mon, Sep 22, 2014 at 07:23:10PM -0300, Gustavo Padovan wrote:
> > > From: Gustavo Padovan
> > >
> > > Move checks inside intel_crtc_cursor_set_obj() to
> > > intel_check_cursor_plane(), we only
From: Pradeep Bhat
This patch defines the structures needed for computation of
watermarks of pipes and planes for SKL.
v2: Incorporated Damien's review comments and removed unused fields
in structs for future features like rotation, drrs and scaling.
The skl_wm_values struct is now made
On 9/23/2014 2:21 PM, Jani Nikula wrote:
On Wed, 17 Sep 2014, Michel Thierry wrote:
On 9/17/2014 11:20 AM, Jani Nikula wrote:
FYI, Mika has posted the fix:
http://mid.gmane.org/1411146326-9884-1-git-send-email-mika.kuopp...@intel.com
Thanks, (Has it been merged? I can't find it in nightly)
2014-09-04 8:27 GMT-03:00 Damien Lespiau :
> From: Satheeshakrishna M
>
> DPLL0 is not part of the shared PLL infrastructure. We'll use on for
> eDP and rely on what the BIOS does for now.
>
> Signed-off-by: Satheeshakrishna M
> Signed-off-by: Damien Lespiau
> ---
> drivers/gpu/drm/i915/intel_d
2014-09-04 8:27 GMT-03:00 Damien Lespiau :
> From: Satheeshakrishna M
>
> Skylake deprecates the usage of PORT_CLK_SEL and we are advised to use
> the new DPLL_CRTL2 for the DDI->PLL mapping.
>
> Signed-off-by: Satheeshakrishna M
> Signed-off-by: Damien Lespiau
> ---
> drivers/gpu/drm/i915/inte
2014-09-04 8:27 GMT-03:00 Damien Lespiau :
> From: Satheeshakrishna M
>
> On skylake, DPLL 1, 2 and 3 can be used for DP and HDMI. The shared dpll
> framework allows us to share those DPLLs among DDIs when possible.
>
> The most tricky part is to provide a DPLL state that can be easily
> compared.
On 23/09/14 15:51, Daniel Vetter wrote:
On Tue, Sep 23, 2014 at 03:48:25PM +0300, Jani Nikula wrote:
On Mon, 15 Sep 2014, Daniel Vetter wrote:
On Sat, Sep 13, 2014 at 06:25:54PM +0200, Mario Kleiner wrote:
The current drm-next misses Ville's original Patch 14/19, the one i first
objected, the
On Wed, 17 Sep 2014, Daniel Vetter wrote:
> On Wed, Sep 17, 2014 at 03:34:58PM +0300, Jani Nikula wrote:
>> Check the correct bit for audio. Seems like a copy-paste error from the
>> start:
>>
>> commit 9ed109a7b445e3f073d8ea72f888ec80c0532465
>> Author: Daniel Vetter
>> Date: Thu Apr 24 23:54
On Tue, Sep 23, 2014 at 03:48:25PM +0300, Jani Nikula wrote:
> On Mon, 15 Sep 2014, Daniel Vetter wrote:
> > On Sat, Sep 13, 2014 at 06:25:54PM +0200, Mario Kleiner wrote:
> >> The current drm-next misses Ville's original Patch 14/19, the one i first
> >> objected, then objected to my objection. I
On Wed, 17 Sep 2014, Michel Thierry wrote:
> On 9/17/2014 11:20 AM, Jani Nikula wrote:
>>
>> IMHO it would be perilous to apply these patches before we have root
>> caused https://bugs.freedesktop.org/show_bug.cgi?id=83482. I think we
>> need to be able to revert those changes if we can't fix the
Env variables are a bit more annoying since much harder to discover.
With options you can just see what they do with --help.
Cc: Rodrigo Vivi
Signed-off-by: Daniel Vetter
---
tests/kms_psr_sink_crc.c | 30 --
1 file changed, 24 insertions(+), 6 deletions(-)
diff --g
On Tue, 23 Sep 2014, Daniel Vetter wrote:
> On Mon, Sep 22, 2014 at 08:25:21AM -0700, bradley.d.vol...@intel.com wrote:
>> From: Brad Volkin
>>
>> Ring init and cleanup are not balanced because we re-init the rings on
>> resume without having cleaned them up on suspend. This leads to the
>> driv
On Mon, 15 Sep 2014, Daniel Vetter wrote:
> On Sat, Sep 13, 2014 at 06:25:54PM +0200, Mario Kleiner wrote:
>> The current drm-next misses Ville's original Patch 14/19, the one i first
>> objected, then objected to my objection. It is needed to avoid actual
>> regressions. Attached a trivially reba
On Tue, 23 Sep 2014, 陳勇秀 wrote:
> Hi All,
>
> I am using a baytrail cpu and linux kernel 3.14.7, and will echo some
> message to /dev/tty1 during boot.
>
> There is chance that no display output during boot, but I can use linux via
> ttyS4, the HSUART.
>
> Attached is output of intel_reg_dumper,
>
On Thu, 18 Sep 2014, Daniel Vetter wrote:
> On Thu, Sep 18, 2014 at 07:03:32AM +0100, Chris Wilson wrote:
>> As we use WC updates of the PTE, we are responsible for notifying the
>> hardware when to flush its TLBs. Do so after we zap all the PTEs before
>> suspend (and the BIOS tries to read our G
On Tue, 23 Sep 2014, Daniel Vetter wrote:
> On Fri, Sep 19, 2014 at 08:49:06PM +0300, Ville Syrjälä wrote:
>> On Fri, Sep 19, 2014 at 08:05:26PM +0300, Mika Kuoppala wrote:
>> > as these have been fixed in production hw and hurt performance
>> > if applied.
>> >
>> > v2: adjust requested ring spa
On Tue, Sep 23, 2014 at 10:14:33AM +0100, Chris Wilson wrote:
> On Tue, Sep 23, 2014 at 10:34:46AM +0200, Daniel Vetter wrote:
> > On Mon, Sep 22, 2014 at 08:25:21AM -0700, bradley.d.vol...@intel.com wrote:
> > > From: Brad Volkin
> > >
> > > Ring init and cleanup are not balanced because we re-i
On Tue, Sep 23, 2014 at 10:19:02AM +0100, Chris Wilson wrote:
> On Tue, Sep 23, 2014 at 10:26:26AM +0200, Daniel Vetter wrote:
> > On Fri, Sep 19, 2014 at 09:00:00PM +0100, Chris Wilson wrote:
> > > On Fri, Sep 19, 2014 at 06:21:46PM +, Tian, Kevin wrote:
> > > > > From: Chris Wilson
> > > > >
v2: Fix the 3rd plane/cursor logic (Pradeep Bhat)
v3: Fix one-by-one error in the DDB allocation code
v4: Rebase on top of the skl_pipe_pixel_rate() argument change
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_pm.c | 150
1 file changed, 1
From: Pradeep Bhat
This patch defines SKL specific PLANE_WM Watermark registers. It also
defines macros to get the addresses of different LP levels within a pipe.
v2: Reworked the register definitions and associated macros to make it more
generic and be able to use for_each_pipe in values co
From: Pradeep Bhat
This patch implements the watermark algorithm and its necessary
functions. Two function pointers skl_update_wm and
skl_update_sprite_wm are provided. The skl_update_wm will update
the watermarks for the crtc provided as an argument and then
checks for change in DDB allocation f
On Wed, Sep 17, 2014 at 03:07:51PM +0300, Ville Syrjälä wrote:
> On Thu, Sep 04, 2014 at 12:27:13PM +0100, Damien Lespiau wrote:
> > From: Pradeep Bhat
> >
> > This patch implements the watermark algorithm and its necessary
> > functions. Two function pointers skl_update_wm and
> > skl_update_spr
On 2014.09.23 10:38:49 +0200, Daniel Vetter wrote:
> On Tue, Sep 23, 2014 at 12:41:50AM +0200, Michał Winiarski wrote:
> > These registers are used as a temporary storage by MI_MATH command when
> > performing ALU operations.
> >
> > Signed-off-by: Michał Winiarski
>
> Needs to come with corresp
On Tue, Sep 23, 2014 at 10:26:26AM +0200, Daniel Vetter wrote:
> On Fri, Sep 19, 2014 at 09:00:00PM +0100, Chris Wilson wrote:
> > On Fri, Sep 19, 2014 at 06:21:46PM +, Tian, Kevin wrote:
> > > > From: Chris Wilson
> > > > The implementation also looks backwards. To work correctly with the GTT
On Tue, Sep 23, 2014 at 10:34:46AM +0200, Daniel Vetter wrote:
> On Mon, Sep 22, 2014 at 08:25:21AM -0700, bradley.d.vol...@intel.com wrote:
> > From: Brad Volkin
> >
> > Ring init and cleanup are not balanced because we re-init the rings on
> > resume without having cleaned them up on suspend. T
On Fri, Sep 12, 2014 at 11:13:03PM +0530, Vandana Kannan wrote:
> As part of implementing DRRS based on frontbuffer tracking, this patch series
> includes some modifications related to the data for DRRS, code to enable/
> disable DRRS during init or uninit, calls to switch between high and low
> re
On Fri, Sep 12, 2014 at 11:13:07PM +0530, Vandana Kannan wrote:
> Calls to switch between high and low refresh rates based on calls made to
> fb_invalidate and fb_flush.
>
> Signed-off-by: Vandana Kannan
A few comments below.
-Daniel
> ---
> drivers/gpu/drm/i915/intel_display.c | 5
> dr
On Fri, Sep 12, 2014 at 11:13:04PM +0530, Vandana Kannan wrote:
> Moving around and changing some data related to DRRS to support
> DRRS based on frontbuffer tracking in the following patches
>
> Signed-off-by: Vandana Kannan
The commit message is a bit too sparse imo. You shouldn't just describ
On Tue, Sep 23, 2014 at 12:41:50AM +0200, Michał Winiarski wrote:
> These registers are used as a temporary storage by MI_MATH command when
> performing ALU operations.
>
> Signed-off-by: Michał Winiarski
Needs to come with corresponding userspace using this. Also we need to rev
the cmd parser r
On Mon, Sep 22, 2014 at 06:22:53PM +0200, Jacek Danecki wrote:
> Current implementation of reading GPU timestamp is broken.
> It returns lower 32 bits shifted by 32 bits ( instead of
> ).
> Below change is adding possibility to read hi part of that register
> separ
On Mon, Sep 22, 2014 at 08:25:21AM -0700, bradley.d.vol...@intel.com wrote:
> From: Brad Volkin
>
> Ring init and cleanup are not balanced because we re-init the rings on
> resume without having cleaned them up on suspend. This leads to the
> driver leaking the parser's hash tables with a kmemlea
On Fri, Sep 19, 2014 at 12:44:08PM -0700, Rodrigo Vivi wrote:
> Reviewed-by: Rodrigo Vivi
Both patches merged to dinq.
> But I think it would be good now to change fbc_status interface on debugfs
> to show the current bit state as well.
Seconded. Also some locking for fbc would be awesome ;-)
On Fri, Sep 19, 2014 at 09:00:00PM +0100, Chris Wilson wrote:
> On Fri, Sep 19, 2014 at 06:21:46PM +, Tian, Kevin wrote:
> > > From: Chris Wilson
> > > The implementation also looks backwards. To work correctly with the GTT
> > > allocator, you need to preallocate the reserved space such that i
On Fri, Sep 19, 2014 at 08:49:06PM +0300, Ville Syrjälä wrote:
> On Fri, Sep 19, 2014 at 08:05:26PM +0300, Mika Kuoppala wrote:
> > as these have been fixed in production hw and hurt performance
> > if applied.
> >
> > v2: adjust requested ring space (Ville)
> >
> > Bugzilla: https://bugs.freedes
On Mon, Sep 22, 2014 at 03:21:22PM +0100, Damien Lespiau wrote:
> On Mon, Sep 22, 2014 at 05:06:11PM +0300, Ville Syrjälä wrote:
> > > +struct skl_pipe_wm {
> > > + struct skl_wm_level wm[8];
> > > + struct skl_wm_level trans_wm;
> > > + uint32_t linetime;
> > > +};
> > > +
> > > struct intel_crtc
On Fri, Sep 19, 2014 at 08:58:58PM +0300, Ville Syrjälä wrote:
> On Wed, Jun 18, 2014 at 12:23:14PM +0100, Chris Wilson wrote:
> > Since mmio-flips do not occur on the suggested ring, we are introducing
> > an extra sync operation where none is required. Pass the current
> > obj->ring, which is wha
On Mon, Sep 22, 2014 at 07:23:10PM -0300, Gustavo Padovan wrote:
> From: Gustavo Padovan
>
> Move checks inside intel_crtc_cursor_set_obj() to
> intel_check_cursor_plane(), we only use they there so move them out to
> make the merge of intel_crtc_cursor_set_obj() into
> intel_check_cursor_plane()
On Mon, Sep 22, 2014 at 07:23:09PM -0300, Gustavo Padovan wrote:
> From: Gustavo Padovan
>
> Now that universal planes are in place we don't need this plane unref on
> failures.
>
> Suggested-by: Ville Syrjälä
> Signed-off-by: Gustavo Padovan
> ---
> drivers/gpu/drm/i915/intel_display.c | 8 +
On Mon, Sep 22, 2014 at 07:23:08PM -0300, Gustavo Padovan wrote:
> From: Gustavo Padovan
>
> Fold intel_pipe_set_base() in the update primary plane path merging
> pieces of code that are common to both paths.
>
> Basically the the pin/unpin procedures are the same for both paths
> and some check
On Mon, Sep 22, 2014 at 02:43:02PM -0400, Suketu Shah wrote:
> The newly loaded Gfx driver must first initialize the forcewake request
> register
> for render, media and blitter engines by clearing all forcewake bits
> (0x).
> This applies to BDW and GEN9 platforms.
Already done
intel_un
Hi Michel:
I'm doing a task which require LRIs to load root pointer around RCS
context switch.My BDW CPU is C stepping. And what I found is
MI_SET_CONTEXT instruction will save/restore PDP0/1/2/3. It's weired
that as part of EXECLIST context, the "EXECLIST PPGTT base" context also
appear i
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