On Mon, Sep 22, 2014 at 07:23:08PM -0300, Gustavo Padovan wrote:
> From: Gustavo Padovan
>
> Fold intel_pipe_set_base() in the update primary plane path merging
> pieces of code that are common to both paths.
>
> Basically the the pin/unpin procedures are the same for both paths
> and some check
On Tuesday 23 September 2014 04:06 AM, Damien Lespiau wrote:
Hi Satheesh,
On Wed, Sep 17, 2014 at 03:07:51PM +0300, Ville Syrjälä wrote:
+static bool skl_compute_plane_wm(struct skl_pipe_wm_parameters *p,
+ struct intel_plane_wm_parameters *p_params,
+
These registers are used as a temporary storage by MI_MATH command when
performing ALU operations.
Signed-off-by: Michał Winiarski
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 16
drivers/gpu/drm/i915/i915_reg.h| 3 +++
2 files changed, 19 insertions(+)
diff --git a/dr
Hi Satheesh,
On Wed, Sep 17, 2014 at 03:07:51PM +0300, Ville Syrjälä wrote:
> > +static bool skl_compute_plane_wm(struct skl_pipe_wm_parameters *p,
> > + struct intel_plane_wm_parameters *p_params,
> > + uint16_t max_page_buff_alloc,
> > +
From: Gustavo Padovan
After some refactor intel_primary_plane_setplane() does the same
as intel_pipe_set_base() so we can get rid of it and replace the calls
with intel_primary_plane_setplane().
v2: take Ville's comments:
- get the right arguments for update_plane()
- use drm_crt
From: Daniel Stone
Start the work of splitting the intel_crtc_page_flip() for later use
by the atomic modesetting API.
Signed-off-by: Daniel Stone
Signed-off-by: Gustavo Padovan
---
drivers/gpu/drm/i915/intel_display.c | 51 ++--
1 file changed, 37 insertions(+
From: Gustavo Padovan
Take out the pin_fb code so commit phase can't fail anymore.
Signed-off-by: Gustavo Padovan
---
drivers/gpu/drm/i915/intel_display.c | 35 ++-
1 file changed, 26 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display
From: Gustavo Padovan
take out pin_fb code so the commit phase can't fail anymore.
Signed-off-by: Gustavo Padovan
---
drivers/gpu/drm/i915/intel_sprite.c | 63 +++--
1 file changed, 40 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprit
From: Gustavo Padovan
Move checks inside intel_crtc_cursor_set_obj() to
intel_check_cursor_plane(), we only use they there so move them out to
make the merge of intel_crtc_cursor_set_obj() into
intel_check_cursor_plane() easier.
This is another step toward the atomic modesetting support and unif
From: Gustavo Padovan
We need to get hdisplay and vdisplay in a few places so create a
helper to make our job easier.
Suggested-by: Ville Syrjälä
Signed-off-by: Gustavo Padovan
---
drivers/gpu/drm/drm_crtc.c | 20 +---
drivers/gpu/drm/i915/intel_display.c | 6 +++---
From: Gustavo Padovan
Merge it into the plane update_plane() callback and make other
users use the update_plane() functions instead.
The fb != crtc->cursor->fb was already inside intel_crtc_cursor_set_obj()
so we fold intel_crtc_cursor_set_obj() inside intel_commit_cursor_plane()
and merge both
From: Gustavo Padovan
Use the macros makes the code cleaner and it also checks for a NULL fb.
Signed-off-by: Gustavo Padovan
---
drivers/gpu/drm/i915/intel_sprite.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/dr
From: Gustavo Padovan
Now that universal planes are in place we don't need this plane unref on
failures.
Suggested-by: Ville Syrjälä
Signed-off-by: Gustavo Padovan
---
drivers/gpu/drm/i915/intel_display.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/
From: Gustavo Padovan
Fold intel_pipe_set_base() in the update primary plane path merging
pieces of code that are common to both paths.
Basically the the pin/unpin procedures are the same for both paths
and some checks can also be shared (some of the were moved to the
check() stage)
v2: take Vi
The newly loaded Gfx driver must first initialize the forcewake request register
for render, media and blitter engines by clearing all forcewake bits
(0x).
This applies to BDW and GEN9 platforms.
Change-Id: I633c530340a5918c084249a188d0397ed4f51a41
Signed-off-by: Suketu Shah
---
drivers
2014-09-04 8:27 GMT-03:00 Damien Lespiau :
> From: Satheeshakrishna M
>
> Modify the implementation to query DPLL attached to a SKL port.
>
> v2: Rebase on top of the run-time PM on DPMS series (Damien)
>
> Signed-off-by: Satheeshakrishna M
> Signed-off-by: Damien Lespiau
> ---
> drivers/gpu/dr
2014-09-04 8:27 GMT-03:00 Damien Lespiau :
> From: Satheeshakrishna M
>
> v2: Fixup compilation due to the removal of the intel_ddi_dpll_id enum.
> And add a fixme about the abuse of pipe_config here.
>
> v3: Rebase on top of the hsw_ddi_clock_get() rename (Damien)
>
> Signed-off-by: Satheeshakris
Oh! ok, so let's not block the progress
Thanks, so feel free to use:
Reviewed-by: Rodrigo Vivi
On Mon, Sep 22, 2014 at 6:42 AM, Damien Lespiau
wrote:
> On Wed, Sep 17, 2014 at 03:18:21PM -0700, Rodrigo Vivi wrote:
> >Where can I find these pch device id definitions?
>
> You'll have to tru
Thanks, so feel free to use:
Reviewed-by: Rodrigo Vivi
On Mon, Sep 22, 2014 at 6:21 AM, Damien Lespiau
wrote:
> On Tue, Sep 16, 2014 at 06:12:04PM -0700, Rodrigo Vivi wrote:
> >I believe this patch should remove the gen9 part of
> >ilk_get_aux_clock_divider.
>
> The previous patch chan
2014-09-04 8:27 GMT-03:00 Damien Lespiau :
> From: Satheeshakrishna M
>
> Determine programmed cd clock for SKL.
>
> v2: Fix the LCPLL1 enable warning logic
>
> v3: Rebase over the hsw pll rework.
>
> v4: Rebase on top of the per-platform split (Damien)
>
> Signed-off-by: Satheeshakrishna M
> Sig
On Mon, Sep 22, 2014 at 03:08:27PM +0100, Damien Lespiau wrote:
> On Wed, Sep 17, 2014 at 01:47:54PM +0300, Ville Syrjälä wrote:
> > On Thu, Sep 04, 2014 at 12:27:12PM +0100, Damien Lespiau wrote:
> > > We now need to allocate space in the DDB for planes being scanned out
> > > ourselves. The data
2014-09-04 8:27 GMT-03:00 Damien Lespiau :
> From: Satheeshakrishna M
>
> Adding structure/enum for SKL clocking implementation.
>
> v2: Addressed Damien's comment
> - Removed internal structure from this header file
>
> v3: Stove this into the generic intel_dpll_id enum and give them the
2014-09-04 8:27 GMT-03:00 Damien Lespiau :
> From: Satheeshakrishna M
>
> This patch defines the necessary SKL registers for implementing the
> new clocking mechanism.
>
> v2: Addressed review comments by Damien
> - Added code comment
> - Introduced enum for WRPLL values
>
> v3: Re
Current implementation of reading GPU timestamp is broken.
It returns lower 32 bits shifted by 32 bits ( instead of
).
Below change is adding possibility to read hi part of that register separately.
Signed-off-by: Jacek Danecki jacek.dane...@intel.com
---
diff --g
From: Brad Volkin
Ring init and cleanup are not balanced because we re-init the rings on
resume without having cleaned them up on suspend. This leads to the
driver leaking the parser's hash tables with a kmemleak signature such
as this:
unreferenced object 0x880405960980 (size 32):
comm "s
Damien Lespiau writes:
> From: Zhe Wang
>
> Enable multi-engine forcewake for Gen9.
>
> v2: Rebase on top of nightly
> Move the register range definitions to intel_uncore.c
> Whitespace fixes
> (Damien)
>
> Signed-off-by: Zhe Wang
> Signed-off-by: Damien Lespiau
> ---
> drivers/gp
On Mon, Sep 22, 2014 at 05:06:11PM +0300, Ville Syrjälä wrote:
> > +struct skl_pipe_wm {
> > + struct skl_wm_level wm[8];
> > + struct skl_wm_level trans_wm;
> > + uint32_t linetime;
> > +};
> > +
> > struct intel_crtc {
> > struct drm_crtc base;
> > enum pipe pipe;
> > @@ -431,9 +43
On Wed, Sep 17, 2014 at 01:47:54PM +0300, Ville Syrjälä wrote:
> On Thu, Sep 04, 2014 at 12:27:12PM +0100, Damien Lespiau wrote:
> > We now need to allocate space in the DDB for planes being scanned out
> > ourselves. The data structure to represent an allocation mirrors what
> > we'll need to writ
On Thu, Sep 04, 2014 at 12:27:11PM +0100, Damien Lespiau wrote:
> From: Pradeep Bhat
>
> This patch defines the structures needed for computation of
> watermarks of pipes and planes for SKL.
>
> v2: Incorporated Damien's review comments and removed unused fields
> in structs for future featu
On Wed, Sep 17, 2014 at 05:59:24PM +0200, Daniel Vetter wrote:
> On Wed, Sep 17, 2014 at 02:59:00PM +0100, Damien Lespiau wrote:
> > On Wed, Sep 10, 2014 at 09:39:53PM +0300, Ville Syrjälä wrote:
> > > > +struct skl_wm_values {
> > > > + bool dirty[I915_MAX_PIPES];
> > > > + uint32_t wm
On Wed, Sep 17, 2014 at 12:00:39PM -0700, Rodrigo Vivi wrote:
>Although I believe that we could have a init_workaround function for skl
>as we have for bdw and chv
FWIW, the W/A code is in a confusing state right now, with at least two
people working on it. I'd like to wait a bit before th
On Wed, Sep 17, 2014 at 03:18:21PM -0700, Rodrigo Vivi wrote:
>Where can I find these pch device id definitions?
You'll have to trust Satheesh on that, it's not something we have
documented in the GPU specs.
--
Damien
>On Thu, Sep 4, 2014 at 4:26 AM, Damien Lespiau
>wrote:
>
>
On Wed, Sep 17, 2014 at 11:41:54AM -0700, Rodrigo Vivi wrote:
>Oh cool here are the actual fixes on de_pipe int bits!
>I agree with Daniel that a separated function would be better, but what is
>here is right anyway so
Took a note about that. Will have to wait for when the situation h
On Tue, Sep 16, 2014 at 06:50:47PM -0700, Rodrigo Vivi wrote:
>isn't fdi_link_training needed?
No, it's not. SKL doesn't have FDI.
--
Damien
>if not: Reviewed-by: Rodrigo Vivi
>On Thu, Sep 4, 2014 at 4:26 AM, Damien Lespiau
>wrote:
>
> From: Satheeshakrishna M
>
>
On Tue, Sep 16, 2014 at 06:27:04PM -0700, Rodrigo Vivi wrote:
>This seems to allow more than just the RCS timestamp, but also allow
>the I915_REG_READ ioctl for gen9.
Well, yes, this array is the white list for the reg_read ioctl, so
that's expected.
>Anyway:
>Reviewed-by: Rodrigo
On Tue, Sep 16, 2014 at 06:12:04PM -0700, Rodrigo Vivi wrote:
>I believe this patch should remove the gen9 part of
>ilk_get_aux_clock_divider.
The previous patch changing ilk_get_aux_clock_divider() got removed
entirely.
>Also there it just returns 0, but here it returns 0 or 1 depend
Damien Lespiau writes:
> From: Zhe Wang
>
> Configure and enable RC6 for Gen9.
>
> v2: Rebase on top of BDW rc6 support (Damien)
>
> Signed-off-by: Zhe Wang
> Signed-off-by: Damien Lespiau
> ---
> drivers/gpu/drm/i915/intel_pm.c | 52
> -
> 1 file chan
On Mon, Sep 22, 2014 at 03:10:05PM +0800, Jike Song wrote:
> On 09/19/2014 04:07 PM, Chris Wilson wrote:
> >This should be done inside intel_enable_fbc() so that the correct reason
> >is given as to why it is disabled.
>
> I'm sorry, but do you mean intel_update_fbc()?
Yes. But don't let me stop
On Mon, Sep 22, 2014 at 07:17:41PM +0800, Jike Song wrote:
> Thanks for the demo. Currently sanitize_enable_ppgtt() is called by
> i915_gem_gtt_init(), before
> intel_check_vgpu().
>
> I'm trying to detect VGPU as early as possible, maybe between
> intel_detect_pch() and intel_uncore_init(),
> u
On 09/19/2014 04:25 PM, Chris Wilson wrote:
This should be moved to sanitize_enable_ppgtt(), probably by expanding
HAS_PPGTT(), e.g.:
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 07dafa2c2d8c..b1fa13942d14 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++
Skylake makes primary planes the same as sprite planes and call the
result "universal planes".
This commit emulates a primary plane with plane 0, taking the
opportunity to redefine primary and sprite registers to be identical now
that the underlying hardware is. It also makes sense as plenty of fi
On Fri, Sep 19, 2014 at 06:31:25PM -0300, Gustavo Padovan wrote:
> 2014-09-19 Ville Syrjälä :
>
> > On Thu, Sep 18, 2014 at 04:43:16PM -0300, Gustavo Padovan wrote:
> > > From: Gustavo Padovan
> > >
> > > After some refactor intel_primary_plane_setplane() does the same
> > > as intel_pipe_set_ba
Hi Chris,
> This patch extends the current DRM_I915_GEM_GET_APERTURE ioctl to
> include a couple of new fields in its reply to userspace - the total
> amount of space available in the mappable region of the aperture and
> also the single largest block available.
Would it be possible to include th
On Sun, Sep 21, 2014 at 07:20:09PM +0100, Chris Wilson wrote:
> If you attempt to use xrandr --rotation inverted at the moment, the
> kernel disables the output when attempting to update the plane
> rotation. This is because the primary plane src/dst rectangle is never
> initialised and so it attem
On 09/19/2014 04:07 PM, Chris Wilson wrote:
On Sat, Sep 20, 2014 at 02:47:04AM +0800, Jike Song wrote:
From: Yu Zhang
Framebuffer compression is disabled when driver detects it's
running in XenGT VM, because XenGT does not provide emulations
for FBC related operations, and we do not expose sto
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