From: Dave Airlie
This is probably not the greatest idea in the world, but if userspace
does a modesetting sequences
initial state : crtc 0 -> eDP-1
modeset : crtc 1 -> DP-4 (dual crtc)
we have to steal crtc 2 for DP-3
modeset : crtc 2 -> eDP-1
we are kind off stuck, so when we see this, we bac
From: Dave Airlie
Since DP MST has new userspace requirements and any effort at trying
to shoehorn things into the something the current userspace can handle are
doomed, lets just put this behind a config option.
This also adds a command line arg to switch it on as well.
Distros should probably
From: Dave Airlie
Using the tiling info attempt to set a mode across two crtcs
---
drivers/gpu/drm/drm_crtc.c| 100 +-
drivers/gpu/drm/drm_displayid.c | 13 -
drivers/gpu/drm/drm_dp_mst_topology.c | 18 +-
drivers/gpu/drm/drm_edid.c
All these are on top of rc3 (also in my drm-mst-hide-monitor branch).
So after talking to Keith and Daniel in Chicago I decided to give
another go at hiding the horror that is 30" 4k dual-panel MST
monitors in the kernel.
Also this hw is not going away, if anything it seems to be getting
worse wi
From: Dave Airlie
This gives us a base identifier to group tiled outputs from.
However after reading about the Dell 5k monitor I expect this
is probably too little, and we need some sort of hash table
from the monitor EDID serial number.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/drm_dp_m
From: Dave Airlie
This patches the EDID to add the special mode.
TODO make this more generic.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/drm_dp_mst_topology.c | 13 ++---
drivers/gpu/drm/drm_edid.c| 36 +++
include/drm/drm_edid.h
From: Dave Airlie
The old code has problems with the Dell MST monitors due to some
assumptions I made that weren't true.
I initially thought the Virtual Channel Payload IDs had to be in
the DPCD table in ascending order, however it appears that assumption
is bogus.
The old code also assumed it
From: Dave Airlie
Just enough to get the tiling info from a Dell 4k monitor.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/Makefile | 2 +-
drivers/gpu/drm/drm_displayid.c| 68 ++
drivers/gpu/drm/drm_edid.c | 29 ++--
driv
From: Dave Airlie
For the monitors with panels we only want EDID once,
and they show up on logical ports, which are always connected.
This is required as if we start hiding connector status
we won't be able to get the EDID normally later.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/drm_dp_
From: Dave Airlie
So when userspace asks us to set a mode on a tiled crtc,
split it up and find the actual modes and attempt to set them.
Also disable crtcs when no longer in tiled group.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/drm_crtc.c| 51 +++
From: Dave Airlie
This is OMG bad, but in order to get semantics that don't defeat
userspace we have to wait for both flips to complete.
So rewrite the event handling code to make sure we wait for
all crtcs in the tile group to complete flipping.
The main problem otherwise is userspace does
ad
From: Dave Airlie
This is going to be a bit of a reference counting nightmare,
Since when we moved from one tile to the other, we need to
transfer the framebuffer over between them.
Also only universal is tackled here.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/drm_crtc.c | 33 ++
From: Shashank Sharma
This patch does following things:
1. Adds new function to attach color proprties with
corresponsing crtc / plane objects.
2. Call these attach functions, from corresponding crtc/plane
init functions.
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/i915/intel_clrm
From: Shashank Sharma
Add set_property function in CRTC ops.
This function will be required for color correction properties.
Userspace will do a set_property operation on CRTC object, to
do display tuning or color correction.
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/i915/intel_displa
From: Shashank Sharma
This patch adds support for CSC correction color property.
It does the following:
1. Creates a new DRM property for CSC correction. Adds this into
mode_config.
2. Attaches this CSC property to calling CRTC. Creates a blob
to store the correction values, and attaches th
From: Shashank Sharma
Color manager is a framework which adds drm properties for
color correction in I915 driver. This framework creates DRM
properties for each color correction feature, and attaches
it to appropriate CRTC/plane based on the property type.
This allows userspace to fine tune the d
From: Shashank Sharma
Color manager is an extention to i915 driver which provides display
tuning and color-correction properties to user space, via DRM propery
interface.Different Intel platforms support different color tuning capabilities
which can be exploited using this framework.
This patch
Before we process the final unbind on an object and move it to the
unbound list, it is semantically cleaner if there are no more active
references to the object. (An active reference would imply that it was
still being accessed by the GPU after it became inaccessible.) The
caveat is that all callsi
Due to the lazy retirement semantics, even though we have unbound an
object, it may still hold onto an active reference. So in te debug code,
play safe.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 31 ++-
1 file changed, 26 insertions(+), 5 d
Hi Daniel,
Due to 2014Q3 release testing circle this week, QA will do this test in next
week.
Thanks
--Sun, Yi
> -Original Message-
> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch]
> Sent: Friday, September 5, 2014 9:16 PM
> To: Sun, Yi
> Cc: intel-gfx@lists.freedesktop.org; Dani
Hi all,
Here is another release of Intel-gpu-tools 1.8.
This one came without any pre warning again and release was "time based" to
be on time for the Intel Linux Graphics stack validation that we are
starting today and that might be released by the end of this Quarter as
usual.
This is my last r
Need to reset the flip_received flag at the end of this block, indicate
that the flip interrupt will stop working.
+ if (dev_priv->rps.is_bdw_sw_turbo) {
+ del_timer_sync(&dev_priv->rps.sw_turbo.flip_timer);
+ cancel_work_sync(&dev_priv->rps.sw_turbo.work_max_fr
On Monday 08 Sep 2014 09:06:50 Chris Wilson wrote:
> On Sat, Sep 06, 2014 at 02:01:31PM +0100, Tom Pitcher wrote:
> > I've been attempting to solve a bug with i915 & switcheroo on many Macbook
> > Pros (some with nvidia discrete cards, others radeon), report here:
> >
> > https://bugs.freedesktop.
On Mon, 8 Sep 2014 18:28:20 +0200
Daniel Vetter wrote:
> This was lost in
>
> commit e11aa362308f5de467ce355a2a2471321b15a35c
> Author: Jesse Barnes
> Date: Wed Jun 18 09:52:55 2014 -0700
>
> drm/i915: use runtime irq suspend/resume in freeze/thaw
>
> which makes the second part of thi
On Mon, Sep 08, 2014 at 04:59:42PM +0300, Ville Syrjälä wrote:
> On Fri, Sep 05, 2014 at 05:04:45PM -0300, Gustavo Padovan wrote:
> > From: Gustavo Padovan
> >
> > This is the beginning of the work to prepare i915 for the upcoming
> > atomic modesetting API. Here we split the plane update fucntio
This was lost in
commit e11aa362308f5de467ce355a2a2471321b15a35c
Author: Jesse Barnes
Date: Wed Jun 18 09:52:55 2014 -0700
drm/i915: use runtime irq suspend/resume in freeze/thaw
which makes the second part of this commen a bit nonsense. Both were
originally added in
commit 15239099d7a7a
On Monday 08 September 2014 08:10 PM, Daniel Vetter wrote:
On Mon, Sep 08, 2014 at 05:14:23PM +0300, Ville Syrjälä wrote:
On Mon, Sep 08, 2014 at 05:02:43PM +0300, Ville Syrjälä wrote:
On Tue, Sep 09, 2014 at 07:14:16PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S
In chv, we have t
Somehow I've overlooked this when simplifying the irq reinit
scheme on gen4.5+ in
commit 78ad455fd229c6f6cc2f390ccbe0d8f1a62d55a9
Author: Daniel Vetter
Date: Thu May 22 22:18:21 2014 +0200
drm/i915: Improve irq handling after gpu resets
Since display interrups in general survive a gpu res
On Mon, 08 Sep 2014, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> The vblank waits in intel_tv_detect_type() are timing out for some
> reason. This is a regression caused removing seemingly useless vblank
> waits from the modeset seqeuence in:
>
> commit 56ef52cad5e37fca89638e4b
From: Ville Syrjälä
The vblank waits in intel_tv_detect_type() are timing out for some
reason. This is a regression caused removing seemingly useless vblank
waits from the modeset seqeuence in:
commit 56ef52cad5e37fca89638e4bad598a994ecc3d9f
Author: Ville Syrjälä
Date: Thu May 8 19:23:15 2
On Mon, Sep 08, 2014 at 05:14:23PM +0300, Ville Syrjälä wrote:
> On Mon, Sep 08, 2014 at 05:02:43PM +0300, Ville Syrjälä wrote:
> > On Tue, Sep 09, 2014 at 07:14:16PM +0530, deepa...@linux.intel.com wrote:
> > > From: Deepak S
> > >
> > > In chv, we have two power wells Render & Media. We need to
On Mon, Sep 08, 2014 at 05:02:43PM +0300, Ville Syrjälä wrote:
> On Tue, Sep 09, 2014 at 07:14:16PM +0530, deepa...@linux.intel.com wrote:
> > From: Deepak S
> >
> > In chv, we have two power wells Render & Media. We need to use
> > corresponsing forcewake count. If we dont follow this we are get
On Tue, Sep 09, 2014 at 07:14:16PM +0530, deepa...@linux.intel.com wrote:
> From: Deepak S
>
> In chv, we have two power wells Render & Media. We need to use
> corresponsing forcewake count. If we dont follow this we are getting
> error "*ERROR*: Timed out waiting for forcewake old ack to clear"
On Fri, Sep 05, 2014 at 05:04:45PM -0300, Gustavo Padovan wrote:
> From: Gustavo Padovan
>
> This is the beginning of the work to prepare i915 for the upcoming
> atomic modesetting API. Here we split the plane update fucntions in
> the check and commit states.
>
> v2: use struct intel_plane_stat
On Fri, Sep 05, 2014 at 05:04:45PM -0300, Gustavo Padovan wrote:
> From: Gustavo Padovan
>
> This is the beginning of the work to prepare i915 for the upcoming
> atomic modesetting API. Here we split the plane update fucntions in
> the check and commit states.
>
> v2: use struct intel_plane_stat
On Mon, 08 Sep 2014, Chris Wilson wrote:
> Running igt, I was encountering the invalid TLB bug on my 845g, despite
> that it was using the CS workaround. Examining the w/a buffer in the
> error state, showed that the copy from the user batch into the
> workaround itself was suffering from the inva
From: Deepak S
In chv, we have two power wells Render & Media. We need to use
corresponsing forcewake count. If we dont follow this we are getting
error "*ERROR*: Timed out waiting for forcewake old ack to clear" due to
multiple entry into __vlv_force_wake_get.
Signed-off-by: Deepak S
---
driv
Running igt, I was encountering the invalid TLB bug on my 845g, despite
that it was using the CS workaround. Examining the w/a buffer in the
error state, showed that the copy from the user batch into the
workaround itself was suffering from the invalid TLB bug (the first
cacheline was broken with t
On 8 September 2014 13:07, Daniel Vetter wrote:
> On Mon, Sep 08, 2014 at 12:12:21PM +0100, Thomas Wood wrote:
> > Include the generic_edid array inside igt_kms.c to avoid having to
> include
> > it separately in tests. This also means it can be included in the i-g-t
> kms
> > section of the docu
We want to enable/disable display IRQs only if global i915 IRQs are
enabled. To check the latter it's not enough to consult the DRM
dev->irq_enabled flag, since runtime PM can disable/enable IRQs
and it won't adjust this flag only the i915 specific
dev_priv->pm._irqs_disabled flag. Fix this by usin
On Mon, Sep 08, 2014 at 12:12:21PM +0100, Thomas Wood wrote:
> Include the generic_edid array inside igt_kms.c to avoid having to include
> it separately in tests. This also means it can be included in the i-g-t kms
> section of the documentation.
You can just include igt_edid.h from igt_kms.h and
Include the generic_edid array inside igt_kms.c to avoid having to include
it separately in tests. This also means it can be included in the i-g-t kms
section of the documentation.
Signed-off-by: Thomas Wood
---
docs/reference/intel-gpu-tools/Makefile.am | 3 ++-
docs/reference/int
On Mon, Sep 08, 2014 at 09:15:50AM +0100, Chris Wilson wrote:
> On Mon, Sep 08, 2014 at 10:03:51AM +0200, Daniel Vetter wrote:
> > On Sun, Sep 07, 2014 at 09:08:31AM +0100, Chris Wilson wrote:
> > > Running igt, I was encountering the invalid TLB bug on my 845g, despite
> > > that it was using the
On Mon, Sep 08, 2014 at 09:15:50AM +0100, Chris Wilson wrote:
> On Mon, Sep 08, 2014 at 10:03:51AM +0200, Daniel Vetter wrote:
> > On Sun, Sep 07, 2014 at 09:08:31AM +0100, Chris Wilson wrote:
> > > Running igt, I was encountering the invalid TLB bug on my 845g, despite
> > > that it was using the
On Wed, Aug 27, 2014 at 04:00:22PM -0700, Jesse Barnes wrote:
> On Wed, 27 Aug 2014 10:43:37 +0200
> Daniel Vetter wrote:
>
> > Now that vlv has runtime pm we kinda should check for that like on the
> > pch split platforms. Looks like this was simply lost in the vlv rpm
> > enabling.
> >
> > Cc:
On Mon, Sep 08, 2014 at 10:03:51AM +0200, Daniel Vetter wrote:
> On Sun, Sep 07, 2014 at 09:08:31AM +0100, Chris Wilson wrote:
> > Running igt, I was encountering the invalid TLB bug on my 845g, despite
> > that it was using the CS workaround. Examining the w/a buffer in the
> > error state, showed
On Sat, Sep 06, 2014 at 02:01:31PM +0100, Tom Pitcher wrote:
> I've been attempting to solve a bug with i915 & switcheroo on many Macbook
> Pros (some with nvidia discrete cards, others radeon), report here:
>
> https://bugs.freedesktop.org/show_bug.cgi?id=61115
>
> Basically, after switching to
On Sun, Sep 07, 2014 at 09:08:31AM +0100, Chris Wilson wrote:
> Running igt, I was encountering the invalid TLB bug on my 845g, despite
> that it was using the CS workaround. Examining the w/a buffer in the
> error state, showed that the copy from the user batch into the
> workaround itself was suf
Snapshot 2.99.916 (2014-09-08)
==
Quick update for MST in UXA - we need to hook up the RandR outputs for
dynamicaly added connectors.
Complete list of changes since 2.99.915
---
Chris Wilson (1):
2.99.916 snapshot
Dave Airlie
On Fri, Sep 05, 2014 at 05:53:23PM +0100, Michel Thierry wrote:
> With the new vma/ppgtt lifetime rules, the ppgtt (vm) could be removed
> after i915_vma_unbind.
>
> Use list_for_each_entry_safe() to prevent this use-after-free.
>
> Found with gem_persistent_relocs and gem_evict_everything igt te
On Mon, Sep 08, 2014 at 09:44:43AM +0200, Daniel Vetter wrote:
> On Fri, Sep 05, 2014 at 04:19:18PM +0300, Jani Nikula wrote:
>
> Slightly less thin commit message appreciated ...
It looks like this now:
commit 476e2ac36e9d00e513356d7ebc443c75a1dd3ede
Author: Jani Nikula
Date: Fri Sep 5 16:19
I've been attempting to solve a bug with i915 & switcheroo on many Macbook
Pros (some with nvidia discrete cards, others radeon), report here:
https://bugs.freedesktop.org/show_bug.cgi?id=61115
Basically, after switching to i915 using switcheroo the display isn't
connected. It was mentioned tha
On Mon, Sep 08, 2014 at 05:46:18PM +1000, Dave Airlie wrote:
> From: Dave Airlie
>
> I somehow lost this chunk in my mst patch I sent.
>
> Signed-off-by: Dave Airlie
And I didn't notice, since this is one of the major things you have to
do with delayed addition of outputs.
Thanks for the quic
On Fri, Sep 05, 2014 at 08:51:03AM -0700, Rodrigo Vivi wrote:
> I really didn't like this implementation because I'm using the global
> variable in the test case.
>
> So I think also providing a define igt_skip_function_on_dryrun() if
> (igt_dry_run) return 0 is more igt like.
>
> For psr I need
From: Dave Airlie
I somehow lost this chunk in my mst patch I sent.
Signed-off-by: Dave Airlie
---
src/uxa/intel_display.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/uxa/intel_display.c b/src/uxa/intel_display.c
index c5f0620..97af76d 100644
--- a/src/uxa/intel_display.c
+++
On Fri, Sep 05, 2014 at 04:19:18PM +0300, Jani Nikula wrote:
Slightly less thin commit message appreciated ...
> Signed-off-by: Jani Nikula
Queued for -next, thanks for the patch.
-Daniel
> ---
> drivers/gpu/drm/i915/intel_dp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff
On Fri, Sep 05, 2014 at 02:13:16PM +0100, Michel Thierry wrote:
> Use full PPGTT as the default option in gen7.
> Note that aliasing PPGTT is the default option for gen8 (see HAS_PPGTT).
>
> This may well come back to bite me later.
>
> Signed-off-by: Michel Thierry
Queued for -next, thanks for
Am 08.09.2014 09:39, schrieb Daniel Vetter:
On Fri, Sep 05, 2014 at 09:54:13PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
830 is very unhappy of the watermark value is too low (indicating a very
high watermark in fact, ie. memory fetch will occur with an almost full
FIFO).
On Fri, Sep 05, 2014 at 09:54:13PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> 830 is very unhappy of the watermark value is too low (indicating a very
> high watermark in fact, ie. memory fetch will occur with an almost full
> FIFO). Limit the watermark value to at leas
On Fri, Sep 05, 2014 at 09:52:42PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> The spec says:
> "For the correct operation of the muxed DVO pins (GDEVSELB/ I2Cdata,
> GIRDBY/I2CClk) and (GFRAMEB/DVI_Data, GTRDYB/DVI_Clk): Bit 31
> (DPLL VCO Enable) and Bit 30 (2X Clock E
On Fri, Sep 05, 2014 at 02:12:49PM -0700, Rodrigo Vivi wrote:
> As Paulo told the part 2 of his proposal is still missing and we will get
> the WARN of reading fbc register at fbc_enabled when on runtime_suspend...
>
> But I couldn't find the propper place to check for intel_crtc->active. This
> w
On Fri, Sep 05, 2014 at 12:35:18PM -0700, Rodrigo Vivi wrote:
> On Fri, Sep 5, 2014 at 11:28 AM, Paulo Zanoni wrote:
> > - The screen is disabled
>
> - We're runtime suspended
> >
>
> These are another error. Not caused by this patch.
> Why frontbuffer_flush is being called with screen disabled
Snapshot 2.99.915 (2014-09-08)
==
A significant change to UXA to enable MST and to keep it working on recent
kernels needs some soaking before a major release, and the usual
plethora of bugfixes. One other feature is the support for hardware
rotations on very recent kern
On Thu, 04 Sep 2014, Daniel Vetter wrote:
> On Thu, Sep 04, 2014 at 04:42:36PM +0300, Jani Nikula wrote:
>> On Thu, 04 Sep 2014, Daniel Vetter wrote:
>> > On Thu, Sep 04, 2014 at 02:12:10PM +0300, Jani Nikula wrote:
>> >> On Wed, 27 Aug 2014, Daniel Vetter wrote:
>> >> > A bunch of warnings fire
64 matches
Mail list logo
