Hi all,
New -testing cycle with cool stuff:
- basic code for execlist, which is the fancy new cmd submission on gen8. Still
disabled by default (Ben, Oscar Mateo, Thomas Daniel et al)
- remove the useless usage of console_lock for I915_FBDEV=n (Chris)
- clean up relations between ctx and ppgtt
-
On Fri, Aug 22, 2014 at 3:38 PM, Chris Wilson wrote:
> On Fri, Aug 22, 2014 at 03:30:12PM +0200, Daniel Vetter wrote:
>> On Fri, Aug 22, 2014 at 9:03 AM, Chris Wilson
>> wrote:
>> >> > > If a GPU
>> >> > > client uses only prelocations, the relocation process can be entirely
>> >> > > skipped. T
On Fri, Aug 22, 2014 at 3:38 PM, Chris Wilson wrote:
> On Fri, Aug 22, 2014 at 03:30:12PM +0200, Daniel Vetter wrote:
>> On Fri, Aug 22, 2014 at 9:03 AM, Chris Wilson
>> wrote:
>> >> > > If a GPU
>> >> > > client uses only prelocations, the relocation process can be entirely
>> >> > > skipped. T
Some of the workarounds are lost followed by a gpu reset, suspend/resume;
this patch adds a test which compares register state before and after
the test scenario.
This test currently verifies only bdw workarounds.
v2: address patch cleanup comments (ThomasW)
Add binary to ignore list and use igt
For BDW workarounds are currently initialized in init_clock_gating() but
they are lost during reset, suspend/resume etc; this patch moves the WAs
that are part of register state context to render ring init fn otherwise
default context ends up with incorrect values as they don't get initialized
unti
The workarounds that are applied are exported to a debugfs file;
this is used to verify their state after the test case (reset or
suspend/resume etc). This patch is only required to support i-g-t.
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_debugfs.c | 40 +
Workarounds for BDW are applied using LRIs during render ring initialization.
Only those WA registers that are part of register state are initialized
in this fn, remaining are still in its current place init_clock_gating() which
are not affected by a gpu reset. I can send another patch where they c
On Fri, Aug 22, 2014 at 08:15:28AM -0400, Alex Deucher wrote:
> On Thu, Aug 21, 2014 at 11:12 PM, Ben Widawsky
> wrote:
> > This was a quick proof of concept to show the new API for prelocating
> > buffers.
> >
>
> What are prelocated buffers?
http://lists.freedesktop.org/archives/mesa-dev/2014-
I'll check it out. I haven't heard any complaint about this before, but it may
be one of those things that started back on i745 and never got documented.
-Original Message-
From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
Sent: Friday, August 22, 2014 6:07 AM
To: Taylor, Clinton
From: Ville Syrjälä
The power sequencer loses its state when the disp2d power well is down.
Clear the dev_priv->pps_pipe tracking so that the power sequencer state
gets reinitialized the next time it's needed.
v2: Fix the pps_mutex vs. power_domain mutex deadlock by taking power
domain refer
Rather than describing an object as either "snooped or LLC", we can do
better as we should know what machine we are running on!
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.h | 4 +++-
drivers/gpu/drm/i915/i915_gpu_error.c |
On Fri, Aug 22, 2014 at 03:30:12PM +0200, Daniel Vetter wrote:
> On Fri, Aug 22, 2014 at 9:03 AM, Chris Wilson
> wrote:
> >> > > If a GPU
> >> > > client uses only prelocations, the relocation process can be entirely
> >> > > skipped. This sounds like a big win initially,
> >> >
> >> > Close to z
On Fri, Aug 22, 2014 at 9:03 AM, Chris Wilson wrote:
>> > > If a GPU
>> > > client uses only prelocations, the relocation process can be entirely
>> > > skipped. This sounds like a big win initially,
>> >
>> > Close to zero if the client uses existing interfaces.
>> > -Chris
>>
>> Chris,
>>
>> I d
+Art
On Thu, 21 Aug 2014, Clint Taylor wrote:
> There is also a need to add this delay when turning off the PWM enable
> bit through intel_panel_disable_backlight(). If the PWM enable bit is
> turned off while the PWM signal is high then the signal remains high. If
> the bit is turned off whe
On Fri, Aug 22, 2014 at 03:06:35PM +0300, Jani Nikula wrote:
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 5
My Toshiba A50 with graphics adapter described by
00:02.0 VGA compatible controller [0300]: Intel Corporation 4th Gen Core
Processor Integrated Graphics Controller [8086:0416] (rev 06) gets the following
warning on 3.17-rc1:
[ 1271.563533] [ cut here ]
[ 1271.563568] WARN
On Thu, Aug 21, 2014 at 11:12 PM, Ben Widawsky
wrote:
> This was a quick proof of concept to show the new API for prelocating
> buffers.
>
What are prelocated buffers?
Alex
> It needs way more testing, to not ifdef the no-relocs, and to do a
> libdrm ABI dep bump.
> ---
> src/mesa/drivers/dri/
On 22/08/2014 12:06, Mika Kuoppala wrote:
Ville Syrjälä writes:
On Wed, Aug 20, 2014 at 03:19:17PM +0100, Arun Siluvery wrote:
Workarounds for bdw are currently applied in init_clock_gating() but they
are lost following a gpu reset. Some of the WA registers are part of register
state context
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 51b4cd29f932..83eabd758ed9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+
Fix assert_panel_unlocked for vlv/chv, and improve it a bit for
non-LVDS. Also don't pretend it works for DDI. There's still work to do
to get this right for eDP on PCH platforms, but this is a start.
v2: WARN_ON(HAS_DDI)
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/dr
Ville Syrjälä writes:
> On Wed, Aug 20, 2014 at 03:19:17PM +0100, Arun Siluvery wrote:
>> Workarounds for bdw are currently applied in init_clock_gating() but they
>> are lost following a gpu reset. Some of the WA registers are part of register
>> state context and they are restored with every co
> On Fri, 22 Aug 2014, Bertrik Sikken wrote:
>> On 19-8-2014 3:29, Jani Nikula wrote:
>>> On Tue, 19 Aug 2014, Bertrik Sikken wrote:
> On Sun, 17 Aug 2014, Bertrik Sikken wrote:
>> On 15-8-2014 3:43, Jani Nikula wrote:
>>> On Thu, 14 Aug 2014, Bertrik Sikken wrote:
>>
A
On Thu, Aug 21, 2014 at 10:23:43AM -0700, Clint Taylor wrote:
> On 08/20/2014 04:23 AM, Ville Syrjälä wrote:
> > On Mon, Aug 18, 2014 at 01:48:35PM -0700, clinton.a.tay...@intel.com wrote:
> >> From: Clint Taylor
> >>
> >> Backlight on delay uses PWM enable time to seperate PWM to
> >> backlight e
From: Sonika Jindal
Primary planes support 180 degree rotation. Expose the feature
through rotation drm property.
v2: Calculating linear/tiled offsets based on pipe source width and
height. Added 180 degree rotation support in ironlake_update_plane.
v3: Checking if CRTC is active before issuein
On 8/22/2014 1:44 PM, Ville Syrjälä wrote:
On Fri, Aug 22, 2014 at 09:29:56AM +0530, Jindal, Sonika wrote:
On 8/21/2014 7:07 PM, Ville Syrjälä wrote:
On Thu, Aug 21, 2014 at 05:14:35PM +0530, Jindal, Sonika wrote:
On 8/21/2014 2:03 PM, Ville Syrjälä wrote:
On Thu, Aug 21, 2014 at 11:45:
On Fri, Aug 22, 2014 at 09:29:56AM +0530, Jindal, Sonika wrote:
>
>
> On 8/21/2014 7:07 PM, Ville Syrjälä wrote:
> > On Thu, Aug 21, 2014 at 05:14:35PM +0530, Jindal, Sonika wrote:
> >>
> >>
> >> On 8/21/2014 2:03 PM, Ville Syrjälä wrote:
> >>> On Thu, Aug 21, 2014 at 11:45:41AM +0530, sonika.jin
On Thu, Aug 21, 2014 at 12:01:07PM -0300, Paulo Zanoni wrote:
> 2014-08-21 11:56 GMT-03:00 Ville Syrjälä :
> > On Thu, Aug 21, 2014 at 03:06:26PM +0300, Jani Nikula wrote:
> >> Fix assert_panel_unlocked for vlv/chv, and improve it a bit for
> >> non-LVDS. Also don't pretend it works for DDI. There'
On Thu, Aug 21, 2014 at 11:59:04PM -0700, Kenneth Graunke wrote:
> On Friday, August 22, 2014 07:30:37 AM Chris Wilson wrote:
> > On Thu, Aug 21, 2014 at 08:11:23PM -0700, Ben Widawsky wrote:
> > > The primary goal of these patches is to introduce what I've started
> > > calling, "prelocations" on
From: Sonika Jindal
Primary planes support 180 degree rotation. Expose the feature
through rotation drm property.
v2: Calculating linear/tiled offsets based on pipe source width and
height. Added 180 degree rotation support in ironlake_update_plane.
v3: Checking if CRTC is active before issuein
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