On Mon, May 26, 2014 at 03:34:43PM +0530, Vandana Kannan wrote:
[...]
> @@ -1344,6 +1350,27 @@ int drm_mode_create_scaling_mode_property(struct
> drm_device *dev)
> EXPORT_SYMBOL(drm_mode_create_scaling_mode_property);
>
> /**
> + * drm_mode_create_aspect_ratio_property - create aspect ratio p
On Mon, May 26, 2014 at 03:37:42PM +0530, Vandana Kannan wrote:
> In case user has specified an input for aspect ratio through the property,
> then the user space value for PAR would take preference over the value from
> CEA mode list.
>
> v2: Thierry's review comments.
> - Modified the comm
Hey Gideon,
[CCing intel-gfx mailing list]
On Wed, 4 Jun 2014 20:22:13 +0530 Gideon D'souza wrote:
> Thank you so much for your reply.
>
> I did manage to move a bit forward with my issue since my email here.
> When the system kinda stuck, I realized I could press Ctrl + Alt + F2
> and I had acc
On Wed, 2014-05-28 at 15:27 +0530, sourab gupta wrote:
> On Mon, 2014-04-14 at 09:45 +, Gupta, Sourab wrote:
> > From: Akash Goel
> >
> > This workaround is needed on VLV for the HW context feature.
> > It is used after adding the mi_set_context command in ring buffer
> > for Hw context switc
From: Dave Airlie
---
drivers/gpu/drm/i915/intel_dp_mst.c | 10 ++
drivers/gpu/drm/i915/intel_fbdev.c | 2 +-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
b/drivers/gpu/drm/i915/intel_dp_mst.c
index a7db741..ddac87f 100644
--- a/dr
From: Dave Airlie
This is required to get fbcon probing to work on new connectors,
callers should acquire the mode config lock before calling these.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/drm_fb_helper.c | 53 +
include/drm/drm_fb_helper.h |
From: Dave Airlie
This property will be used by the MST code to provide userspace
with a path to parse so it can recognise connectors around hotplugs.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/drm_crtc.c | 26 ++
include/drm/drm_crtc.h | 5 +
2 files chang
From: Dave Airlie
this is just prep work for mst support.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/intel_ddi.c | 18 +-
drivers/gpu/drm/i915/intel_drv.h | 1 +
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers
From: Dave Airlie
These are just from the Haswell spec.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/i915_reg.h | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5122254..60cfbb6 100644
From: Dave Airlie
DP MST will need connectors that aren't connected to specific
encoders, add some checks in advance to avoid oopses.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/i915_debugfs.c | 16 +---
drivers/gpu/drm/i915/i915_irq.c | 4
drivers/gpu/drm/i915/
From: Dave Airlie
This can be called to update things after dynamic connectors/encoders
are created/deleted.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/drm_crtc.c | 9 +
include/drm/drm_crtc.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/drm_crtc.c b/d
From: Dave Airlie
use the mst helper code to dump the topology in debugfs.
v0.2: drop is_mst check - as we want to dump other info
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/i915_debugfs.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i9
Another round of the MST support for i915 haswell.
This relies on the aux locking and i915 irq rework patches I posted
already.
this also splits out some more i915 rework into earlier patches.
The main fix is not talking to devices if HPD isn't asserted, at
least on the dock I have it will reply
From: Dave Airlie
for MST I need to reuse these, so split them out early.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/intel_ddi.c | 27 ---
drivers/gpu/drm/i915/intel_display.c | 31 ++-
2 files changed, 34 insertions(+), 24 delet
Move rc6_residency_check to subtest, add new rc6_residency_counter subtest
for pm_rc6_residency IGT case.
Test results run on platforms show as below:
On HSW
---
[root@x-hswu opt]# ./pm_rc6_residency
IGT-Version: 1.6-g35b31df (x86_64) (Linux:
3.15.0-rc3_drm-int
I just noticed and verified this patch fixes this bug:
https://bugs.freedesktop.org/show_bug.cgi?id=79621
On Wed, Jun 4, 2014 at 5:16 PM, Ben Widawsky wrote:
> On Wed, Jun 04, 2014 at 05:09:30PM -0700, Rodrigo Vivi wrote:
> > BDW uses IVB cursor offsets.
> >
> > Whithout this patch it is not p
On Wed, Jun 04, 2014 at 05:09:30PM -0700, Rodrigo Vivi wrote:
> BDW uses IVB cursor offsets.
>
> Whithout this patch it is not possible to use multiple outputs with cursor
> on BDW.
> The cursor gets completely crazy because update position uses the wrong
> cursor register for the second pipe.
>
BDW uses IVB cursor offsets.
Whithout this patch it is not possible to use multiple outputs with cursor
on BDW.
The cursor gets completely crazy because update position uses the wrong
cursor register for the second pipe.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.c | 2 ++
1
Hi folks,
when switching resolutions with xrandr (or otherwise) on the 830MG
chipset, I usually get a "Pipe A underrun" error,
sometimes resulting in a completely black screen. To my understanding,
the internal screen is connected to pipe B on
this laptop, thus I wonder why I get the error. Thu
From: Clint Taylor
Remove OUI read function from the lower half interrupt handler. Upon
closing the eDP panel lid an HPD interrupt is generated. The lower half
handler calls intel_dp_probe_oui() as part of intel_dp_detect().
intel_dp_probe_oui() enables eDP VDD and subsequently disables eDP VDD
c
This allows the system to enter the lowest power mode during system freeze.
v2: delete force wake timer at suspend (Imre)
v3: add GT work suspend function (Imre)
v4: use uncore forcewake reset (Daniel)
Signed-off-by: Kristen Carlson Accardi
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/
On Fri, 2014-05-30 at 11:48 -0700, Jesse Barnes wrote:
> From: Kristen Carlson Accardi
>
> This matches the runtime suspend paths and allows the system to enter
> the lowest power mode at freeze time.
>
> v2: move disable_pc8 call to thaw_early (Imre)
> move enable_pc8 to freeze_late (Imre/J
2014-06-04 15:47 GMT-03:00 Rodrigo Vivi :
> Signed-off-by: Rodrigo Vivi
Yeah, this seems to make -nightly compile.
Reviewed-by: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/intel_fbdev.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_fbdev.c
This allows the system to enter the lowest power mode during system freeze.
v2: delete force wake timer at suspend (Imre)
v3: add GT work suspend function (Imre)
Signed-off-by: Kristen Carlson Accardi
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.c | 4 ++--
drivers/gpu/drm/i
On Wed, Jun 04, 2014 at 03:06:18PM +0100, michel.thie...@intel.com wrote:
> From: Michel Thierry
>
> HDC_CHICKEN0 bit 14 (Fence Destination To SLM Disable) must be
> programmed by software to 1h (Disable) to work around a LSLM unit issue.
>
> WaDisableFenceDestinationToSLM is only needed for BDW
On Wed, May 28, 2014 at 5:57 AM, Daniel Vetter wrote:
> On Tue, May 27, 2014 at 04:50:14PM -0700, Rodrigo Vivi wrote:
> > Some registers set during setup might not be persistent after
> suspend/resume.
> > This was causing bugs for some people that was unable to get PSR entry
> state
> > after re
This is breaking -nightly build!
On Wed, Jun 4, 2014 at 11:47 AM, Rodrigo Vivi
wrote:
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_fbdev.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_fbdev.c
> b/drivers/gpu/drm/i915/i
2014-05-22 11:48 GMT-03:00 :
> From: Ville Syrjälä
>
> If we mark the LP1+ watermarks as disabled every time sprite scaling
> is enabled, we end doing pointless work applying watermarks even though
> nothing has changed. This is an artifact of the way
> dev_priv->wm.lp_disabled affects the operat
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_fbdev.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c
b/drivers/gpu/drm/i915/intel_fbdev.c
index e768207..b5448d8 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/
2014-05-22 11:48 GMT-03:00 :
> From: Ville Syrjälä
>
> ILK and IVB don't like switching between sprite only and primary only
> configurations when LP1+ watermarks have been enabled in the recent
> past. Like WaCxSRDisabledForSpriteScaling we can avoid the flash
> by disabling LP1+ watermarks for
2014-05-22 11:48 GMT-03:00 :
> From: Ville Syrjälä
>
> When the primary plane is disabled, pick the 5/6 DDB split to give the
> sprite as much FIFO space as possible.
>
> The normal heuristic of just looking at the highest valid WM level won't
> necessarily pick the optimal split since both split
2014-05-22 11:48 GMT-03:00 :
> From: Ville Syrjälä
>
> Currently ilk_disable_lp_wm() just disabled LP1+ watermarks directly.
> However there's nothing preventing someone else from re-enabling them
> immediately. To make sure sure LP1+ watermarks stay disabled for the
> intended period, keep track
2014-05-22 11:48 GMT-03:00 :
> From: Ville Syrjälä
>
> When we switch between one active pipe and multiple active pipes, the
> display FIFO gets repartitioned. Disable the LP1+ waterwarks while that
> is happening to make sure we don't get any glitches on other active
> pipes while doing a modese
On Wed, Jun 4, 2014 at 6:58 PM, Sedat Dilek wrote:
> On Wed, Jun 4, 2014 at 6:52 PM, Chris Wilson wrote:
>> On Wed, Jun 04, 2014 at 06:37:44PM +0200, Sedat Dilek wrote:
>>> > DRI2 or DRI3 running here?
>>> >
>>>
>>> I did some more testing and played with UXA/SNA for intel-ddx.
>>>
>>> $ egrep -i
2014-05-22 11:48 GMT-03:00 :
> From: Ville Syrjälä
>
> Pull the code to locate the other active crtc out from
> haswell_mode_set_planes_workaround() into a separate function.
> This will have another use later.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Paulo Zanoni
> ---
> drivers/gpu/dr
On Wed, Jun 4, 2014 at 6:52 PM, Chris Wilson wrote:
> On Wed, Jun 04, 2014 at 06:37:44PM +0200, Sedat Dilek wrote:
>> > DRI2 or DRI3 running here?
>> >
>>
>> I did some more testing and played with UXA/SNA for intel-ddx.
>>
>> $ egrep -i 'dri2|dri3|present|sna|uxa' Xorg.0.log_UXA
>> [ 8471.151] (
On Wed, Jun 04, 2014 at 06:37:44PM +0200, Sedat Dilek wrote:
> > DRI2 or DRI3 running here?
> >
>
> I did some more testing and played with UXA/SNA for intel-ddx.
>
> $ egrep -i 'dri2|dri3|present|sna|uxa' Xorg.0.log_UXA
> [ 8471.151] (II) intel(0): DRI2: Enabled
> [ 8471.151] (II) intel(0): DR
On Tue, Jun 03, 2014 at 05:51:01PM -0300, Paulo Zanoni wrote:
> 2014-05-22 11:48 GMT-03:00 :
> > From: Ville Syrjälä
> >
> > We need to perform watermark programming before and after changing the
> > plane configuration. Add two new vfuncs to do that. The pre phase is
> > supposed to switch over
On Wed, Jun 04, 2014 at 09:32:54AM +0100, tim.g...@intel.com wrote:
> From: Tim Gore
>
> In Makefile.sources, kms_fence_pin_leak was in the "Multi" test list,
> ie tests with subtests, whereas it is actually simple/single test.
> This was confusing the Android script for enumerating tests.
>
> S
On Wed, Jun 04, 2014 at 03:56:19PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> The EBUSY checking is very fragile currently in case there's any kind
> extra delay in the test loop. At least the flip-vs-rmfb fails reliably
> on my IVB.
>
> So to make the test less fragil
On Wed, Jun 04, 2014 at 11:01:01AM -0300, Paulo Zanoni wrote:
> > This function is only called at init/resume. It populates the software
> > state with something that matches the current hardware state. I guess
> > a comment explaning the purpose of the function is the best we can do
> > here, or d
On Wed, Jun 4, 2014 at 2:11 AM, Jani Nikula wrote:
> On Wed, 04 Jun 2014, Stéphane Marchesin wrote:
>> On Tue, Jun 3, 2014 at 1:26 PM, Daniel Vetter wrote:
>>> On Tue, Jun 3, 2014 at 6:40 PM, Stéphane Marchesin
>>> wrote:
On Tue, Apr 29, 2014 at 1:30 PM, Jani Nikula wrote:
> Historic
Hi Chris,
On 3 June 2014 16:12, Chris Wilson wrote:
> On Mon, Jun 02, 2014 at 02:18:14PM +0100, Sam Jansen wrote:
> >Hello intel-gfx,
> >I'm working on an application using VA-API for H264 encode+decode, and
> >JPEG decode on an Atom E3815. Unfortunately we've hit what I believe
> is
From: Michel Thierry
HDC_CHICKEN0 bit 14 (Fence Destination To SLM Disable) must be
programmed by software to 1h (Disable) to work around a LSLM unit issue.
WaDisableFenceDestinationToSLM is only needed for BDW E,F step.
Issue: APDEV-3096
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915
2014-06-03 16:32 GMT-03:00 Ville Syrjälä :
> On Tue, Jun 03, 2014 at 03:50:12PM -0300, Paulo Zanoni wrote:
>> 2014-05-22 11:48 GMT-03:00 :
>> > From: Ville Syrjälä
>> >
>> > Add a mechanism by which you can queue up watermark update to happen
>> > after the vblank counter has reached a certain va
Hi,
I took [1] as a base to test DRI3 on Ubuntu/precise AMD64.
Unfortunately, the packages from this repo have no DRI3 support.
So, I packaged some missing stuff, built mesa-10.1.4 and intel-ddx
from Git manually.
In the end I got somehow running a DRI3 system here.
$ grep -A2 intel_drv /var/lo
2014-05-22 11:48 GMT-03:00 :
> From: Ville Syrjälä
>
> After we've disabled the planes, it seems like a good idea wait for
> the vblank driven watermark updates to finish before we turn off the
> vblank interrupts and eventually the entire pipe.
Can you please elaborate more on why it is a "good
Hi
On Wed, Jun 4, 2014 at 2:20 PM, Jani Nikula wrote:
> On Wed, 04 Jun 2014, David Herrmann wrote:
>> You rely on compiler-optimizations here. "dummy_con" is not available
>> if !CONFIG_DUMMY_CONSOLE, but you use it. This causes linker-failure
>> if dead-code elimination is not done (-O0).
>
> N
From: Ville Syrjälä
The EBUSY checking is very fragile currently in case there's any kind
extra delay in the test loop. At least the flip-vs-rmfb fails reliably
on my IVB.
So to make the test less fragile remove the EBUSY check from all the
current flip tests, and instead add a specific busy-fli
On Tue, 03 Jun 2014, clinton.a.tay...@intel.com wrote:
> From: Clint Taylor
>
> The panel power sequencer on vlv doesn't appear to accept changes to its
> T12 power down duration during warm reboots. This change forces a delay
> for warm reboots to the T12 panel timing as defined in the VBT table
On Wed, 04 Jun 2014, David Herrmann wrote:
> Hi
>
> On Wed, Jun 4, 2014 at 12:57 AM, Daniel Vetter wrote:
>> From: Chris Wilson
>>
>> Touching the VGA resources on an IVB EFI machine causes hard hangs when
>> we then kick out the efifb. Ouch.
>>
>> Apparently this also prevents unclaimed registe
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
Matt Roper
Sent: Friday, May 23, 2014 2:30 AM
To: dri-de...@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 6/6] drm/i915: Switch to unified plane cursor
Hi
On Wed, Jun 4, 2014 at 12:57 AM, Daniel Vetter wrote:
> From: Chris Wilson
>
> Touching the VGA resources on an IVB EFI machine causes hard hangs when
> we then kick out the efifb. Ouch.
>
> Apparently this also prevents unclaimed register errors on hsw and
> hard machine hangs on my i855gm w
On Wed, 04 Jun 2014, Stéphane Marchesin wrote:
> On Tue, Jun 3, 2014 at 1:26 PM, Daniel Vetter wrote:
>> On Tue, Jun 3, 2014 at 6:40 PM, Stéphane Marchesin
>> wrote:
>>> On Tue, Apr 29, 2014 at 1:30 PM, Jani Nikula wrote:
Historically we've exposed the full backlight PWM duty cycle range
From: Tim Gore
In Makefile.sources, kms_fence_pin_leak was in the "Multi" test list,
ie tests with subtests, whereas it is actually simple/single test.
This was confusing the Android script for enumerating tests.
Signed-off-by: Tim Gore
---
tests/Makefile.sources | 2 +-
1 file changed, 1 inse
On Tue, Jun 3, 2014 at 1:26 PM, Daniel Vetter wrote:
> On Tue, Jun 3, 2014 at 6:40 PM, Stéphane Marchesin
> wrote:
>> On Tue, Apr 29, 2014 at 1:30 PM, Jani Nikula wrote:
>>> Historically we've exposed the full backlight PWM duty cycle range to
>>> the userspace, in the name of "mechanism, not p
On Wed, 04 Jun 2014, Ben Widawsky wrote:
> On Tue, Jun 03, 2014 at 02:52:30PM -0700, Kenneth Graunke wrote:
>> rendercopy was failing to emit 3DSTATE_WM_DEPTH_STENCIL, which is a new
>> packet on Broadwell. Mesa emits this packet.
>>
>> This appears to fix various tests on a fresh boot, when Mes
57 matches
Mail list logo
