This also appears to be true (but not documented as so) for gen4 and
gen5. To generalise we force it into the low mappable region for all
non-LLC platforms. If we locate the HWS at the top of the GTT the
machine will hard hang during boot (fails on pnv, gm45, ilk and byt,
but works on snb, ivb, hsw
On Sun, May 18, 2014 at 11:27:00AM +0530, Akash Goel wrote:
> On Wed, 2014-05-14 at 10:14 +0200, Daniel Vetter wrote:
> > On Tue, May 13, 2014 at 03:43:12PM -0700, Jesse Barnes wrote:
> > > On Wed, 14 May 2014 00:30:34 +0200
> > > Daniel Vetter wrote:
> > >
> > > > On Tue, May 13, 2014 at 03:05:2
On Sun, May 18, 2014 at 09:08:40PM +0200, Thomas Meyer wrote:
> Am Montag, den 12.05.2014, 07:33 +0100 schrieb Chris Wilson:
> > On Sun, May 11, 2014 at 07:40:57PM +0200, Daniel Vetter wrote:
> > > On Sun, May 11, 2014 at 11:02 AM, Dave Airlie wrote:
> > > > On 11 May 2014 18:28, Thomas Meyer wro
Am Montag, den 12.05.2014, 07:33 +0100 schrieb Chris Wilson:
> On Sun, May 11, 2014 at 07:40:57PM +0200, Daniel Vetter wrote:
> > On Sun, May 11, 2014 at 11:02 AM, Dave Airlie wrote:
> > > On 11 May 2014 18:28, Thomas Meyer wrote:
> > >> Hi,
> > >>
> > >> 3.14.3 works as expected.
> > >> 3.15-rc5
On 05/15 12:21, Matt Roper wrote:
> Intel hardware allows the primary plane to be disabled independently of
> the CRTC. Provide custom primary plane handling to allow this.
>
> v7:
> - Clip primary plane to invisible when crtc is disabled since
>intel_crtc->config.pipe_src_{w,h} may be garba
