Greg, ping? Can we go with this?
On Mon, 28 Apr 2014, Daniel Vetter wrote:
> On Mon, Apr 28, 2014 at 01:10:07PM +0300, Jani Nikula wrote:
>> This reverts the bisected regressing
>>
>> commit bc0bb9fd1c7810407ab810d204bbaecb255fddde
>> Author: Jani Nikula
>> Date: Thu Nov 14 12:14:29 2013 +02
On Mon, 05 May 2014, Mike Psarras wrote:
> Hi. I am not sure if I should send this to you but I was asked to send
> the below bug to the maintainers list. Could you please have a look
> and let me know? In case I should forward the email to someone else,
> please let me know.
Please file a new b
On Mon, May 05, 2014 at 02:50:27PM -0700, Daisy Sun wrote:
> RP frequency request is affected by 2 modules: normal turbo
> algorithm and RPS boost algorithm. By adding RPS boost algorithm
> to the mix, the final frequency becomes relatively unpredictable.
> Add a switch to enable/disable RPS boost
On Tue, Apr 22, 2014 at 08:19:43PM +0300, Mika Kuoppala wrote:
> HW guys say that it is not a cool idea to let device
> go into rc6 without proper 3d pipeline state.
>
> For each new uninitialized context, generate a
> valid null render state to be run on context
> creation.
>
> This patch introd
RP frequency request is affected by 2 modules: normal turbo
algorithm and RPS boost algorithm. By adding RPS boost algorithm
to the mix, the final frequency becomes relatively unpredictable.
Add a switch to enable/disable RPS boost functionality. When
disabled, RP frequency will follow the normal t
On Mon, May 05, 2014 at 11:49:12AM -0700, Ben Widawsky wrote:
> On Mon, May 05, 2014 at 09:07:33AM +0100, Chris Wilson wrote:
> > During the review of
> >
> > commit 1f70999f9052f5a1b0ce1a55aff3808f2ec9fe42
> > Author: Chris Wilson
> > Date: Mon Jan 27 22:43:07 2014 +
> >
> > drm/i915:
On Mon, May 05, 2014 at 09:07:33AM +0100, Chris Wilson wrote:
> During the review of
>
> commit 1f70999f9052f5a1b0ce1a55aff3808f2ec9fe42
> Author: Chris Wilson
> Date: Mon Jan 27 22:43:07 2014 +
>
> drm/i915: Prevent recursion by retiring requests when the ring is full
>
> Ville raise
From: Sagar Kamble
This test will set various values for drm properties exposed by planes
and check for functional accuracy in some cases using CRC check.
Currently this test is enabled for "const-alpha" drm property.
Cc: daniel.vet...@ffwll.ch
Cc: jani.nik...@linux.intel.com
Cc: ville.syrj...@l
From: Sagar Kamble
Cc: rdun...@infradead.org
Cc: alexander.deuc...@amd.com
Cc: airl...@redhat.com
Cc: laurent.pinch...@ideasonboard.com
Cc: dh.herrm...@gmail.com
Cc: daniel.vet...@ffwll.ch
Cc: jani.nik...@linux.intel.com
Cc: ville.syrj...@linux.intel.com
Cc: indranil.mukher...@intel.com
Cc: shash
From: Sagar Kamble
Cc: daniel.vet...@ffwll.ch
Cc: jani.nik...@linux.intel.com
Cc: ville.syrj...@linux.intel.com
Cc: indranil.mukher...@intel.com
Cc: shashidhar.hirem...@intel.com
Cc: vandita.kulka...@intel.com
Cc: vijay.a.purushotha...@intel.com
Cc: ankitprasad.r.sha...@intel.com
Signed-off-by: S
From: Sagar Kamble
Testcase: kms_plane_props
Cc: daniel.vet...@ffwll.ch
Cc: jani.nik...@linux.intel.com
Cc: ville.syrj...@linux.intel.com
Cc: indranil.mukher...@intel.com
Cc: shashidhar.hirem...@intel.com
Cc: vandita.kulka...@intel.com
Cc: vijay.a.purushotha...@intel.com
Cc: ankitprasad.r.sha...@
From: Sagar Kamble
This patch series introduces drm property for plane level alpha.
These patches are based on following patches which are already under
review/reviewed:
Documentation: drm: describing drm properties exposed by various drivers
Propagate the error from intel_update_plane() up thr
On Fri, May 02, 2014 at 11:29:16AM +0300, Ville Syrjälä wrote:
> On Thu, May 01, 2014 at 01:55:23PM +, Barbalho, Rafael wrote:
> > > -Original Message-
> > > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
> > > Of ville.syrj...@linux.intel.com
> > > Sent: Wed
On Mon, May 05, 2014 at 05:13:18PM +0530, akash.g...@intel.com wrote:
> From: Akash Goel
>
> There is a use case, when user space (display compositor) tries
> to directly flip a fb (without any prior rendering) on primary
> plane. So the backing pages of the object are allocated at page
> flip ti
On Thu, May 01, 2014 at 09:04:50AM +0100, Chris Wilson wrote:
> On Mon, Apr 28, 2014 at 05:18:28PM -0700, Ben Widawsky wrote:
> > All the rest of the code to enable this is in my branch. Without my
> > branch, hitting > 32b offsets is impossible. The code has always
> > "supported" 64b, but it's ne
On Thu, May 01, 2014 at 10:18:52AM +, Barbalho, Rafael wrote:
> > -Original Message-
> > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
> > Of Chris Wilson
> > Sent: Thursday, May 01, 2014 9:13 AM
> > To: Widawsky, Benjamin
> > Cc: Intel GFX
> > Subject: Re:
On Mon, 2014-05-05 at 15:44 +0300, Ville Syrjälä wrote:
> On Wed, Apr 30, 2014 at 09:53:08PM +0300, Imre Deak wrote:
> > On Wed, 2014-04-30 at 21:05 +0300, Ville Syrjälä wrote:
> > > On Tue, Apr 15, 2014 at 04:39:45PM +0300, Imre Deak wrote:
> > > > Atm, none of the RPM callbacks can fail, but the
On Mon, 2014-05-05 at 09:17 +0100, Chris Wilson wrote:
> On Mon, May 05, 2014 at 09:55:29AM +0530, akash.g...@intel.com wrote:
> > From: Akash Goel
> >
> > This patch could help to reduce the time, 'struct_mutex' is kept
> > locked during either the exec-buffer path or Page fault
> > handling pat
On Mon, 2014-05-05 at 13:39 +0100, Chris Wilson wrote:
> On Mon, May 05, 2014 at 06:03:17PM +0530, Akash Goel wrote:
> > On Mon, 2014-05-05 at 12:47 +0100, Chris Wilson wrote:
> > > On Mon, May 05, 2014 at 05:13:18PM +0530, akash.g...@intel.com wrote:
> > > > From: Akash Goel
> > > >
> > > > Ther
From: Deepak S
Streamline the CHV forcewake functions just like was done for VLV.
This will also fix a bug in accessing the common well registers,
where we'd end up trying to wake up the wells too many times
since we'd call force_wake_get/put twice per register access, with
FORCEFAKE_ALL both ti
From: Ville Syrjälä
CHV uses the gen8 shadow register mechanism so we shouldn't be
checking the GT FIFO status.
This effectively removes the posting read, so add an explicit
posting read using FORCEWAKE_ACK_VLV (which is what use in
vlv_forcewake_reset()).
Reviewed-by: Mika Kuoppala
Signed-off
From: Deepak S
v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)
v3: Mass rename of the dev_priv->rps variables in upstream.
v4: Rebase against latest code. (Deepak)
Signed-off-by: Deepak S
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gp
From: Deepak S
Signed-off-by: Deepak S
[vsyrjala: Fix merge fubmle where the code ended up in
g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]
Signed-off-by: Ville Syrjälä
Acked-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_pm.c | 11 +++
1 file changed, 11 inse
From: Ville Syrjälä
Skip __gen6_gt_wait_for_thread_c0() on CHV.
Reviewed-by: Mika Kuoppala
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_uncore.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/i
From: Deepak S
On CHV, All the freq request should be even. So, we need to make sure we
request the opcode accordingly.
Signed-off-by: Deepak S
Reviewed-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_irq.c | 9 +++--
drivers/gpu/drm/i915/i915_reg.h |
From: Deepak S
Squashed some of the patches and created a new patch series. Addressed review
comments on most of the patches.
Ben Widawsky (1):
drm/i915/bdw: Implement a basic PM interrupt handler
Deepak S (7):
drm/i915: Enable PM Interrupts target via Display Interface.
drm/i915/chv: En
From: Deepak S
v2: Configure PCBR if BIOS fails allocate pcbr (deepak)
v3: Fix PCBR condition check during CHV RC6 Enable flag set
v4: Fixup PCBR comment msg. (Chris)
Rebase against latest code (Deak)
Fixup Spurious hunk (Ben)
Signed-off-by: Deepak S
Acked-by: Ben Widawsky
---
drive
From: Ben Widawsky
Almost all of it is reusable from the existing code. The primary
difference is we need to do even less in the interrupt handler, since
interrupts are not shared in the same way.
The patch is mostly a copy-paste of the existing snb+ code, with updates
to the relevant parts requ
From: Deepak S
Support to individually control Media/Render well based on the register access.
Add CHV specific write function to habdle difference between registers
that are sadowed vs those that need forcewake even for writes.
v2: Drop write FIFO for CHV and add comman well forcewake (Ville)
From: Deepak S
In BDW, Apart from unmasking up/down threshold interrupts. we need
to umask bit 32 of PM_INTRMASK to route interrupts to target via Display
Interface.
v2: Add (1<<31) mask (Ville)
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c
On Wed, Apr 30, 2014 at 09:53:08PM +0300, Imre Deak wrote:
> On Wed, 2014-04-30 at 21:05 +0300, Ville Syrjälä wrote:
> > On Tue, Apr 15, 2014 at 04:39:45PM +0300, Imre Deak wrote:
> > > Atm, none of the RPM callbacks can fail, but the next patch adding
> > > RPM support for VLV changes this, so pre
On Mon, May 05, 2014 at 06:03:17PM +0530, Akash Goel wrote:
> On Mon, 2014-05-05 at 12:47 +0100, Chris Wilson wrote:
> > On Mon, May 05, 2014 at 05:13:18PM +0530, akash.g...@intel.com wrote:
> > > From: Akash Goel
> > >
> > > There is a use case, when user space (display compositor) tries
> > > t
On Mon, 2014-05-05 at 12:47 +0100, Chris Wilson wrote:
> On Mon, May 05, 2014 at 05:13:18PM +0530, akash.g...@intel.com wrote:
> > From: Akash Goel
> >
> > There is a use case, when user space (display compositor) tries
> > to directly flip a fb (without any prior rendering) on primary
> > plane.
On Mon, May 05, 2014 at 03:13:55PM +0300, Imre Deak wrote:
> Needed by the VLV S0ix context save/restore helpers.
>
> v2:
> - unchanged
> v3:
> - use proper GEN register prefixes (Ville)
>
> Signed-off-by: Imre Deak
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_reg.h | 41
> +
Add runtime PM support for VLV, but leave it disabled. The next patch
enables it.
The suspend/resume sequence used is based on [1] and [2]. In practice we
depend on the GT RC6 mechanism to save the HW context depending on the
render and media power wells. By the time we run the runtime suspend
cal
Needed by the VLV S0ix context save/restore helpers.
v2:
- unchanged
v3:
- use proper GEN register prefixes (Ville)
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/i915_reg.h | 41 -
1 file changed, 40 insertions(+), 1 deletion(-)
diff --git a/drivers/
On Mon, May 05, 2014 at 05:13:18PM +0530, akash.g...@intel.com wrote:
> From: Akash Goel
>
> There is a use case, when user space (display compositor) tries
> to directly flip a fb (without any prior rendering) on primary
> plane. So the backing pages of the object are allocated at page
> flip ti
On Wed, 2014-04-30 at 17:32 +0300, Ville Syrjälä wrote:
> On Mon, Apr 14, 2014 at 08:24:44PM +0300, Imre Deak wrote:
> > Needed by the VLV S0ix context save/restore helpers.
> >
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 43
> > +++
From: Akash Goel
There is a use case, when user space (display compositor) tries
to directly flip a fb (without any prior rendering) on primary
plane. So the backing pages of the object are allocated at page
flip time only, which takes time. Since, this buffer is supposed to
serve as a blanking b
On Sun, May 04, 2014 at 04:48:23PM +0530, akash.g...@intel.com wrote:
> From: Akash Goel
>
> We are trying to reduce the time for which the global 'struct_mutex'
> is locked. Execbuffer ioctl is one place where it is generally held
> for the longest time. And sometimes because of this occasional
On Fri, May 02, 2014 at 10:15:30AM -0700, Ben Widawsky wrote:
> On Fri, May 02, 2014 at 11:27:45AM +0100, Tvrtko Ursulin wrote:
> >
> > On 05/01/2014 07:47 PM, Ben Widawsky wrote:
> > >On Wed, Feb 26, 2014 at 04:41:41PM +, Tvrtko Ursulin wrote:
> > >>From: Tvrtko Ursulin
> > >>
> > >>Allow us
On Wed, Apr 30, 2014 at 7:35 PM, Ville Syrjälä
wrote:
> I know Daniel hates this stuff, but I don't really want to bikeshed it
> now. As we've discussed we should get the thing to enter some s0ix state
> where we actually lost the context and then dump a ton of registers and
> figure out what real
Hi Dave,
Update pull request with drm core patches. Mostly some polish for the
primary plane stuff and a pile of patches all over from Thierry. Has
survived a few days in drm-intel-nightly without causing ill.
I've frobbed my scripts a bit to also tag my topic branches so that you
have something
On Mon, May 05, 2014 at 09:55:29AM +0530, akash.g...@intel.com wrote:
> From: Akash Goel
>
> This patch could help to reduce the time, 'struct_mutex' is kept
> locked during either the exec-buffer path or Page fault
> handling path as now the backing pages are requested from shmem layer
> without
During the review of
commit 1f70999f9052f5a1b0ce1a55aff3808f2ec9fe42
Author: Chris Wilson
Date: Mon Jan 27 22:43:07 2014 +
drm/i915: Prevent recursion by retiring requests when the ring is full
Ville raised the point that our interaction with request->tail was
likely to foul up other
A few improvements to the fallback method for waiting upon ring space:
1. Fix the start/end wait tracepoints to always be paired.
2. Increase responsiveness of checking
3. Mark the process as waiting upon io
4. Check for signal interruptions
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/
Adding relevant read out comparison code, in check_crtc_state, for the new
member of crtc_config, dp_m2_n2, which was introduced to store link_m_n
values for a DP downclock mode (if available). Suggested by Daniel.
v2: Changed patch title.
Daniel's review comments incorporated.
Added relevant stat
On Tue, Apr 29, 2014 at 12:44 PM, Chris Wilson wrote:
> On Tue, Apr 29, 2014 at 11:53:58AM +0200, Daniel Vetter wrote:
>> Otherwise we'll end up spamming dmesg on every context creation on snb
>> with vt-d enabled. This regression was introduced in
>>
>> commit 246cbfb5fb9a1ca0997fbb135464c1ff5bb9
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