Gentle reminder
Regards
Shashank
-Original Message-
From: Sharma, Shashank
Sent: Friday, April 18, 2014 12:01 PM
To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; Ville
Syrjälä; Thierry Reding; Alex Deucher; Sean Paul; robdcl...@gmail.com
Cc: Shankar, Uma; Korjani, V
Booting kernel 3.15-rc2 on an AOpen i915GMm-hfs, I see the framebuffer broken.
Only about the upper left quarter of the monitor is used for displaying the
boot messages,
these (and the cursor) are replicated at the right of that area.
Approximately the lower half of the monitor stays black. The o
On 26.03.2013 17:25, Jesse Barnes wrote:
With the other bits in place, we can do this safely.
v2: disable backlight on suspend to prevent premature enablement on resume
v3: disable CRTCs on suspend to allow RTD3 (Kristen)
Signed-off-by: Jesse Barnes
I might be a bit late as your patch has lon
Hi Ville,
let me know if you want some of other small patches to be squashed.
Thanks
Deepak
On Monday 21 April 2014 01:23 PM, deepa...@linux.intel.com wrote:
From: Deepak S
Squashed some of the patches and created a new patch series.
ToDo: Address the comments on some the patches. Changes
From: Deepak S
v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)
v3: Mass rename of the dev_priv->rps variables in upstream.
Signed-off-by: Deepak S
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 10 +
dr
From: Deepak S
On CHV, All the freq request should be even. S0, we need to make sure we
request the opcode accordingly.
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/i915_drv.h | 9 +
drivers/gpu/drm/i915/i915_irq.c | 4 ++--
2 files changed, 11 insertions(+), 2 deletions(-)
diff -
From: Deepak S
Support to individually control Media/Render well based on the register access.
Add CHV specific write function to habdle difference between registers
that are sadowed vs those that need forcewake even for writes.
v2: Drop write FIFO for CHV and add comman well forcewake (Ville)
From: Ben Widawsky
Almost all of it is reusable from the existing code. The primary
difference is we need to do even less in the interrupt handler, since
interrupts are not shared in the same way.
The patch is mostly a copy-paste of the existing snb+ code, with updates
to the relevant parts requ
From: Deepak S
v2: Configure PCBR if BIOS fails allocate pcbr (deepak)
v3: Fix PCBR condition check during CHV RC6 Enable flag set
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 100 +++-
2 files chang
From: Deepak S
In BDW, Apart from unmasking up/down threshold interrupts. we need
to umask bit 32 of PM_INTRMASK to route interrupts to target via Display
Interface.
v2: Add (1<<31) mask (Ville)
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c
From: Ville Syrjälä
Streamline the CHV forcewake functions just like was done for VLV.
This will also fix a bug in accessing the common well registers,
where we'd end up trying to wake up the wells too many times
since we'd call force_wake_get/put twice per register access, with
FORCEFAKE_ALL bo
From: Deepak S
Signed-off-by: Deepak S
[vsyrjala: Fix merge fubmle where the code ended up in
g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/
From: Ville Syrjälä
Skip __gen6_gt_wait_for_thread_c0() on CHV.
Reviewed-by: Mika Kuoppala
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_uncore.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/i
From: Ville Syrjälä
CHV uses the gen8 shadow register mechanism so we shouldn't be
checking the GT FIFO status.
This effectively removes the posting read, so add an explicit
posting read using FORCEWAKE_ACK_VLV (which is what use in
vlv_forcewake_reset()).
Reviewed-by: Mika Kuoppala
Signed-off
From: Deepak S
Squashed some of the patches and created a new patch series.
ToDo: Address the comments on some the patches. Changes will be shared in next
series.
Ben Widawsky (1):
drm/i915/bdw: Implement a basic PM interrupt handler
Deepak S (6):
drm/i915: Enable PM Interrupts target via
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