Am 18.04.2014 22:38, schrieb Tejun Heo:
> Hello,
>
> Sorry about the long delay.
>
> On Thu, Apr 03, 2014 at 08:37:49AM +0200, Tobias Powalowski wrote:
>> Hi,
>> I bisected a X startup crash due to new 3.14 kernel:
>> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/fs/kernfs/
From: Chris Wilson
If we try to execute on a known ring, but it has failed to be
initialised correctly, report that the GPU is hung rather than the
command invalid. This leaves us reporting EINVAL only if the user
requests execution on a ring that is not supported by the device.
This should prev
From: Ben Widawsky
I don't have any insight on what parts can do what. The docs do seem to
suggest WT caching works in at least the same manner as it doesn't on
Haswell.
The addr = 0 is to shut up GCC:
drivers/gpu/drm/i915/i915_gem_gtt.c:80:7: warning: 'addr' may be used
uninitialized in this f
From: Ben Widawsky
Cc: Kenneth Graunke
Signed-off-by: Ben Widawsky
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_gem_context.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_
From: Deepak S
We need do forcewake before Disabling RC6, This is what the BIOS
expects while going into suspend.
v2: updated commit message. (Daniel)
Signed-off-by: Deepak S
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_pm.c | 6 ++
1 file changed, 6 insertions(+)
diff --g
From: Ben Widawsky
The same register exists for querying and programming eDRAM AKA eLLC. So
we can simply use it. For now, use all the same defaults as we had
for Haswell, since like Haswell, I have no further details.
I do not actually have a part with eDRAM, so I cannot test this.
Signed-off-
From: Chris Wilson
In the move over to use BIOS connector configs, we lost the ability to
force a specific set of connectors on or off. Try to remedy that by
dropping back to the old behavior if we detect a hard coded connector
config that tries to enable a connector (disabling is easy!).
Based
From: Chris Wilson
Across a device reset, we try to restore and user forcewake reference
counts. This is complicated by our deferred forcewake put adding an
extra reference, that may or may not be flushed when we call
del_timer_sync. So we have to take that pending reference into account
when res
From: Chris Wilson
Make sure that the whole BDB section is within the MMIO region prior to
accessing it contents. That we don't read outside of the secion is left
up to the individual section parsers.
Signed-off-by: Chris Wilson
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_bios.
From: Ben Widawsky
It seems we need this at least for the current platforms we have, but
probably not later. In any event, it should cause too much harm as we do
the same thing on several other platforms.
Signed-off-by: Ben Widawsky
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_p
From: "Yu(Alex) Dai"
Add "zorder" property to crtc to control Z-order of sprite and
primary planes. The plane tag is packed into the 64 bits value
in the order of from bottom (lower bits) to top (higher bits).
Four bits are used for each plane tag. It can support up to 16
planes.
The alpha chann
From: Chris Wilson
Be we read and chase pointers from the VBT, it is prudent to make sure
that those accesses are wholly contained within the MMIO region, or else
we may cause a kernel panic during boot.
Signed-off-by: Chris Wilson
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_bi
From: Ben Widawsky
While the context is not being used, we can make the PTEs invalid, so
nothing can accidentally corrupt it. Systems tend to have a lot of
trouble when the context gets corrupted.
NOTE: This is a slightly different patch than what I posted to Bugzilla.
References: https://bugs.
From: Chris Wilson
If we run out of stolen memory when trying to allocate an object, see if
we can reap enough purgeable objects to free up enough contiguous free
space for the allocation. This is in principle very much like evicting
objects to free up enough contiguous space in the vma when bind
This is another drm-intel-collector updated notice:
http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=drm-intel-collector
Here goes the update list in order for better reviewers assignment:
Patch drm/i915: Bring UP Power Wells before disabling RC6. - Reviewer:
Patch drm/i915: Add sup
From: Vandana Kannan
Added a property to enable user space to set aspect ratio for HDMI displays.
If there is no user specified value, then PAR_NONE/Automatic option is set
by default. User can select aspect ratio 4:3 or 16:9. The aspect ratio
selected by user would come into effect with a mode s
Hello,
Sorry about the long delay.
On Thu, Apr 03, 2014 at 08:37:49AM +0200, Tobias Powalowski wrote:
> Hi,
> I bisected a X startup crash due to new 3.14 kernel:
> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/fs/kernfs/file.c?id=9b2db6e1894577d48f4e290381bac6e573593838
On Thu, 10 Apr 2014 08:05:06 +0100 Chris Wilson
wrote:
> During testing of i915.ko with working texture sets larger than RAM, we
> encounter OOM with plenty of memory still trapped within writeback, e.g:
>
> [ 42.386039] active_anon:10134 inactive_anon:1900781 isolated_anon:32
> active_file:
On Wed, Mar 19, 2014 at 04:13:04AM -0700, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> A set of userptr test cases to support the new feature.
>
> For the eviction and swapping stress testing I have extracted
> some common behaviour from gem_evict_everything and made both
> test cases use it
This will be needed by the VLV runtime PM helpers too, so factor it out.
Also add a safety check for the case where the previous force-off is
still pending, since I'm not sure if Punit can handle a new setting
while the previous one hasn't settled yet.
v2:
- unchanged
v3:
- add a note to the comm
This is needed by the next patch moving the call out from platform
specific RPM callbacks to platform independent code.
No functional change.
v2:
- patch introduce in v2 of the patchset
v3:
- simplify platform check condition (Ville)
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/i915_drv.c
Atm, an invalid enable_rc6 module option will be silently ignored, so
emit an info message about it. Doing an early sanitization we can also
reuse intel_enable_rc6() in a follow-up patch to see if RC6 is actually
enabled. Currently the caller would have to filter a non-zero return
value based on th
While checking the error capture path I noticed that we lacked the
power domain-on check for PIPESTAT so fix this by moving that to where
the rest of pipe registers are captured.
The move also revealed that we actually don't include this register in
the error report, so fix that too.
v2:
- patch
Atm we can end up in the GPU reset deferred work in D3 state if the last
runtime PM reference is dropped between detecting a hang/scheduling the
work and executing the work. At least one such case I could trigger is
the simulated reset via the i915_wedged debugfs entry. Fix this by
disabling RPM be
On 4/16/2014 2:11 PM, Ville Syrjälä wrote:
On Tue, Apr 15, 2014 at 07:43:07PM -0700, Ben Widawsky wrote:
On Mon, Apr 14, 2014 at 10:55:53PM +0300, Ville Syrjälä wrote:
On Mon, Apr 14, 2014 at 10:41:14PM +0530, deepa...@intel.com wrote:
From: Ben Widawsky
Almost all of it is reusable from t
On 4/16/2014 2:11 PM, Ville Syrjälä wrote:
On Tue, Apr 15, 2014 at 07:43:07PM -0700, Ben Widawsky wrote:
On Mon, Apr 14, 2014 at 10:55:53PM +0300, Ville Syrjälä wrote:
On Mon, Apr 14, 2014 at 10:41:14PM +0530, deepa...@intel.com wrote:
From: Ben Widawsky
Almost all of it is reusable from t
On Wed, 2014-04-16 at 15:17 +0300, Ville Syrjälä wrote:
> On Mon, Apr 14, 2014 at 08:24:32PM +0300, Imre Deak wrote:
> > While checking the error capture path I noticed that we lacked the
> > power domain-on check for PIPESTAT so fix this by moving that to where
> > the rest of pipe registers are c
On Wed, 2014-04-16 at 20:46 +0300, Ville Syrjälä wrote:
> On Mon, Apr 14, 2014 at 08:24:40PM +0300, Imre Deak wrote:
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/i915_drv.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > b/dr
On Fri, Dec 06, 2013 at 02:11:02PM -0800, Ben Widawsky wrote:
> From: Ben Widawsky
>
> Previously we dropped the association of a context to a ring. It is
> however very important to know which ring a context ran on (we could
> have reused the other member, but I was nitpicky).
>
> This is very
On Wednesday 16 April 2014 07:02 PM, Ville Syrjälä wrote:
On Mon, Apr 14, 2014 at 10:36:55PM +0300, Ville Syrjälä wrote:
On Mon, Apr 14, 2014 at 10:41:15PM +0530, deepa...@intel.com wrote:
From: Deepak S
In BDW, Apart from unmasking up/down threshold interrupts. we need
to umask bit 32 of PM
On Friday 18 April 2014 05:58 AM, Ben Widawsky wrote:
On Wed, Apr 09, 2014 at 01:28:26PM +0300, ville.syrj...@linux.intel.com wrote:
From: Deepak S
Support to individually control Media/Render well based on the register access.
Add CHV specific write function to habdle difference between regi
A single object may be referenced by multiple registers fundamentally
breaking the static allotment of ids in the current design. When the
object is used the second time, the physical address of the first
assignment is relinquished and a second one granted. However, the
hardware is still reading (a
Currently objects for which the hardware needs a contiguous physical
address are allocated a shadow backing storage to satisfy the contraint.
This shadow buffer is not wired into the normal obj->pages and so the
physical object is incoherent with accesses via the GPU, GTT and CPU. By
setting up the
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