On Mon, 31 Mar 2014, Daniel Vetter wrote:
> VTd has a few too many "outright disable the damn thing" workarounds
> accumulated and for validation we want a simple knob to make sure we
> disable them all.
>
> Since this is for bdw+ validation and atm we don't have any
> workarounds for bdw this opt
On Tue, 2014-03-25 at 12:23 +0530, sourab gupta wrote:
> On Mon, 2014-03-24 at 17:56 +, Lespiau, Damien wrote:
> > On Mon, Mar 24, 2014 at 11:00:07PM +0530, sourab.gu...@intel.com wrote:
> > > From: Akash Goel
> > >
> > > For disabling L3 clock gating we need to set bit 25 of MMIO
> > > regis
On Mon, 2014-03-24 at 17:30 +, Gupta, Sourab wrote:
> From: Akash Goel
>
> This patch Enables the bit for TLB invalidate in GFX Mode register
> for Gen7.
>
> According to bspec, When enabled this bit limits the invalidation
> of the TLB only to batch buffer boundaries, to pipe_control
> com
Gentle Reminder for reviewing this and related patches:
http://lists.freedesktop.org/archives/intel-gfx/2014-March/042350.html
http://lists.freedesktop.org/archives/intel-gfx/2014-March/042351.html
http://lists.freedesktop.org/archives/intel-gfx/2014-March/042352.html
http://lists.freedesktop.org/a
On Thursday 27 March 2014 10:18 AM, Murthy, Arun R wrote:
On Tuesday 25 March 2014 03:16 PM, Murthy, Arun R wrote:
On Tuesday 25 March 2014 03:02 PM, Jani Nikula wrote:
On Tue, 25 Mar 2014, Chris Wilson wrote:
On Tue, Mar 25, 2014 at 02:28:22PM +0530, Arun R Murthy wrote:
In wait for vblank
On Apr-01-2014 12:35 AM, Daniel Vetter wrote:
> On Fri, Mar 21, 2014 at 08:31:29AM +0530, Vandana Kannan wrote:
>> Populate PAR in infoframe structure. If there is a user setting for PAR, then
>> that value is set. Else, value is taken from CEA mode list if VIC is found.
>> Else, PAR is calculated
On Thu, Mar 27, 2014 at 05:59:46PM +, oscar.ma...@intel.com wrote:
> --- a/drivers/gpu/drm/i915/i915_lrc.c
> +++ b/drivers/gpu/drm/i915/i915_lrc.c
> @@ -41,7 +41,45 @@
> #include
> #include "i915_drv.h"
>
> +#define GEN8_LR_CONTEXT_SIZE (21 * PAGE_SIZE)
I'm a bit puzzled by that number:
Reviewed-by: Rodrigo Vivi
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ed45143..9728c2c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++
Programming it outside of the rp0-rp1 range is considered a programming
error. Since we do not know that the previous value would actually be in
the range, program something we've read from the hardware, and therefore
know will work.
This is potentially an issue for platforms whose ranges are outs
Almost all of it is reusable from the existing code. The primary
difference is we need to do even less in the interrupt handler, since
interrupts are not shared in the same way.
The patch is mostly a copy-paste of the existing snb+ code, with updates
to the relevant parts requiring changes to the
We have a need for duplicated parsing of the RP_STATE_CAPS register (and
the setting of the associated fields). To reuse some code, we can
extract the function into a simple helper.
This patch also addresses the fact that we missed doing this for gen8,
something we should have done anyway.
This c
Reviewed-by: Rodrigo Vivi
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ed45143..9728c2c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++
Programming it outside of the rp0-rp1 range is considered a programming
error. Since we do not know that the previous value would actually be in
the range, program something we've read from the hardware, and therefore
know will work.
This is potentially an issue for platforms whose ranges are outs
We have a need for duplicated parsing of the RP_STATE_CAPS register (and
the setting of the associated fields). To reuse some code, we can
extract the function into a simple helper.
This patch also addresses the fact that we missed doing this for gen8,
something we should have done anyway.
This c
On Thu, Mar 27, 2014 at 05:59:48PM +, oscar.ma...@intel.com wrote:
> + if (ring->id == RCS)
> + reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14);
> + else
> + reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11);
In the "Register State Context", this hea
On Mon, Mar 31, 2014 at 06:56:10PM +0200, Daniel Vetter wrote:
> On Mon, Mar 31, 2014 at 6:35 PM, Ville Syrjälä
> wrote:
> >> Hmm, after some thought I am in favour of the function as a readibility
> >> improvement. However, I would prefer to have the iir check inlined
> >> into the caller.
> >
>
On Mon, Mar 31, 2014 at 09:29:41PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> These were apparently meant to protect the SAREA which only has
> room for two pipes, but things clearly went a bit wonky when
> first the .update_plane() hooks were split up and then pipe C
>
On Mon, 31 Mar 2014 21:07:04 +0200
Daniel Vetter wrote:
> On Mon, Mar 31, 2014 at 11:13:57AM -0700, Jesse Barnes wrote:
> > Going below the minimum value may affect the BLC_EN line, so try to use
> > the VBT provided minimum where possible, otherwise use an experimentally
> > derived value to pre
On Mon, Mar 31, 2014 at 11:13:57AM -0700, Jesse Barnes wrote:
> Going below the minimum value may affect the BLC_EN line, so try to use
> the VBT provided minimum where possible, otherwise use an experimentally
> derived value to prevent the panel from coming up.
"to prevent the panel form failing
On Fri, Mar 21, 2014 at 08:31:29AM +0530, Vandana Kannan wrote:
> Populate PAR in infoframe structure. If there is a user setting for PAR, then
> that value is set. Else, value is taken from CEA mode list if VIC is found.
> Else, PAR is calculated from resolution. If none of these conditions are
>
On Mon, Mar 31, 2014 at 03:22:36PM -0300, Paulo Zanoni wrote:
> 2014-03-14 15:43 GMT-03:00 Daniel Vetter :
> > On Fri, Mar 14, 2014 at 5:13 PM, Chris Wilson
> > wrote:
> >> On Fri, Mar 14, 2014 at 04:51:16PM +0100, Daniel Vetter wrote:
> >>> On Fri, Mar 14, 2014 at 08:37:15AM +, Chris Wilson
On Mon, 20 Jan 2014 19:07:23 +0200
Ville Syrjälä wrote:
> On Mon, Dec 23, 2013 at 11:27:40AM +0530, Vandana Kannan wrote:
> > Adding picture aspect ratio for CEA modes based on CEA-861D Table 3 or
> > CEA-861E Table 4. This is useful for filling up the detail in AVI
> > infoframe.
> >
> > v2: Vi
On Fri, 21 Mar 2014 08:31:29 +0530
Vandana Kannan wrote:
> Populate PAR in infoframe structure. If there is a user setting for PAR, then
> that value is set. Else, value is taken from CEA mode list if VIC is found.
> Else, PAR is calculated from resolution. If none of these conditions are
> satis
Runyan, Arthur J intel.com> writes:
>
> Please check the DRAM configuration for the systems that fail. The higher
latency is more likely with
> higher tRFC which is mainly found with 8 Gbit components.
>
What other information do we need to get this included?
The DRAM config, is this someth
From: Ville Syrjälä
These were apparently meant to protect the SAREA which only has
room for two pipes, but things clearly went a bit wonky when
first the .update_plane() hooks were split up and then pipe C
got introduced.
The checks actually protecting the SAREA live in
intel_crtc_update_sarea(
2014-03-14 15:43 GMT-03:00 Daniel Vetter :
> On Fri, Mar 14, 2014 at 5:13 PM, Chris Wilson
> wrote:
>> On Fri, Mar 14, 2014 at 04:51:16PM +0100, Daniel Vetter wrote:
>>> On Fri, Mar 14, 2014 at 08:37:15AM +, Chris Wilson wrote:
>>> > ---
>>> > drivers/gpu/drm/i915/i915_drv.c | 2 +-
>>> >
Going below the minimum value may affect the BLC_EN line, so try to use
the VBT provided minimum where possible, otherwise use an experimentally
derived value to prevent the panel from coming up.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.h| 1 +
drivers/gpu/drm/i915/inte
To make sure we properly follow the enable/disable sequences.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_dp.c| 62 --
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_panel.c | 5 ++-
3 files changed, 65 insertions(+),
With the new checks in place, we can see we're doing things backwards,
so fix them up per the spec.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_dp.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/
On Mon, Mar 31, 2014 at 11:30:02AM +0530, deepa...@linux.intel.com wrote:
> From: Deepak S
>
> Let's change the i915_cur_delayinfo to i915_frequency_info to be in sync
> with new RPS naming convention.
>
> v2: Add "i915_frequency_info" as debugfs interface name (Ben)
>
> Signed-off-by: Deepak S
On Mon, Mar 31, 2014 at 07:23:20PM +0200, Daniel Vetter wrote:
> On Mon, Mar 31, 2014 at 06:17:17PM +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Previously in
> > commit 295e8bb73a4785b65db6655fbf6ad57c4177b551
> > Author: Ville Syrjälä
> > Date: Thu Feb 27 21
On Mon, Mar 31, 2014 at 07:31:04PM +0200, Daniel Vetter wrote:
> On Mon, Mar 31, 2014 at 06:21:30PM +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Change the update_plane() plane checks to use enum plane, and
> > also fix up the error message to say something that's n
On Mon, Mar 31, 2014 at 06:21:30PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Change the update_plane() plane checks to use enum plane, and
> also fix up the error message to say something that's not total
> nonsense.
>
> FIXME killing the checks entirely is probably a
On Mon, Mar 31, 2014 at 06:17:17PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Previously in
> commit 295e8bb73a4785b65db6655fbf6ad57c4177b551
> Author: Ville Syrjälä
> Date: Thu Feb 27 21:59:01 2014 +0200
>
> drm/i915: Disable semaphore wait event idle messag
On Mon, Mar 31, 2014 at 04:44:47PM +0100, Chris Wilson wrote:
> On Mon, Mar 31, 2014 at 04:23:03PM +0200, Daniel Vetter wrote:
> > Progess according to the deprecation plan laid out in
> >
> > commit b30324adaf8d2e5950a602bde63030d15a61826f
> > Author: Daniel Vetter
> > Date: Wed Nov 13 22:11:2
On Mon, Mar 31, 2014 at 6:35 PM, Ville Syrjälä
wrote:
>> Hmm, after some thought I am in favour of the function as a readibility
>> improvement. However, I would prefer to have the iir check inlined
>> into the caller.
>
> I had it like that originally, but I moved it into the function when I
> re
On Thu, Mar 27, 2014 at 06:00:08PM +, oscar.ma...@intel.com wrote:
> + reg_state[CTX_PDP3_UDW+1] = ppgtt->pd_dma_addr[3] >> 32;
> + reg_state[CTX_PDP3_LDW+1] = ppgtt->pd_dma_addr[3];
> + reg_state[CTX_PDP2_UDW+1] = ppgtt->pd_dma_addr[2] >> 32;
> + reg_state[CTX_PDP2_LDW+1] = ppg
On Mon, Mar 31, 2014 at 04:49:28PM +0100, Chris Wilson wrote:
> On Mon, Mar 31, 2014 at 06:21:24PM +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Pull all the gmch platform hotplug interrupt handling into one
> > function.
> >
> > Signed-off-by: Ville Syrjälä
> > --
On Mon, Mar 31, 2014 at 06:21:24PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Pull all the gmch platform hotplug interrupt handling into one
> function.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_irq.c | 71
> +++--
On Mon, Mar 31, 2014 at 04:23:03PM +0200, Daniel Vetter wrote:
> Progess according to the deprecation plan laid out in
>
> commit b30324adaf8d2e5950a602bde63030d15a61826f
> Author: Daniel Vetter
> Date: Wed Nov 13 22:11:25 2013 +0100
>
> drm/i915: Deprecated UMS support
>
> and disable UM
On Mon, Mar 31, 2014 at 06:09:49PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> We don't do CPU access to GPU contexts so making the GPU access snoop
> the CPU caches seems silly, and potentially expensive.
>
> Signed-off-by: Ville Syrjälä
Maybe define a macro to be HA
From: Rafael Barbalho
The framecount register was still using the old PIPE macro instead
of the new PIPE2 macro
Signed-off-by: Rafael Barbalho
---
drivers/gpu/drm/i915/i915_reg.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers
From: Ville Syrjälä
These are mostly prep work for some future stuff.
Rafael Barbalho (1):
drm/i915: Fix framecount offset
Ville Syrjälä (6):
drm/i915: Refactor gmch hpd irq handling
drm/i915: Move DP M/N setup from update_pll to mode_set for gmch
platforms
drm/i915: Split dp post_d
From: Ville Syrjälä
DPIO reads from groups/broadcast register offsets for PCS and
TX return all 1's. If that result gets used for something
we'll probably end up doing something wrong. So warn when that
happens.
FIXME there might be some registers where all 1's is a valid value,
so ideally we sh
From: Ville Syrjälä
Print the enable_mask and status_mask from
__i915_{enable,disable}_pipestat() when the called has messed them up
somehow.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/driver
From: Ville Syrjälä
Pull all the gmch platform hotplug interrupt handling into one
function.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 71 +++--
1 file changed, 32 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/i91
From: Ville Syrjälä
Change the update_plane() plane checks to use enum plane, and
also fix up the error message to say something that's not total
nonsense.
FIXME killing the checks entirely is probably a better idea
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 14 ++
From: Ville Syrjälä
There's no point in hiding the DP M/N setup in the update_pll functions.
Just move it to the mode_set function.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm
From: Ville Syrjälä
Split the post_disable hooks for DP to g4x and vlv variants. We'll
need another variant soon, so this should make it look a bit cleaner.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_dp.c | 23 +++
1 file changed, 15 insertions(+), 8 deleti
From: Ville Syrjälä
Iterate over all the PDP registers instead of just printing PDP0 four
times in gen8 PPGTT debugfs info.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debug
From: Ville Syrjälä
(Properly) add a few more workarounds for gen8, and fix the PDP register
dumps in debugfs.
Ville Syrjälä (3):
drm/i915: Fix debugfs PDP register dump
drm/i915: Implement sema idle msg disable for all rings
drm/i915: Implement WaProgramMiArbOnOffAroundMiSetContext:bdw
From: Ville Syrjälä
Previously in
commit 295e8bb73a4785b65db6655fbf6ad57c4177b551
Author: Ville Syrjälä
Date: Thu Feb 27 21:59:01 2014 +0200
drm/i915: Disable semaphore wait event idle message on BDW
I failed to notice that all rings have their own copy of the bit that
disables the se
From: Ville Syrjälä
BSpec seems to tell us we need the MI_ARB_ON_OFF w/a around
MI_SET_CONTEXT on gen8.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_gem_context.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/
From: Ville Syrjälä
We don't do CPU access to GPU contexts so making the GPU access snoop
the CPU caches seems silly, and potentially expensive.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/
VTd has a few too many "outright disable the damn thing" workarounds
accumulated and for validation we want a simple knob to make sure we
disable them all.
Since this is for bdw+ validation and atm we don't have any
workarounds for bdw this option currently does nothing. So currently
this is just
Our validation guys want to have a positive proof that the gfx driver
is indeed using VT-d, since setting up a gfx stack, especially in
early bring-up and by people not versed in linux gfx is a bit tricky.
So provide just that.
Cc: David Woodhouse
Signed-off-by: Daniel Vetter
---
drivers/gpu/dr
Progess according to the deprecation plan laid out in
commit b30324adaf8d2e5950a602bde63030d15a61826f
Author: Daniel Vetter
Date: Wed Nov 13 22:11:25 2013 +0100
drm/i915: Deprecated UMS support
and disable UMS for 3.16.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/Kconfig | 2
On Mon, Mar 31, 2014 at 02:27:13PM +0300, Jani Nikula wrote:
> We've tried to avoid drm_i915_private_t for some time, but new uses keep
> creeping in. Should we get rid of it once and for all?
>
> Patches 1-7 are per file, patch 8 has the rest, patch 9 drops the
> typedef. The first 8 can be appli
On Mon, 31 Mar 2014, Chris Wilson wrote:
> On Mon, Mar 31, 2014 at 02:27:22PM +0300, Jani Nikula wrote:
>> There are no longer users of drm_i915_private_t. Drop the typedef. Good
>> riddance.
>
> One last test, we expect i915.ko to be the same before and after.
Any tips for this one? I tried:
$
Atm we reserve/allocate and free the power context during GT power
enable/disable time. There is no need to do this, we can reserve/allocate
the buffer once during driver loading and free it during driver cleanup.
The re-reservation can also fail in case the driver previously manages to
allocate so
On Mon, Mar 31, 2014 at 01:47:12PM +0300, Jani Nikula wrote:
> On Mon, 31 Mar 2014, Damien Lespiau wrote:
> > The reg_read whitelist has a gen bitmask to code the gens we're allowing
> > the register to be read on. Until now, it was a litteral, but we can be
> > a bit more expressive.
>
> s/litte
On Mon, Mar 31, 2014 at 02:27:22PM +0300, Jani Nikula wrote:
> There are no longer users of drm_i915_private_t. Drop the typedef. Good
> riddance.
One last test, we expect i915.ko to be the same before and after.
Good riddance,
Acked-by: Chris Wilson
-Chris
--
Chris Wilson, Intel Open Source T
There are no longer users of drm_i915_private_t. Drop the typedef. Good
riddance.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2f1d
Remove the rest of the references to drm_i915_private_t. No functional
changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_cmd_parser.c |2 +-
drivers/gpu/drm/i915/i915_drv.c|2 +-
drivers/gpu/drm/i915/i915_drv.h|6 +++---
drivers/gpu/drm/i91
No functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 38 +++
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 913b8ab5a
No functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_overlay.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_overlay.c
b/drivers/gpu/drm/i915/intel_overlay.c
index 312961a8472e..778b8fbd6cc
Also drop any unnecessary casts. No functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_dma.c | 48 +++
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
Also drop any unnecessary casts. No functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_irq.c | 110 +++
1 file changed, 55 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
No functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_gem.c | 46 +++
1 file changed, 23 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 33bbaa0d4412..c70121dbce78
No functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_display.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index ecc01f550b77..5d92d0eb776e
We've tried to avoid drm_i915_private_t for some time, but new uses keep
creeping in. Should we get rid of it once and for all?
Patches 1-7 are per file, patch 8 has the rest, patch 9 drops the
typedef. The first 8 can be applied in any order. Or squashed together
to reduce the patch count. Or if
No functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_debugfs.c | 46 +--
1 file changed, 23 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index e5d9a9027e34..4be
On Mon, 31 Mar 2014, tim.g...@intel.com wrote:
> From: tgore
Please configure git to use your real name instead of login.
Thanks,
Jani.
--
Jani Nikula, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
ht
From: tgore
A recent commit means igt_debugfs.c now needs to include igt_kms.h,
which in turn includes igt_fb.h and hence cairo.h.
We need to avoid this inclusion of cairo.h when building for Android,
(until we have a cairo port) so I have added a #ifndef around it.
Signed-off-by: Tim Gore
---
From: tgore
This is a rework of the third patch in a previous series of 3,
to accomodate a simplification suggested by Daniel Vetter.
tgore (1):
intel-gpu-tools: avoid include of cairo.h on Android builds
lib/Android.mk | 3 ++-
lib/igt_fb.h | 5 +
2 files changed, 7 insertions(+), 1 d
On Mon, 31 Mar 2014, Damien Lespiau wrote:
> The reg_read whitelist has a gen bitmask to code the gens we're allowing
> the register to be read on. Until now, it was a litteral, but we can be
> a bit more expressive.
s/litteral/literal/
Reviewed-by: Jani Nikula
>
> To ease the review, a small
The reg_read whitelist has a gen bitmask to code the gens we're allowing
the register to be read on. Until now, it was a litteral, but we can be
a bit more expressive.
To ease the review, a small test program:
$ cat bit-range.c
#include
#include
#define U32_C(x) x ## U
#
On Mon, Mar 31, 2014 at 11:30:02AM +0530, deepa...@linux.intel.com wrote:
> From: Deepak S
>
> Let's change the i915_cur_delayinfo to i915_frequency_info to be in sync
> with new RPS naming convention.
>
> v2: Add "i915_frequency_info" as debugfs interface name (Ben)
>
> Signed-off-by: Deepak S
On Sun, Mar 30, 2014 at 12:30:56PM +0530, deepa...@linux.intel.com wrote:
> From: Deepak S
>
> This reverts commit f64a28a7c5ab2fc342326de9e126acf3cc0f91d6.
>
> As per the inputs provided by hardware team we still use DDR
> Rates as 0,1=800, 2=1066, 3=1333.
> With this change, Turbo freqs used
On Sun, Mar 30, 2014 at 12:08:35PM +0530, Deepak S wrote:
>
> On Friday 28 March 2014 01:33 PM, Chris Wilson wrote:
> >The speculation is that we can conserve more power by masking off
> >the interrupts at source (PMINTRMSK) rather than filtering them by the
> >up/down thresholds (RPINTLIM). We ca
Dear developers,
I have the same problem as the one described by Michael bellow: the
Intel Graphic card produces eye strain and headache after some minutes
of using it. I found a lot of people complaining on the same problem,
but no solution. I tried lowering the resolution, increasing the PWM
fre
On Sun, 30 Mar 2014, Kenneth de Mello wrote:
> What about dual-link DVI? I though the additional link addressed the
> pixel clock limitation. Has it only been using a single link this entire
> time, and it's only worked by ignoring the maximum dotclock, so in other
> words, the fact it works a
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