On Mon, 2014-02-17 at 19:51 +0200, Ville Syrjälä wrote:
> On Mon, Feb 17, 2014 at 10:53:50PM +0530, Sagar Arun Kamble wrote:
> > On Fri, 2014-02-14 at 13:39 +0200, Ville Syrjälä wrote:
> > > On Fri, Feb 14, 2014 at 04:31:17PM +0530, Sagar Arun Kamble wrote:
> > > > On Wed, 2014-02-12 at 23:15 +0200
Some system's ACPI video backlight control interface is broken and the
native backlight control interface should be used by default. This patch
sets the use_native_backlight parameter to true for those systems so
that video backlight control interface will not be created. For detailed
models that a
RC6 works a lot like HW contexts in that when the GPU enters RC6 it
saves away the state to a context, and loads it upon wake.
It's to be somewhat expected that BIOS will not set up valid GPU state.
As a result, if loading bad state can cause the GPU to get angry, it
would make sense then that we
RC6 works a lot like HW contexts in that when the GPU enters RC6 it
saves away the state to a context, and loads it upon wake.
It's to be somewhat expected that BIOS will not set up valid GPU state.
As a result, if loading bad state can cause the GPU to get angry, it
would make sense then that we
Reviewed-by: Rodrigo Vivi
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ac8419d..6259e47 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++
We have a need for duplicated parsing of the RP_STATE_CAPS register (and
the setting of the associated fields). To reuse some code, we can
extract the function into a simple helper.
This patch also addresses the fact that we missed doing this for gen8,
something we should have done anyway.
This c
Programming it outside of the rp0-rp1 range is considered a programming
error. Since we do not know that the previous value would actually be in
the range, program something we've read from the hardware, and therefore
know will work.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_pm.
It is tested and looking fairly stable now, so turn it on. It wasn't
intentionally turned off originally :P
Reviewed-by: Rodrigo Vivi
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm
With the renamed RPS struct members, it's easier to skip the local
variables which no longer clarify anything, and if anything just make
the code harder to read.
The real motivation for this patch is actually the next patch, which
attempts to consolidate some of the functionality.
Cc: Jeff McGee
Almost all of it is reusable from the existing code. The primary
difference is we need to do even less in the interrupt handler, since
interrupts are not shared in the same way.
The patch is mostly a copy-paste of the existing snb+ code, with updates
to the relevant parts requiring changes to the
The values created at initialization must always exist to use the
interface. Reading them again is confusing, and pointless.
More cleanups are coming in the next patch. Since I am not 100% certain,
moreso on BYT, (though I am extremely close to that) that there is no
need to leave the MMIO here, I
Here is the v2 of the RC6, and RPS enabling for Broadwell. With the last
patch in the series RC6 works without hangs (in limited testing).
Without the last patch, the first batch seems to always hang. I don't
think there any actual fixes over the last version. I changed enough of
the RPS code to no
RC6 works a lot like HW contexts in that when the GPU enters RC6 it
saves away the state to a context, and loads it upon wake.
It's to be somewhat expected that BIOS will not set up valid GPU state.
As a result, if loading bad state can cause the GPU to get angry, it
would make sense then that we
Introduced:
commit b8a5ff8d7c676a04e0da5ec16bb068dd39459042
Author: Jeff McGee
Date: Tue Feb 4 11:37:01 2014 -0600
drm/i915: Update rps interrupt limits
Cc: Jeff McGee
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_sysfs.c | 20 ++--
1 file changed, 10 inserti
The existing code (which I changed last) was very convoluted. I believe
it was attempting to skip the overclock portion if the previous pcode
write failed. When I last touched the code, I was preserving this
behavior. There is some benefit to doing it that way in that if the
first pcode access fail
The names of the struct members for RPS are stupid. Every time I need to
do anything in this code I have to spend a significant amount of time to
remember what it all means. By renaming the variables (and adding the
comments) I hope to clear up the situation. Indeed doing this make some
upcoming pa
Summary
We covered the platform: Broadwell, Baytrail-M, Haswell mobile, HSW desktop,
HSW ULT, IvyBridge, SandyBridge, IronLake.
In this circle, 8 new bugs are filed, 43 bugs are still opened, no WONTFIX
bugs, 1 INVALID bugs , no NOTABUG bugs ,no NOTOURBUG bugs, 4 Duplicated bugs, 1
REOPENED bugs
Suggested by Daniel.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_pm.c | 33 ++---
1 file changed, 30 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e81e7de..21ccf89 100644
--- a/drivers/g
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_pm.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 21ccf89..68f58e5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm
Based on an early draft from Jesse.
Add support for powering on/off the dynamic power wells on VLV by
registering its display and dpio dynamic power wells with the power
domain framework.
For now power on all PHY TX lanes regardless of the actual lane
configuration. Later this can be optimized wh
This way we can reuse the check on other platforms too. Also factor out
a version of the function that doesn't check if the power is on, we'll
need to call this from within the power domain framework.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/
We need to do the same for other platforms in upcoming patches.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_pm.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9cb7ed6..e81e7d
On VLV at least the display IRQ register access and functionality
depends on its power well to be on, so move the power domain HW init
before we install the IRQs.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/i915_dma.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/
We'll need to disable/re-enable the display-side IRQs when turning
off/on the VLV display power well. Factor out the helper functions
for this. For now keep the display IRQs enabled by default, so the
functionality doesn't change. This will be changed to enable/disable
the IRQs on-demand when addin
Parts that poke port specific HW blocks like the encoder HW state
readout or connector hotplug detect code need a way to check whether
required power domains are on or enable/disable these. For this purpose
add a set of power domains that refer to the port HW blocks. Get the
proper port power domai
An always-on power well can be already recognized by the lack of
is_enabled handler, so just depend on that. Suggested by Daniel.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/intel_pm.c | 5 +
2 files changed, 1 insertion(+), 5 deletions(-)
diff -
In the upcoming patches we'll need to access the rest of the fields in
the punit power gating register, so prepare for that.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/i915_reg.h | 29 +++--
drivers/gpu/drm/i915/intel_uncore.c | 4 +++-
2 files changed, 26 ins
The connector detect and get_mode handlers need to access the port
specific HW blocks to read the EDID etc. Get/put the port power domains
around these handlers.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_crt.c | 42
drivers/gpu/drm/i915/inte
This is a left-over from
commit b7e634cc8dcd320123199a18bae0937b40dc28b8
Author: Imre Deak
Date: Tue Feb 4 21:35:45 2014 +0200
drm/i915: vlv: don't unmask IIR[DISPLAY_PIPE_A/B_VBLANK] interrupt
where we stopped unmasking the vblank IRQs, but left them enabled in the
IER register. Disable them
We can read out the pipe HW state only if the required power domain is
on. If not we consider the pipe to be off.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_display.c | 19 +++
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_
These functions will be needed by the valleyview specific power well
update functionality added in an upcoming patch, so move them earlier.
No functional change.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_display.c | 140 +--
1 file changed, 70 inser
The power domains framework is internal to the i915 driver, so pass
drm_i915_private instead of drm_device to its functions.
Also remove a dangling intel_set_power_well() declaration.
No functional change.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/i915_dma.c | 14
drivers
Since the encoder is tied to its port, we need to make sure the power
domain for that port is on before reading out the encoder HW state.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 23 ++-
drivers/gpu/drm/
These macros are used only locally, so move them to the .c file.
Also since logically the init power domain should be part of all power
wells add it to the always-on power wells too for consistency. Since
always-on power wells have noop handlers, this doesn't change the
functionality.
Signed-off-
Split the 'set' power well handler into an 'enable', 'disable' and
'sync_hw' handler. This maps more conveniently to higher level
operations, for example it allows us to push the hsw package c8 handling
into the corresponding hsw/bdw enable/disable handlers and the hsw BIOS
hand-over setting into t
These functions are used only by a single call site and are simple
enough to just fold them in.
No functional change.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_pm.c | 37 +
1 file changed, 13 insertions(+), 24 deletions(-)
diff --git a/drivers/
This patchset adds support for enabling/disabling dynamic power-wells on
VLV on-demand.
Before enabling on-demand power well toggling the patchset adds the
checks for required power domains for places that poke at the HW. These
are the pipe, encoder and connector HW state readout functions. It als
On Mon, Feb 17, 2014 at 12:04:19PM -0800, Ben Widawsky wrote:
> On Thu, Feb 06, 2014 at 11:54:44AM -0200, Rodrigo Vivi wrote:
> > On Wed, Jan 29, 2014 at 2:25 AM, Ben Widawsky
> > wrote:
> > > It is tested and looking fairly stable now, so turn it on. It wasn't
> > > intentionally turned off origi
On Thu, Feb 06, 2014 at 11:54:44AM -0200, Rodrigo Vivi wrote:
> On Wed, Jan 29, 2014 at 2:25 AM, Ben Widawsky
> wrote:
> > It is tested and looking fairly stable now, so turn it on. It wasn't
> > intentionally turned off originally :P
> >
> > Signed-off-by: Ben Widawsky
> > ---
> > drivers/gpu/d
On Thu, Feb 06, 2014 at 12:15:12PM -0200, Rodrigo Vivi wrote:
> On Wed, Jan 29, 2014 at 2:25 AM, Ben Widawsky
> wrote:
> > Almost all of it is reusable from the existing code. The primary
> > difference is we need to do even less in the interrupt handler, since
> > interrupts are not shared in the
On Fri, Feb 14, 2014 at 08:41:08PM +, Chris Wilson wrote:
> On Fri, Feb 14, 2014 at 12:34:22PM -0800, Ben Widawsky wrote:
> > On Tue, Feb 11, 2014 at 05:12:17PM +0100, Daniel Vetter wrote:
> > > - 6/9 lacks review ...
> > >
> >
> > 6/9 can be skipped for this series, though I think it's a rea
On Mon, Feb 17, 2014 at 01:16:54PM +0100, Hans de Goede wrote:
> Since the helper is a standalone app, the usual xserver rules of not using
> stdio because of signal handling don't apply.
>
> And since the helper does run with elevated rights, it is important to keep
> the code KISS so that it can
On Mon, Feb 17, 2014 at 10:53:50PM +0530, Sagar Arun Kamble wrote:
> On Fri, 2014-02-14 at 13:39 +0200, Ville Syrjälä wrote:
> > On Fri, Feb 14, 2014 at 04:31:17PM +0530, Sagar Arun Kamble wrote:
> > > On Wed, 2014-02-12 at 23:15 +0200, ville.syrj...@linux.intel.com wrote:
> > > > From: Ville Syrjä
On Fri, 2014-02-14 at 13:39 +0200, Ville Syrjälä wrote:
> On Fri, Feb 14, 2014 at 04:31:17PM +0530, Sagar Arun Kamble wrote:
> > On Wed, 2014-02-12 at 23:15 +0200, ville.syrj...@linux.intel.com wrote:
> > > From: Ville Syrjälä
> > >
> > > The cursor plane also supports 180 degree rotation. Add a
Event though we've failed to open the backlight normally, we may still be
running under a suid-root xserver, so drop any elevated rights before
executing what we hope will be pkxec.
Signed-off-by: Hans de Goede
---
src/backlight.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/backl
Since the helper is a standalone app, the usual xserver rules of not using
stdio because of signal handling don't apply.
And since the helper does run with elevated rights, it is important to keep
the code KISS so that it can be audited easily.
This commit replaces the hard to read "raw" read loo
Update the comment about trying suid-root first with some explanations of
why pkexec may be preferable in some cases.
Signed-off-by: Hans de Goede
---
src/backlight.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/backlight.c b/src/backlight.c
index 70c6559..0e63ba
Hi All,
I've tried the backlight code as merged with X running as a regular user +
pkexec, and they work as advertised.
When reviewing the changes I noticed some minor and not so minor (security!)
issues, which this patch series address.
Thanks & Regards,
Hans
__
Event though we've failed to open the backlight normally, we may still be
running under a suid-root xserver, so use the servers build in System instead
of system so as to properly drop root rights.
Signed-off-by: Hans de Goede
---
src/backlight.c | 3 ++-
1 file changed, 2 insertions(+), 1 delet
On Fri, Feb 14, 2014 at 10:34:43PM +, Chris Wilson wrote:
> In commit e4e0c058a19c41150d12ad2d3023b3cf09c5de67
> Author: Eugeni Dodonov
> Date: Wed Feb 8 12:53:50 2012 -0800
>
> drm/i915: gen7: Implement an L3 caching workaround.
>
> the L3 cache aging was disabled. This was part of a
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