At Thu, 23 Jan 2014 06:35:12 +,
Lin, Mengdong wrote:
>
> > -Original Message-
> > From: Takashi Iwai [mailto:ti...@suse.de]
> > Sent: Thursday, January 23, 2014 1:19 AM
> > To: Daniel Vetter
> > Cc: Lin, Mengdong; Barnes, Jesse; Zanoni, Paulo R;
> > alsa-de...@alsa-project.org; intel-g
On 01/22/2014 11:41 PM, Jani Nikula wrote:
On Thu, 23 Jan 2014, Todd Previte wrote:
Add new definitions for hotplug live status bits for VLV2 since they're
in reverse order from the gen4x ones.
Changelog:
- Restored gen4 bit definitions
- Added new definitions for VLV2
- Added platform check
Fixed the trailing brace for the switch() statement in gen4x_dp_detect()
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Add new definitions for hotplug live status bits for VLV2 since they're
in reverse order from the gen4x ones.
Changelog:
- Restored gen4 bit definitions
- Added new definitions for VLV2
- Added platform check for IS_VALLEYVIEW() in dp_detect to use the correct
bit defintions
- Replaced a lost tr
On Thu, 23 Jan 2014, Todd Previte wrote:
> Add new definitions for hotplug live status bits for VLV2 since they're
> in reverse order from the gen4x ones.
>
> Changelog:
> - Restored gen4 bit definitions
> - Added new definitions for VLV2
> - Added platform check for IS_VALLEYVIEW() in dp_detect t
On Thu, 23 Jan 2014, Todd Previte wrote:
> Add new definitions for hotplug live status bits for VLV2 since they're
> in reverse order from the gen4x ones.
>
> Changelog:
> - Restored gen4 bit definitions
> - Added new definitions for VLV2
> - Added platform check for IS_VALLEYVIEW() in dp_detect t
> -Original Message-
> From: Takashi Iwai [mailto:ti...@suse.de]
> Sent: Thursday, January 23, 2014 1:19 AM
> To: Daniel Vetter
> Cc: Lin, Mengdong; Barnes, Jesse; Zanoni, Paulo R;
> alsa-de...@alsa-project.org; intel-gfx@lists.freedesktop.org; dri-devel
> Subject: Re: Need your advice: Add
On Wed, 22 Jan 2014, Daniel Vetter wrote:
> Just figured I'll comment on these two issues, patches themselves look
> really nice \o/
Look nice they do, but it also makes me a little sad that neither git
grep nor my source code tagging system will no longer find where the
registers are accessed. T
Add new definitions for hotplug live status bits for VLV2 since they're
in reverse order from the gen4x ones.
Changelog:
- Restored gen4 bit definitions
- Added new definitions for VLV2
- Added platform check for IS_VALLEYVIEW() in dp_detect to use the correct
bit defintions
Signed-off-by: Todd
Addresses the comments and feedback herein. VLV2 and gen4 have separate bit
definitions now. The correct bits are selected in gen4x_dp_detect() based on
the detected platform.
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freede
Since acpi_evaluate_object() returns acpi_status and not plain int,
ACPI_FAILURE() should be used for checking its return value. Also
add some detailed debug info when acpi_evaluate_object() failed.
Reviewed-by: Jani Nikula
Acked-by: Bjorn Helgaas
Signed-off-by: Yijing Wang
---
v4->v5: Add some
On 2014/1/23 5:37, Bjorn Helgaas wrote:
> On Mon, Jan 20, 2014 at 7:46 PM, Yijing Wang wrote:
>> Since acpi_evaluate_object() returns acpi_status and not plain int,
>> ACPI_FAILURE() should be used for checking its return value.
>>
>> Reviewed-by: Jani Nikula
>> Signed-off-by: Yijing Wang
>> ---
On Wed, Jan 22, 2014 at 2:06 AM, Daniel Vetter wrote:
> Hi Stephen,
>
> On Wed, Jan 22, 2014 at 4:04 AM, Stephen Rothwell
> wrote:
>> Hi all,
>>
>> Today's linux-next merge of the drm-intel tree got a conflict in
>> drivers/gpu/drm/i915/i915_irq.c between commit abca9e454498 ("drm: Pass
>> 'flag
On 11/22/13 1:36 AM, Takashi Iwai wrote:
I got kernel WARNINGs frequently on Haswell laptops complaining about
invalid max DP link bw. With drm.debug=0x0e, it turned out that the
obtained DPCD is utterly bogus when it happens:
[drm:intel_dp_get_dpcd], DPCD: 4d 4d 4d 4d 4d 4d 4d 4d 4d 4d 4d 4d
Yijing Wang wrote:
>Fix acpi_evaluate_object() return value check,
>shoud acpi_status not int.
Should be?
Your mailer also ate the word 'to' .
>
>Signed-off-by: Yijing Wang
>---
>
>v1->v2: Add CC to the related subsystem MAINTAINERS.
>
>---
> drivers/gpu/drm/i915/intel_acpi.c | 13
At least I couldn't find it in the Haswell Bspec any more and we've
tried to test-boot a Haswell machine with num_pipes forced to 0 (i.e.
hit the PCH_NOP path) and the unclaimed register logic complained.
So restrict this dance to just ivb platforms.
v2: Art pointed out that the bits simply moved
At least I couldn't find it in the Haswell Bspec any more and we've
tried to test-boot a Haswell machine with num_pipes forced to 0 (i.e.
hit the PCH_NOP path) and the unclaimed register logic complained.
So restrict this dance to just ivb platforms.
v2: Art pointed out that the bits simply moved
On Wed, Jan 22, 2014 at 10:32:04PM +0100, Daniel Vetter wrote:
> At least I couldn't find it in the Haswell Bspec any more and we've
> tried to test-boot a Haswell machine with num_pipes forced to 0 (i.e.
> hit the PCH_NOP path) and the unclaimed register logic complained.
>
> So restrict this dan
At least I couldn't find it in the Haswell Bspec any more and we've
tried to test-boot a Haswell machine with num_pipes forced to 0 (i.e.
hit the PCH_NOP path) and the unclaimed register logic complained.
So restrict this dance to just ivb platforms.
v2: Art pointed out that the bits simply moved
On Wed, Jan 22, 2014 at 05:52:18PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> Hi
>
> Back in July 2013 I sent an email asking about interrupts and suggesting ways
> to
> improve our code [0]. Based on those discussions, I submitted a patch series
> proposing some changes [1]. I receive
Forgot to convert to using the refclk variable when I added refclk
readout support, and Paulo noticed the resulting calculation was off due
to the way p & r are stored.
Reported-by: Paulo Zanoni
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_ddi.c | 3 ++-
1 file changed, 2 insertio
On Wed, 22 Jan 2014 18:39:26 -0200
Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> This stops the WARNs when booting with an HDMI monitor connected.
>
> Signed-off-by: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a
On Wed, Jan 22, 2014 at 02:40:42PM -0600, Jeff McGee wrote:
> There doesn't seem to be anything like the exit handlers for running when
> a subtest exits. I need a failed subtest to be able to cleanup after
> itself to avoid contaminating subsequent subtests. Have I missed something?
> Perhaps this
The equivalent function moved to register NDE_RSTWRN_OPT bit 4 "RST PCH
Handshake En" on Haswell. You'll need to convert the WAIT_FOR_PCH_*_ACK
programming over to that new location.
>-Original Message-
>From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch]
>Sent: Wednesday, January 22
From: Paulo Zanoni
This stops the WARNs when booting with an HDMI monitor connected.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_ddi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index fe
There doesn't seem to be anything like the exit handlers for running when
a subtest exits. I need a failed subtest to be able to cleanup after
itself to avoid contaminating subsequent subtests. Have I missed something?
Perhaps this is not a problem when running subtests individually through
piglit?
From: Paulo Zanoni
Hi
Back in July 2013 I sent an email asking about interrupts and suggesting ways to
improve our code [0]. Based on those discussions, I submitted a patch series
proposing some changes [1]. I received some reviews and the general idea was
accepted, but due to priority changes I
From: Paulo Zanoni
So we can merge all the common code from postinstall and uninstall.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 26 +++---
1 file changed, 7 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/d
From: Paulo Zanoni
And the equivalent GEN8_IRQ_INIT_NDX macro. These macros are for the
postinstall functions. The next patch will improve this macro.
Notice that I could have included POSTING_READ calls to the macro, but
that would mean the code would do a few more POSTING_READs than
necessary.
From: Paulo Zanoni
We should only enable interrupts at postinstall.
And now on ILK/SNB/IVB/HSW the irq_preinstall and irq_postinstall
functions leave the hardware in the same state.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 10 --
1 file changed, 4 insertions(+
From: Paulo Zanoni
The duplicate was at an _uninstall function, so rename it to
gen5_gt_irq_reset.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i
From: Paulo Zanoni
On the preinstall stage we should just disable all the interrupts, but
we currently enable all the south display interrupts due to the way we
touch SDEIER at the IRQ handlers (note: they are still masked and our
IRQ handler is disabled). Instead of doing that, let's make the
pr
From: Paulo Zanoni
This interrupt gets initialized with a different IER value, so it was
not using the macro. The problem is that we plan to modify the macro
to make it do additional things, and we want the SDE interrupts
updated too. So let's make sure we call the macro, then, after it, we
do th
From: Paulo Zanoni
Instead of trying to clear it again. It should already be masked and
disabled and zeroed at preinstall/uninstall.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 32 +++-
1 file changed, 15 insertions(+), 17 deletions(-)
diff --
From: Paulo Zanoni
The IRQ_INIT and IRQ_FINI macros are basically the same thing, with
the exception that IRQ_FINI doesn't properly clear IIR twice and
doesn't have as many POSTING_READs as IRQ_INIT. So rename the macro to
IRQ_RESET and use it everywhere.
Signed-off-by: Paulo Zanoni
---
driver
From: Paulo Zanoni
To merge the common code of ironlake_irq_preinstall and
ironlake_irq_uninstall.
We should also probably do something about that HSWSTAM write on a
later commit.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 23 ---
1 file changed, 12
From: Paulo Zanoni
We basically never test the uninstall path today, that's why this
works.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d58c392..65d
From: Paulo Zanoni
After the latest changes, ibx_irq_preinstall and ibx_irq_uninstall are
the same, so remove one of the copies and rename the other to
ibx_irq_reset (since we're using the "reset" name for things which are
called both at preinstall and uninstall).
Signed-off-by: Paulo Zanoni
--
From: Paulo Zanoni
Just like ibx_irq_preinstall. We'll call this from somewhere else in
the next patch.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 21 ++---
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/d
From: Paulo Zanoni
Missing from gen8_irq_uninstall.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5d8d262..02594f9 100644
--- a/drivers/gpu/drm/i915/i
From: Paulo Zanoni
After all, we call ibx_irq_preinstall from gen8_irq_preinstall.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 128dbbc..60f4c46 1006
From: Paulo Zanoni
Same as SERR_INT and the other IIR registers: reset on
preinstall/uninstall and WARN for non-zero values at postinstall. This
one also doesn't need double-clear.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 7 +--
1 file changed, 5 insertions(+), 2 d
From: Paulo Zanoni
And rename is to GEN5_IRQ_INIT.
We have discussed doing equivalent changes on July 2013, and I even
sent a patch series for this: "[PATCH 00/15] Unify interrupt register
init/reset". Now that the BDW code was merged, I have one more
argument in favor of these changes.
Here's
From: Paulo Zanoni
The SERR_INT register is very similar to the other IIR registers, so
let's zero it at preinstall/uninstall and WARN for a non-zero value at
postinstall, just like we do with the other IIR registers. For this
one, there's no need to double-clear since it can't store more than
on
From: Paulo Zanoni
The goal is to reuse the GEN8 macros, but a few changes are needed, so
let's make things easier to review.
I could also use these macros on older code, but since I plan to
change how the interrupts are initialized, we'll risk breaking the
older code in the next commits, so I'l
From: Paulo Zanoni
Same as the _INIT macro: the goal is to reuse the GEN8 macros, but
there are still some slight differences.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i
From: Ville Syrjälä
We're disabling a boatload of clock gating features on VLV. Maybe these
days we don't need to do that. At least I'm not aware of any workarounds
with this level of paranoia.
This reverts commit 4e8c84a5b14bbb5b88c63941f1d939560f4abd0b.
Signed-off-by: Ville Syrjälä
---
driv
From: Ville Syrjälä
WaApplyL3ControlAndL3ChickenMode is only relevant to early HSW
steppings..
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 70f3b
From: Ville Syrjälä
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b9b4fe4..d18e43b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i9
From: Ville Syrjälä
Can't find WaDisableRHWOOptimizationForRenderHang listed for VLV.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f9c44d2..895046f
From: Ville Syrjälä
WaDisableRCCUnitClockGating is only relevant for SNB.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f40dd1b..1
From: Ville Syrjälä
Only early VLV steppings needed thist. Should no longer be relevant.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 14 +++---
1 file changed, 3 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/i
From: Ville Syrjälä
Both Bspec and the W/A database state that WaDisablePSDDualDispatchEnable
is only needed for IVB GT1.
The only real confusion here is that the the W/A database also says to
write to the GT2 only register as well, which is strange if the W/A is
only for GT1.
Signed-off-by: Vi
From: Ville Syrjälä
BSpec states that the thread override values set by
gen7_setup_fixed_func_scheduler() are invalid for HSW. So let's not
muck around with them.
Since gen7_setup_fixed_func_scheduler() now has two totally independent
parts, one for IVB and one for HSW, move the HSW part directl
From: Ville Syrjälä
Someone copy pasted the comment from the SNB code w/o reading it.
We never actually implemented the workaround to disable RCPB unit
clock gating on IVB. It would have been needed for early steppings,
but we don't care about those anymore, so just remove the stale
comment.
Sig
From: Ville Syrjälä
Can't find any mention of WaDisableVDSUnitClockGating ever being
relevant for SNB. Remove it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers
From: Ville Syrjälä
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bbaf8c7..6a1d98a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i9
From: Ville Syrjälä
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6c0a10a..0e724c9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/
From: Ville Syrjälä
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index ec96002..9006a87 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++
From: Ville Syrjälä
Here's a resurrected version of my workaround cleanup series from last
summer. I dropped a few patches I deemed incorrect and rebased the lot.
I also added the VLV clock gating revert on top. I had that patch sitting
in a branch but apparently never sent it out.
I've today t
From: Ville Syrjälä
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 6 ++
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 242f540..c3039e1 100644
--- a/drivers/
From: Ville Syrjälä
WaDisableRCCUnitClockGating is only relevant for SNB.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1e1c1b1..d
From: Ville Syrjälä
Can't find WaDisableRHWOOptimizationForRenderHang listed for HSW.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d8381b5..f9c44d2
From: Ville Syrjälä
Call gen7_setup_fixed_func_scheduler() on VLV as well.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 376a52e..ff
From: Ville Syrjälä
The current comments indicate that this function implements
WaVSRefCountFullforceMissDisable, which is only true for HSW.
The original purpose of the function is to implement
WaVSThreadDispatchOverride (and a bit more). Fix up the comments
to match reality.
Signed-off-by: Vil
From: Ville Syrjälä
WaMiSetContext_Hang tells us that a MI_NOOP must follow MI_SET_CONTEXT.
The other thing WaMiSetContext_Hang seems to say is that URB_FENCE isn't
allowed to straddle two cachelines. But we don't issue those from the
kernel so we don't care.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
WaDisable4x2SubspanOptimization isn't listed for VLV in the workaround
database, but BSpec says that the relevant bit must be set. Add a
comment to remind people of this.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 4
1 file changed, 4 insertions
From: Ville Syrjälä
I can't see WaDisableDopClockGating listed for IVB in W/A database.
Also I'm not quite sure we were even disabling the right thing. Register
0x9424 has one DOP clock gating disable bit, amd 0xe4f4/0xf4f4 appears
to have another one, but I don't actually know which is the one
From: Ville Syrjälä
WaDisableTDLUnitClockGating is only relevant for early steppings of VLV.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1a45566..dd68
From: Ville Syrjälä
WaDisableRCZUnitClockGating was needed with early HSW steppings only.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bf45b4c..70
From: Ville Syrjälä
WaDisableVDSUtnitClockGating was only relevant for early steepings of
VLV.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 593046a.
From: Ville Syrjälä
WaApplyL3ControlAndL3ChickenMode is only listed for IVB and HSW in
W/A database and BSpec.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
From: Ville Syrjälä
IVB GT2 has two registers for these things, and both must be written.
To add a bit more confusion both Bspec and the W/A database state that
WaDisablePSDDualDispatchEnable is only needed for IVB GT1, but the W/A
database also says to write even the second GT2 only register. S
From: Ville Syrjälä
The w/a database lists both WaPsdDispatchEnable and
WaDisablePSDDualDispatchEnable for VLV. They appear to be the same
thing, so list both names.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu
From: Ville Syrjälä
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0e724c9..bbaf8c7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/
On Tue, Jan 21, 2014 at 02:15:51PM +0100, Daniel Vetter wrote:
> On Sun, Jan 19, 2014 at 1:47 PM, Ramalingam C wrote:
> > To remove the wait_for_vblank from the plane switch execution path,
> > this change implements a function which will add a delayed work to
> > defer the IPS enable.
> >
> > The
On Wed, Jan 22, 2014 at 5:59 PM, Jesse Barnes wrote:
> Great, thanks Deepak. And this mail looks a lot nicer. :) Thunderbird
> definitely molests mail less readily than Outlook.
Yeah, congrats to upgrading to a real mua ;-)
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0)
On Wed, Jan 22, 2014 at 12:23 PM, Takashi Iwai wrote:
> At Wed, 22 Jan 2014 10:45:26 -0500,
> Rob Clark wrote:
>>
>> On Wed, Jan 22, 2014 at 10:20 AM, Daniel Vetter wrote:
>> > On Wed, Jan 22, 2014 at 10:04:14AM -0500, Rob Clark wrote:
>> >> sorry to jump into this a bit late, so maybe this was c
At Wed, 22 Jan 2014 15:18:21 +0100,
Daniel Vetter wrote:
>
> On Wed, Jan 22, 2014 at 12:48:04PM +, Lin, Mengdong wrote:
> > > -Original Message-
> > > From: daniel.vet...@ffwll.ch [mailto:daniel.vet...@ffwll.ch] On Behalf Of
> > > Daniel Vetter
> > > Sent: Tuesday, January 21, 2014 9:1
At Wed, 22 Jan 2014 10:45:26 -0500,
Rob Clark wrote:
>
> On Wed, Jan 22, 2014 at 10:20 AM, Daniel Vetter wrote:
> > On Wed, Jan 22, 2014 at 10:04:14AM -0500, Rob Clark wrote:
> >> sorry to jump into this a bit late, so maybe this was covered already
> >> earlier..
> >
> > It just started, I've q
On Wed, 22 Jan 2014 22:07:53 +0530
"S, Deepak" wrote:
>
>
> On 1/22/2014 10:04 PM, Jesse Barnes wrote:
> > On Tue, 21 Jan 2014 17:18:59 +0200
> > Ville Syrjälä wrote:
> >
> >> On Mon, Jan 20, 2014 at 06:40:26PM +0530, deepa...@intel.com wrote:
> >>> From: Deepak S
> >>>
> >>> With RC6 enabled
On 1/22/2014 10:04 PM, Jesse Barnes wrote:
On Tue, 21 Jan 2014 17:18:59 +0200
Ville Syrjälä wrote:
On Mon, Jan 20, 2014 at 06:40:26PM +0530, deepa...@intel.com wrote:
From: Deepak S
With RC6 enabled, BYT has an HW issue in determining the right
Gfx busyness.
WA for Turbo + RC6: Use SW bas
On Tue, 21 Jan 2014 17:18:59 +0200
Ville Syrjälä wrote:
> On Mon, Jan 20, 2014 at 06:40:26PM +0530, deepa...@intel.com wrote:
> > From: Deepak S
> >
> > With RC6 enabled, BYT has an HW issue in determining the right
> > Gfx busyness.
> > WA for Turbo + RC6: Use SW based Gfx busy-ness detection
On Wed, Jan 22, 2014 at 10:20 AM, Daniel Vetter wrote:
> On Wed, Jan 22, 2014 at 10:04:14AM -0500, Rob Clark wrote:
>> sorry to jump into this a bit late, so maybe this was covered already
>> earlier..
>
> It just started, I've quoted everything when cc'ing dri-devel. But good to
> have examples
If we have stopped rings then we know that test is running
so no need for spam. In addition, only spam when default
context gets banned.
v2: - make sure default context ban gets shown (Chris)
- use helper for checking for default context, everywhere (Chris)
Reference: https://bugs.freedesktop
On Wed, Jan 22, 2014 at 10:04:14AM -0500, Rob Clark wrote:
> sorry to jump into this a bit late, so maybe this was covered already
> earlier..
It just started, I've quoted everything when cc'ing dri-devel. But good to
have examples outside of x86 (where things are mostly standardized by the
Eye o
On Wed, Jan 22, 2014 at 9:18 AM, Daniel Vetter wrote:
> On Wed, Jan 22, 2014 at 12:48:04PM +, Lin, Mengdong wrote:
>> > -Original Message-
>> > From: daniel.vet...@ffwll.ch [mailto:daniel.vet...@ffwll.ch] On Behalf Of
>> > Daniel Vetter
>> > Sent: Tuesday, January 21, 2014 9:11 PM
>> >
On Wed, Jan 22, 2014 at 02:26:26PM +, Damien Lespiau wrote:
> On Wed, Jan 22, 2014 at 02:36:08PM +0200, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Add a few new debugfs files which allow changing the watermark memory
> > latency values during runtime. This can be use
On Mon, 23 Dec 2013, Vandana Kannan wrote:
> For Broadwell, there is one instance of Transcoder MN values per transcoder.
> For dynamic switching between multiple refreshr rates, M/N values may be
> reprogrammed on the fly. Link N programming triggers update of all data and
> link M & N registers
On Mon, 23 Dec 2013, Vandana Kannan wrote:
> Adding support to detect display idleness by tracking page flip from
> user space. Switch to low refresh rate is triggered after 2 seconds of
> idleness. The delay is configurable. If there is a page flip or call to
> update the plane, then high refresh
On Wed, Jan 22, 2014 at 02:36:08PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Add a few new debugfs files which allow changing the watermark memory
> latency values during runtime. This can be used to determine the if the
> original BIOS provided latency values are no g
On Wed, Jan 22, 2014 at 12:48:04PM +, Lin, Mengdong wrote:
> > -Original Message-
> > From: daniel.vet...@ffwll.ch [mailto:daniel.vet...@ffwll.ch] On Behalf Of
> > Daniel Vetter
> > Sent: Tuesday, January 21, 2014 9:11 PM
> > To: Lin, Mengdong
> > Cc: Takashi Iwai (ti...@suse.de); Barne
On Mon, 23 Dec 2013, Vandana Kannan wrote:
> From: Pradeep Bhat
>
> This patch computes and stored 2nd M/N/TU for switching to different
> refresh rate dynamically. PIPECONF_EDP_RR_MODE_SWITCH bit helps toggle
> between alternate refresh rates programmed in 2nd M/N/TU registers.
>
> v2: Daniel's
2014/1/22 :
> From: Naresh Kumar Kachhi
>
> with current code intel_runtime_pm_gpu_idle is getting called
> even before runtime_pm is initialized. Moving runtime_pm_init
> before i915_gem_init
>
> Following is the call stack, note: by this time
> runtime_pm was not initialized
>
> intel_runtime_p
Hi
2014/1/22 :
> From: Naresh Kumar Kachhi
>
> Once the display is disabled, we need to call runtime_put to
> make sure Runtime framework triggers runtime_suspend based on
> idleness. Similarly when display gets enabled, runtime_get should
> be called. We have similiar function for pc8 feature,
2014/1/22 :
> From: Naresh Kumar Kachhi
>
> GPU idleness is tracked by checking the request queue. Whenever
> request queue is empty we assume that GPU is idle. When a new
> set of commands sheduled on ring we call i915_add_request to
> make sure these commands are tracked properly. However there
2014/1/22 :
> From: Naresh Kumar Kachhi
>
> With runtime PM enabled, we need to make sure that all HW access
> are valid (i.e. Gfx is in D0). Invalid accesses might end up in
> HW hangs. Ex. A hang is seen if display register is accessed on
> BYT while display power island is power gated.
>
> Th
On Mon, 23 Dec 2013, Vandana Kannan wrote:
> From: Pradeep Bhat
>
> This patch and finds out the lowest refresh rate supported for the resolution
> same as the fixed_mode, based on the implementaion find_panel_downclock.
> It also checks the VBT fields to see if panel supports seamless DRRS or no
On Wed, 2014-01-22 at 13:51 +0100, Daniel Vetter wrote:
> On Wed, Jan 22, 2014 at 05:34:17PM +0530, naresh.kumar.kac...@intel.com wrote:
> > From: Naresh Kumar Kachhi
> >
> > With runtime PM enabled, we need to make sure that all HW access
> > are valid (i.e. Gfx is in D0). Invalid accesses migh
On Mon, 23 Dec 2013, Vandana Kannan wrote:
> From: Pradeep Bhat
>
> This patch reads the DRRS support and Mode type from VBT fields.
> The read information will be stored in VBT struct during BIOS
> parsing. The above functionality is needed for decision making
> whether DRRS feature is supported
1 - 100 of 132 matches
Mail list logo
