Reported-by: Patrick McMunn
Signed-off-by: Ben Widawsky
---
configure.ac| 21 ++---
debugger/system_routine/Makefile.am | 1 +
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/configure.ac b/configure.ac
index b43f45c..55cc78f 100644
--- a
On 12/20 12:32, Paulo Zanoni wrote:
> 2013/12/19 Daniel Vetter :
> > On Thu, Dec 19, 2013 at 10:12 PM, Paulo Zanoni wrote:
> >> From: Paulo Zanoni
> >>
> >> When I forked haswell_crtc_enable I copied all the code from
> >> ironlake_crtc_enable. The last piece of the function contains a big
> >> c
Hi Dave,
We're back to the regular -next updates. Somehow still not too much going
on really, I guess everyone was thinking about vacation already ;-)
On that topic: I'll be offline for 2 weeks now. I don't really expect much
to happen and 3.13 seems to be in good shape. But in case something is
This was introduced in:
commit 7c4a395ff8f441acb7876281c6777624e6410349
Author: Ville Syrjälä
Date: Wed Oct 9 19:17:56 2013 +0300
drm/i915: Don't re-compute pipe watermarks except for the affected pipe
and I missed fixing it in:
commit fec8cba306f974f3a4491176994de5d821273643
Author: Jes
Provide some simple checks to make sure things haven't completely blown
up. Once the PPGTT is mostly stable, these checks can be removed.
These are primarily meant to catch cases where our software tracking
(drm_mm) somehow got out of sync with what we expect of the hardware.
Or, cases where we've
On Fri, Dec 20, 2013 at 04:37:34PM +0200, Jani Nikula wrote:
> On Fri, 20 Dec 2013, Daniel Vetter wrote:
> > On Thu, Dec 19, 2013 at 10:55:56PM -0800, Ben Widawsky wrote:
> >> On Fri, Dec 20, 2013 at 07:05:10AM +0100, Daniel Vetter wrote:
> >> > On Fri, Dec 20, 2013 at 12:22 AM, Ben Widawsky
> >>
On Fri, Dec 20, 2013 at 03:11:09PM +0100, Daniel Vetter wrote:
> On Thu, Dec 19, 2013 at 10:55:56PM -0800, Ben Widawsky wrote:
> > On Fri, Dec 20, 2013 at 07:05:10AM +0100, Daniel Vetter wrote:
> > > On Fri, Dec 20, 2013 at 12:22 AM, Ben Widawsky
> > > wrote:
> > > > ctx = i915_gem_context
From: Paulo Zanoni
We're iterating over the CPU transcoders, so check for the correct
power domain.
This fixes many "unclaimed register" error messages.
This can be reproduced by the IGT test mentioned below, but we still
get a FAIL when we run it.
Testcase: igt/kms_lip/flip-vs-panning-vs-hang
On Fri, 20 Dec 2013, Daniel Vetter wrote:
> Suggested by Paulo.
>
> Signed-off-by: Daniel Vetter
> ---
> README | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git a/README b/README
> index 246e24c47ffe..f108b2087a98 100644
> --- a/README
> +++ b/README
> @@ -40,6 +40,16 @@ tests/
Suggested by Paulo.
Signed-off-by: Daniel Vetter
---
README | 10 ++
1 file changed, 10 insertions(+)
diff --git a/README b/README
index 246e24c47ffe..f108b2087a98 100644
--- a/README
+++ b/README
@@ -40,6 +40,16 @@ tests/
piglit-sources $ cd bin
piglit-sources/bin $ ln
On Fri, 20 Dec 2013, Daniel Vetter wrote:
> On Thu, Dec 19, 2013 at 10:55:56PM -0800, Ben Widawsky wrote:
>> On Fri, Dec 20, 2013 at 07:05:10AM +0100, Daniel Vetter wrote:
>> > On Fri, Dec 20, 2013 at 12:22 AM, Ben Widawsky
>> > wrote:
>> > > ctx = i915_gem_context_get(file->driver_priv,
2013/12/19 Daniel Vetter :
> On Thu, Dec 19, 2013 at 10:12 PM, Paulo Zanoni wrote:
>> From: Paulo Zanoni
>>
>> When I forked haswell_crtc_enable I copied all the code from
>> ironlake_crtc_enable. The last piece of the function contains a big
>> comment with a call to intel_wait_for_vblank. After
On Fri, Dec 20, 2013 at 11:30:15AM +0200, Jani Nikula wrote:
> On Thu, 19 Dec 2013, Paulo Zanoni wrote:
> > From: Paulo Zanoni
> >
> > The eDP spec defines some points where after you do action A, you have
> > to wait some time before action B. The thing is that in our driver
> > action B does no
On Thu, Dec 19, 2013 at 08:45:59AM -0500, Alex Deucher wrote:
> On Thu, Dec 19, 2013 at 5:04 AM, Vandana Kannan
> wrote:
> > Adding picture aspect ratio for CEA modes based on CEA-861D Table 3 or
> > CEA-861E Table 4. This is useful for filling up the detail in AVI
> > infoframe.
> >
> > v2: Ville
On Thu, Dec 19, 2013 at 10:55:56PM -0800, Ben Widawsky wrote:
> On Fri, Dec 20, 2013 at 07:05:10AM +0100, Daniel Vetter wrote:
> > On Fri, Dec 20, 2013 at 12:22 AM, Ben Widawsky
> > wrote:
> > > ctx = i915_gem_context_get(file->driver_priv, args->ctx_id);
> > > - if (IS_ERR(ctx)) {
>
On Fri, Dec 20, 2013 at 1:29 PM, Jani Nikula
wrote:
>> Signed-off-by: Pradeep Bhat
>> Signed-off-by: Vandana Kannan
>> Reviewed-by: Daniel Vetter
>> Reviewed-by: Chris Wilson
>> Reviewed-by: Jani Nikula
>
> I'm sorry, this is not true. Only I get to say when you can add my
> Reviewed-by.
Yea
On Fri, 20 Dec 2013, Vandana Kannan wrote:
> From: Pradeep Bhat
>
> This patch and finds out the lowest refresh rate supported for the resolution
> same as the fixed_mode, based on the implementaion find_panel_downclock.
> It also checks the VBT fields to see if panel supports seamless DRRS or no
From: Pradeep Bhat
This patch computes and stored 2nd M/N/TU for switching to different
refresh rate dynamically. PIPECONF_EDP_RR_MODE_SWITCH bit helps toggle
between alternate refresh rates programmed in 2nd M/N/TU registers.
v2: Daniel's review comments
Computing M2/N2 in compute_config and st
For Broadwell, there is one instance of Transcoder MN values per transcoder.
For dynamic switching between multiple refreshr rates, M/N values may be
reprogrammed on the fly. Link N programming triggers update of all data and
link M & N registers and the new M/N values will be used in the next fram
From: Pradeep Bhat
This patch reads the DRRS support and Mode type from VBT fields.
The read information will be stored in VBT struct during BIOS
parsing. The above functionality is needed for decision making
whether DRRS feature is supported in i915 driver for eDP panels.
This information helps
Dynamic Refresh Rate Switching (DRRS) is a power conservation feature which
enabled swtiching between low and high refresh rates based on the usage
scenario. This feature is applciable for internal eDP panel. Indication that
the panel supports DRRS is given by the panel EDID, whic
From: Pradeep Bhat
This patch and finds out the lowest refresh rate supported for the resolution
same as the fixed_mode, based on the implementaion find_panel_downclock.
It also checks the VBT fields to see if panel supports seamless DRRS or not.
Based on above data it marks whether eDP panel sup
Adding support to detect display idleness by tracking page flip from
user space. Switch to low refresh rate is triggered after 2 seconds of
idleness. The delay is configurable. If there is a page flip or call to
update the plane, then high refresh rate is applied.
The feature is not used in dual-di
On Thu, 19 Dec 2013, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> The eDP spec defines some points where after you do action A, you have
> to wait some time before action B. The thing is that in our driver
> action B does not happen exactly after action A, but we still use
> msleep() calls direct
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