From: Pradeep Bhat
This patch provides necessary support to read the Dynamic Media
Refresh Rate (DMRRS) field from VBT. This information will be used
by DRRS feature to create additional refresh rates needed for
media use cases like video playback. This patch is tested by enabling
DRM Logs. This
From: Pradeep Bhat
This patch reads the DRRS support and Mode type from VBT fields.
The read information will be stored in VBT struct during BIOS
parsing. The above functionality is needed for decision making
whether DRRS feature is supported in i915 driver for eDP panels.
This information helps
From: Pradeep Bhat
This patch provides a set_property interface for user space to
seamlessly switch between different DRRS refresh rates. The
patch creates the property only if seamless DRRS is supported.
It implements the support for computing Data & Link M/N for any
given Refresh Rate and progr
From: Pradeep Bhat
This patch provides support for two additional DRRS refresh rates
which will be used for video playback use cases. When the playback
is at 24fps, player can indicate the DRRS to set 48Hz. Similarly
for playback of 25fps DRRS 50Hz is used. This helps in better
power saving in ac
Dynamic Refresh Rate Switching (DRRS) is a power conservation feature which
enables switching between low and high refresh rates based on the usage
scenario. This feature is applicable for internal eDP panel. Indication that
the panel can support DRRS is given by the panel EDID, w
From: Pradeep Bhat
This patch parses the eDP EDID probed_mode list and finds out the
lowest refresh rate supported for the resolution same as the
fixed_mode. It also checks the VBT fields to see if panel supports
seamless DRRS or not. Based on above data it marks whether eDP
panel supports seamle
Adding support to detect display idleness by tracking page flip from
user space. Switch to low refresh rate is triggered after 2 seconds of
idleness. The delay is configurable. If there is a page flip or call to
update the plane, then high refresh rate is applied.
The feature is not used in dual-di
On Mon, Nov 18, 2013 at 6:32 PM, Rodrigo Vivi wrote:
>
> This is another drm-intel-collector updated notice:
> http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=drm-intel-collector
>
> Here goes the update list in order for better reviewers assignment:
>
> Patch drm/i915: Asynchronously pe
Hi Daniel,
could you help me to assign best reviewers for these patches?
also, please let me know if I should just remove patch 1 out from -collector.
Thanks in advance,
Rodrigo.
On Mon, Nov 18, 2013 at 6:32 PM, Rodrigo Vivi wrote:
>
> This is another drm-intel-collector updated notice:
> http:
From: Chris Wilson
A simple modeset, where we only wish to switch over to a new framebuffer
such as the transition from fbcon to X, takes around 30-60ms. This is
due to three factors:
1. We need to make sure the fb->obj is in the display domain, which
incurs a cache flush to ensure no dirt is le
From: Mengdong Lin
This patch defines audio configuration registers and adds audio enabling code
for Valleyview2.
Signed-off-by: Mengdong Lin
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_reg.h | 18 ++
drivers/gpu/drm/i915/intel_display.c | 23 +++
From: Ville Syrjälä
We send the primary and cursor plane data through the gamma unit.
In order to get matching output from sprites, also send the sprite
data through the gamma unit.
In the future we should add some properties to control this
explicitly, and also add properties for the per-sprite
From: Daniel Vetter
This is useful when we only have aliasing ppgtt and want to figure out
what exactly is accesssible and what not. Paulo can somehow overwrite
the fbcon framebuffer with the blitter on his hsw machine ...
v2: Actually make it compile.
Cc: Paulo Zanoni
Signed-off-by: Daniel Ve
From: Chris Wilson
If the hardware does not support package C8, then do not even schedule
work to enable it. Thereby we can eliminate a bunch of dangerous work.
Signed-off-by: Chris Wilson
Cc: Paulo Zanoni
Reviewed-by: Paulo Zanoni
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_d
From: Chris Wilson
We need to hold the pc8 lock around toggling the value of gpu_idle.
Signed-off-by: Chris Wilson
Cc: Paulo Zanoni
Reviewed-by: Paulo Zanoni
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_display.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
d
This is another drm-intel-collector updated notice:
http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=drm-intel-collector
Here goes the update list in order for better reviewers assignment:
Patch drm/i915: Asynchronously perform the set-base for a simple modeset -
Reviewed by me.
Patch
From: Chris Wilson
If we force the hw to idle as our first step during unload, we can abort
the unload upon failure. Later we can probe whether the hardware remain
active even after we try to shut it down.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_dma.c | 10 ++
1 file
From: Ville Syrjälä
Use the same wait_for_vblank code for CTG that we use for ILK+.
Also fix the name of the frame counter register while at it.
Signed-off-by: Ville Syrjälä
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_display.c | 8
1 file changed, 4 insertions(+), 4
From: Ville Syrjälä
When the hardware frame counter reads 0xff and we're already past
vblank start, we'd return 0x100 as the vblank counter value. Once
we'd cross into the next frame's active portion, the vblank counter
would wrap to 0. So we're reporting two different vblank counter valu
I'm just on going with another -collector update and since this patch
fixes a bug I think it would be a good one to include.
But since it was bikeshedded it is better to ask Ville and Chris if
their comments was a NAck or I can consider to get for -collector.
Thanks
On Sat, Nov 2, 2013 at 9:10 A
On Mon, Nov 18, 2013 at 10:14:26PM +0200, Ville Syrjälä wrote:
> On Mon, Nov 18, 2013 at 09:00:58AM +0100, Daniel Vetter wrote:
> > We need this to properly fill in adjusted_mode.crtc_clock, otherwise
> > the state checker gets unhappy. This seems to have been forgotten in
> > the big clock rework
On Mon, Nov 18, 2013 at 09:00:58AM +0100, Daniel Vetter wrote:
> We need this to properly fill in adjusted_mode.crtc_clock, otherwise
> the state checker gets unhappy. This seems to have been forgotten in
> the big clock rework in
>
> commit 18442d08786472c63a0a80c27f92b033dffc26de
> Author: Ville
Hi Stephen,
You may want to CC intel-gfx@lists.freedesktop.org for i915 issues (even
if you are not subscribed and you mail will wait for a moderator to let
it go through).
In case of intel GPU hangs you should at least include
/sys/kernel/debug/dri/0/i915_error_state, probably submitting as a
b
On Mon, Nov 18, 2013 at 02:48:08PM -0200, Paulo Zanoni wrote:
> 2013/11/16 Daniel Vetter :
> > This was forgotten in
> >
> > commit 9d1cb9147dbe45f6e94dc796518ecf67cb64b359
> > Author: Paulo Zanoni
> > Date: Fri Nov 1 13:32:08 2013 -0200
> >
> > drm/i915: avoid unclaimed registers when captu
2013/11/16 Daniel Vetter :
> This was forgotten in
>
> commit 9d1cb9147dbe45f6e94dc796518ecf67cb64b359
> Author: Paulo Zanoni
> Date: Fri Nov 1 13:32:08 2013 -0200
>
> drm/i915: avoid unclaimed registers when capturing the error state
>
> Cc: Paulo Zanoni
> Signed-off-by: Daniel Vetter
Re
2013/11/15 Jani Nikula :
> Similar to
> commit fdbc3b1f639bb2cbfb32c612b2699e0ba373317d
> Author: Jani Nikula
> Date: Tue Nov 12 17:10:13 2013 +0200
>
> drm/i915/dp: set sink to power down mode on dp disable
>
> but for DDI, where we've never done this.
>
> Signed-off-by: Jani Nikula
Makes
On Mon, Nov 18, 2013 at 5:31 PM, Thierry Reding
wrote:
>> Note that there's already a bit of abstraction for i2c over dp aux, but
>> imo that's at the wrong level. At least reading through i915, gma500 and
>> radeon code there's a lot more we could share with just a dp aux helper
>> library (which
On Mon, Nov 18, 2013 at 05:20:54PM +0100, Daniel Vetter wrote:
> On Mon, Nov 18, 2013 at 04:26:17PM +0100, Thierry Reding wrote:
> > On Mon, Nov 18, 2013 at 10:09:56AM -0500, Alex Deucher wrote:
> > > On Mon, Nov 18, 2013 at 9:27 AM, Thierry Reding
> > > wrote:
> > > > On Fri, Nov 15, 2013 at 03:0
On Mon, Nov 18, 2013 at 02:45:09PM +, Chris Wilson wrote:
> We call intel_modeset_setup_hw_state() along two paths, driver
> load/resume and after a lid event notification. During initialisation of
> the driver, it is imperative that we reset the config state. This
> correctly sets up the initi
On Mon, Nov 18, 2013 at 04:34:44PM +0200, Mika Kuoppala wrote:
> Large parts of hw initialization is behind per gen
> clock gating functions. Including workarounds.
>
> Call intel_modeset_init_hw after reset so that we
> set these up correctly.
>
> Signed-off-by: Mika Kuoppala
> ---
> drivers/g
On Mon, Nov 18, 2013 at 04:26:17PM +0100, Thierry Reding wrote:
> On Mon, Nov 18, 2013 at 10:09:56AM -0500, Alex Deucher wrote:
> > On Mon, Nov 18, 2013 at 9:27 AM, Thierry Reding
> > wrote:
> > > On Fri, Nov 15, 2013 at 03:01:51PM +0200, Jani Nikula wrote:
> > >> Debug print the capabilities, and
On Mon, Nov 18, 2013 at 12:01:13PM +, Damien Lespiau wrote:
> On Wed, Oct 30, 2013 at 06:27:43PM -0200, Paulo Zanoni wrote:
> > From: Paulo Zanoni
> >
> > It seems we do have machines with 3 HDMI/DVI outputs, so sharing
> > WRPLLs is the only way to get 3 pipes working.
> >
> > Bugzilla: htt
Hi All,
I am running a repetitive test on HSW with max available RAM limited to
1GB (max TOLUD is 1GB) and it fails with NULL pointer dereference in
execbuf ioctl.
Debug showed that the batch_obj->gtt_space which was valid becomes NULL
before it is dispatched. During debug I stored batch_obj->gtt
On Mon, Nov 18, 2013 at 10:09:56AM -0500, Alex Deucher wrote:
> On Mon, Nov 18, 2013 at 9:27 AM, Thierry Reding
> wrote:
> > On Fri, Nov 15, 2013 at 03:01:51PM +0200, Jani Nikula wrote:
> >> Debug print the capabilities, and flag an error if the panel does not
> >> support adjusting backlight thro
On Thu, Nov 14, 2013 at 07:09:48PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 14, 2013 at 02:54:10PM +0200, Mika Kuoppala wrote:
> > ville.syrj...@linux.intel.com writes:
> >
> > > From: Ville Syrjälä
> > >
> > > On VLV GTFIFODBG has more bits. Just report them all.
> > >
> > > Signed-off-by: Vill
On Mon, Nov 18, 2013 at 9:27 AM, Thierry Reding
wrote:
> On Fri, Nov 15, 2013 at 03:01:51PM +0200, Jani Nikula wrote:
>> Debug print the capabilities, and flag an error if the panel does not
>> support adjusting backlight through the BL_PWM_DIM pin, requiring
>> backlight control through DPCD.
>>
We call intel_modeset_setup_hw_state() along two paths, driver
load/resume and after a lid event notification. During initialisation of
the driver, it is imperative that we reset the config state. This
correctly sets up the initial connector statuses and prepares the
hardware for a thorough probing
Large parts of hw initialization is behind per gen
clock gating functions. Including workarounds.
Call intel_modeset_init_hw after reset so that we
set these up correctly.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/d
On Fri, Nov 15, 2013 at 03:01:51PM +0200, Jani Nikula wrote:
> Debug print the capabilities, and flag an error if the panel does not
> support adjusting backlight through the BL_PWM_DIM pin, requiring
> backlight control through DPCD.
>
> I haven't seen such panels yet, but it's a matter of time.
On Fri, Nov 15, 2013 at 03:01:50PM +0200, Jani Nikula wrote:
> Preparing for the future eDP panels.
>
> Signed-off-by: Jani Nikula
> ---
> include/drm/drm_dp_helper.h | 29 +
> 1 file changed, 29 insertions(+)
Reviewed-by: Thierry Reding
pgpHkgWFbeRBT.pgp
Descri
On Wed, Oct 30, 2013 at 06:27:44PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni
> @@ -657,10 +657,8 @@ bool intel_ddi_pll_mode_set(struct drm_crtc *crtc)
> return false;
> }
>
> - /* We don't need to turn any PLL on because we'll use LCPLL. */
>
On Wed, Oct 30, 2013 at 06:27:43PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> It seems we do have machines with 3 HDMI/DVI outputs, so sharing
> WRPLLs is the only way to get 3 pipes working.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=68485
> Signed-off-by: Paulo Zanoni
On Sun, Nov 17, 2013 at 05:46:44AM -0800, Grant wrote:
> >>> > Thank you, here's what I get:
> >>> >
> >>> > # addr2line -e /usr/lib64/xorg/modules/drivers/intel_drv.so -i
> >>> > 0x2fe79 0x3037f
> >>>
> >>> Grant - I'm assuming that this was done on the emerged
> >>> xf86-video-in
On Sun, Nov 17, 2013 at 10:25:02PM +0100, Daniel Vetter wrote:
> Otherwise we risk that the 2nd part of the line ends up on a line of
> it's own, which means a kernel dmesg line without a log level. This
> then upsets the dmesg checker in piglit.
>
> Only really happens in some of the truly nasty
Hi Daniel, hi intel experts,
please find a patch attached concerning the watermark levels on the i830
chipsets.
I did a couple of experiments this morning and found that the watermark
on i830 may neither be
too small (i.e. the FW_BLC register values may not be too high) as
otherwise the FIFO
We must have one to fill out the adjusted_mode.crtc_clock. And with
the tv encoder fixed up every encoder we have has a ->get_config
callback. So we can drop the checks.
Cc: Ville Syrjälä
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_display.c | 6 ++
1 file changed, 2 inserti
We need this to properly fill in adjusted_mode.crtc_clock, otherwise
the state checker gets unhappy. This seems to have been forgotten in
the big clock rework in
commit 18442d08786472c63a0a80c27f92b033dffc26de
Author: Ville Syrjälä
Date: Fri Sep 13 16:00:08 2013 +0300
drm/i915: Fix port_cl
On Thu, Oct 31, 2013 at 09:53:36AM +0100, Daniel Vetter wrote:
> Now we have this everywhere. Next up would be to wire up the DP
> hotplug pin to speed up panel power sequencing for eDP panels ...
>
> I've decided to leave the has_aux_irq logic in the code, it should
> come handy for hw bringup.
>
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