MSR Nov 2013, Kevin Rogovin
Benchmark Suite:
Creation of a benchmark suite (found on Teamforge) where each benchmark
stresses a particular point of an OpenGL implementation. A number of bugs have
been found and reported from running this suite on Mesa:
https://bugs.freedesktop.org/show_b
On Mon, Nov 11, 2013 at 02:46:28PM -0800, Ben Widawsky wrote:
> The pipe B and pipe C interrupt mask and enable registers are now part
> of the pipe, so disabling the pipe power wells will lost the contests of
> the registers.
>
> Art totally debugged this one!
>
> v2: Use the irq_lock to clarify
On 11/08/2013 10:11 AM, Damien Lespiau wrote:
> On Wed, Oct 30, 2013 at 03:44:16PM +0200, Mika Kuoppala wrote:
>> This ioctl returns reset stats for specified context.
>>
>> The struct returned contains context loss counters.
>>
>> reset_count:all resets across all contexts
>> batch_active: a
On Thu, Nov 07, 2013 at 09:40:51PM -0800, Ben Widawsky wrote:
> Because of the way in which we're allocating the pages for the Aliasing
> PPGTT, we cannot actually successfully alloc enough space for anything
> greater than 2GB.
>
> Instead of a quick hack to fix this, we should defer until we hav
The pipe B and pipe C interrupt mask and enable registers are now part
of the pipe, so disabling the pipe power wells will lost the contests of
the registers.
Art totally debugged this one!
v2: Use the irq_lock to clarify code, and prevent future bugs (Daniel)
Cc: Art Runyan
Cc: Paulo Zanoni
S
This way the igt test will always be killed first (hopefully),
preventing mayhem when one of the memory thrashing tests treatens to
take down the entire system.
To avoid any burden on test writers we adjust the oom score on
drm_open, any of the fork helpers and subtest init. That should cover
ever
On Mon, Nov 11, 2013 at 04:54:32PM -0200, Paulo Zanoni wrote:
> 2013/11/11 Daniel Vetter :
> > On Mon, Nov 11, 2013 at 04:25:36PM -0200, Paulo Zanoni wrote:
> >> 2013/11/11 Daniel Vetter :
> >> > On Mon, Nov 11, 2013 at 03:06:10PM -0200, Paulo Zanoni wrote:
> >> >> From: Paulo Zanoni
> >> >>
> >>
Ian Romanick writes:
> From: Ian Romanick
>
> The drm_intel_context structure is, wisely, opaque. However, libdrm
> users may want to know the hardware context ID associated with the
> structure.
We've had a bunch of our other structures be partially transparent. The
context id to be passed t
On Mon, Nov 11, 2013 at 03:49:01PM +, Mateo Lozano, Oscar wrote:
> Hi Ben,
>
> I have drv_suspend running in a loop for a few hours now and I haven´t been
> able to hit that problem. Could you give some more info? were you using
> piglit? were you able to reproduce it systematically?
>
> I
2013/11/11 Daniel Vetter :
> On Mon, Nov 11, 2013 at 04:25:36PM -0200, Paulo Zanoni wrote:
>> 2013/11/11 Daniel Vetter :
>> > On Mon, Nov 11, 2013 at 03:06:10PM -0200, Paulo Zanoni wrote:
>> >> From: Paulo Zanoni
>> >>
>> >> We recently fixed a bug where it was impossible to do I2C transactions
>>
On Mon, Nov 11, 2013 at 04:18:04PM -0200, Paulo Zanoni wrote:
> 2013/11/11 Daniel Vetter :
> > On Mon, Nov 11, 2013 at 03:06:09PM -0200, Paulo Zanoni wrote:
> >> From: Paulo Zanoni
> >>
> >> These functions should help you checking for new Kernel error
> >> messages. One of the problems I had whil
On Mon, Nov 11, 2013 at 04:25:36PM -0200, Paulo Zanoni wrote:
> 2013/11/11 Daniel Vetter :
> > On Mon, Nov 11, 2013 at 03:06:10PM -0200, Paulo Zanoni wrote:
> >> From: Paulo Zanoni
> >>
> >> We recently fixed a bug where it was impossible to do I2C transactions
> >> on eDP panels when they were di
On Mon, Nov 11, 2013 at 03:36:55PM +, oscar.ma...@intel.com wrote:
> From: Oscar Mateo
>
> Some shells do not understand "&>". For instance, my Ubuntu 12.04
> machine has /bin/sh pointing to dash, which makes a mess out of
> "&>" (to the point that the helper processes cannot be killed).
>
>
2013/11/11 Daniel Vetter :
> On Mon, Nov 11, 2013 at 03:06:10PM -0200, Paulo Zanoni wrote:
>> From: Paulo Zanoni
>>
>> We recently fixed a bug where it was impossible to do I2C transactions
>> on eDP panels when they were disabled. Now it should be possible to do
>> these transactions when the pan
On Mon, Nov 11, 2013 at 11:12:57AM +0200, Jani Nikula wrote:
> From: Ben Widawsky
>
> Prior to Haswell the CPU control register for backlight
> (BLC_PWM_CPU_CTL) toggled the PCH baclight pin for us. This made some
> sense as there was no pin on the CPU. With Haswell came the introduction
> of a C
On Fri, Nov 08, 2013 at 10:20:06AM -0800, Ben Widawsky wrote:
> For what we care about ULT and ULX are interchangeable. We know of 3
> types of pciids for these cases. I am not sure if at some point we will
> need to distinguish ULT and ULX.
>
> Cc: Paulo Zanoni
> Signed-off-by: Ben Widawsky
I
2013/11/11 Daniel Vetter :
> On Mon, Nov 11, 2013 at 03:06:09PM -0200, Paulo Zanoni wrote:
>> From: Paulo Zanoni
>>
>> These functions should help you checking for new Kernel error
>> messages. One of the problems I had while writing the runtime PM test
>> suite is that when you read the sysfs and
On Mon, Nov 11, 2013 at 03:06:10PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> We recently fixed a bug where it was impossible to do I2C transactions
> on eDP panels when they were disabled. Now it should be possible to do
> these transactions when the panel is disabled, but there's a rac
On Mon, Nov 11, 2013 at 03:06:09PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> These functions should help you checking for new Kernel error
> messages. One of the problems I had while writing the runtime PM test
> suite is that when you read the sysfs and debugfs files, the only way
> to
On Mon, Nov 11, 2013 at 03:49:01PM +, Siluvery, Arun wrote:
> On Mon, 2013-11-11 at 16:31 +0100, Daniel Vetter wrote:
> > On Mon, Nov 11, 2013 at 02:58:31PM +, Siluvery, Arun wrote:
> > > From: "Siluvery, Arun"
> > >
> > > This patchset contains changes for Timeout detection and recovery
From: Ian Romanick
The drm_intel_context structure is, wisely, opaque. However, libdrm
users may want to know the hardware context ID associated with the
structure.
Signed-off-by: Ian Romanick
Cc: Ben Widawsky
---
intel/intel_bufmgr.h | 1 +
intel/intel_bufmgr_gem.c | 6 ++
2 files c
From: Ian Romanick
Previously GCC was squaking about:
intel_bufmgr_gem.c: In function 'drm_intel_gem_bo_map_unsynchronized':
intel_bufmgr_gem.c:1325:20: warning: unused variable 'bo_gem'
[-Wunused-variable]
Wrapping with VG(); replaced that warning with:
intel_bufmgr_gem.c: In function 'drm_i
From: Paulo Zanoni
We recently fixed a bug where it was impossible to do I2C transactions
on eDP panels when they were disabled. Now it should be possible to do
these transactions when the panel is disabled, but there's a race
condition that triggers dmesg errors if we try do do the I2C
transacti
From: Paulo Zanoni
These functions should help you checking for new Kernel error
messages. One of the problems I had while writing the runtime PM test
suite is that when you read the sysfs and debugfs files, the only way
to detect errors is by checking dmesg, so I was always getting SUCCESS
even
Thanks Patrik and Daniel. Since one of the customers was able to get the
Windows driver pass HDMI compliance, the hardware should be okay (or was worked
around :-)). We'll try to port the i915 intel_hdmi.c code over to CDV.
- Tushar
> > From what I've seen there are no real HDMI connectors o
Hi Ben,
I have drv_suspend running in a loop for a few hours now and I haven´t been
able to hit that problem. Could you give some more info? were you using piglit?
were you able to reproduce it systematically?
I did have to fix the test for my system, thought (the output of the serial
"cat" wa
On Mon, 2013-11-11 at 16:31 +0100, Daniel Vetter wrote:
> On Mon, Nov 11, 2013 at 02:58:31PM +, Siluvery, Arun wrote:
> > From: "Siluvery, Arun"
> >
> > This patchset contains changes for Timeout detection and recovery (TDR)
> > which
> > provides per-engine hang detection and recovery.
> >
On Mon, Nov 11, 2013 at 4:33 PM, Thomas Richter wrote:
> Now, how much is known about the register DSPARB, found at offset 0x70030?
>
> Because, if I just feed this register with "correct" values (for whatever
> "correct" means), I do get a stable image
> on pipe A and pipe B. I haven't found out
From: Oscar Mateo
Some shells do not understand "&>". For instance, my Ubuntu 12.04
machine has /bin/sh pointing to dash, which makes a mess out of
"&>" (to the point that the helper processes cannot be killed).
Signed-off-by: Oscar Mateo
---
tests/drv_suspend.c |4 ++--
1 file changed, 2
Am 08.11.2013 17:32, schrieb Daniel Vetter:
Kernel has a tool in scripts/checkpatch.pl which will tell you what's all
off ;-) Also sob line and similar essential things are missing, but the
script should notice this all.
Also I think it'd be good to extract this hack into a little helper
functio
On Mon, Nov 11, 2013 at 02:58:31PM +, Siluvery, Arun wrote:
> From: "Siluvery, Arun"
>
> This patchset contains changes for Timeout detection and recovery (TDR) which
> provides per-engine hang detection and recovery.
> The current driver performs full gpu reset in case of a hang, TDR attempt
On Mon, Nov 11, 2013 at 1:43 PM, Patrik Jakobsson
wrote:
> From what I've seen there are no real HDMI connectors on either Poulsbo or
> Cedarview. It's just DVI with HDMI connectors. Though you might know of other
> hardware that I don't.
>
> SDVO_CMD_GET_SUPP_ENCODE always fails on my SDVO chips
On Wed, Nov 06, 2013 at 11:26:07AM -0800, Ausmus, James wrote:
> On Wed, Nov 6, 2013 at 10:48 AM, Grant wrote:
> > Thank you, here's what I get:
> >
> > # addr2line -e /usr/lib64/xorg/modules/drivers/intel_drv.so -i 0x2fe79
> > 0x3037f
>
> Grant - I'm assuming that this was done
From: "Siluvery, Arun"
This patch adds changes to keep track of the number of the times TDR is
triggered and the results for each ring are made available through debugfs.
Signed-off-by: Siluvery, Arun
---
drivers/gpu/drm/i915/i915_debugfs.c | 62 +
drivers/g
From: "Siluvery, Arun"
TDR provides per-engine hang detection and recovery. If an engine hangs then
the TDR will attempt to reset the engine and advance the command streamer to
the next instruction in the ring. If it was in the middle of processing a
batch buffer then control returns to the instr
From: "Siluvery, Arun"
Instead of full GPU reset, where possible a single ring can be reset
individually. This patch adds functions to save ring's current state and
it will be restored with the same state after reset. The state comprises
of a set of ring specific registers. The actual hang detec
From: "Siluvery, Arun"
This patchset contains changes for Timeout detection and recovery (TDR) which
provides per-engine hang detection and recovery.
The current driver performs full gpu reset in case of a hang, TDR attempts to
only reset the engine that is hung and it falls back to full reset if
On Mon, Nov 11, 2013 at 6:57 AM, Gohad, Tushar wrote:
> Folks,
Hi
>From what I've seen there are no real HDMI connectors on either Poulsbo or
Cedarview. It's just DVI with HDMI connectors. Though you might know of other
hardware that I don't.
SDVO_CMD_GET_SUPP_ENCODE always fails on my SDVO chi
On 11/11/2013 02:20 PM, Thierry Reding wrote:
On Sat, Nov 09, 2013 at 11:28:16AM +0100, Daniel Vetter wrote:
On Sat, Nov 09, 2013 at 03:19:01PM +0530, Shobhit Kumar wrote:
Hi All -
These patches enhance the current support for MIPI DSI for Baytrail. They
continue on the sub-encoder design and a
On Fri, 08 Nov 2013, Daniel Vetter wrote:
> So I'd just go with adding a copy-pasted version of set/get/enable for
> broadwell. That should also fit in with Jani's plans for 3.14 with the
> complete backlight refactoring. Adding Jani so he can explain what he'd
> like.
I'd like
http://mid.gmane.o
On Wed, Nov 06, 2013 at 12:51:05PM +0200, Ville Syrjälä wrote:
> On Wed, Nov 06, 2013 at 02:36:35PM +0800, Chon Ming Lee wrote:
> > vlv_dpio_read/write should be describe more in PHY centric instead of
> > display controller centric.
> > Create a enum dpio_channel for channel index and enum dpio_ph
From: Ben Widawsky
Prior to Haswell the CPU control register for backlight
(BLC_PWM_CPU_CTL) toggled the PCH baclight pin for us. This made some
sense as there was no pin on the CPU. With Haswell came the introduction
of a CPU backlight pin, but the interface was still controlled by
software with
On Sat, Nov 09, 2013 at 11:28:16AM +0100, Daniel Vetter wrote:
> On Sat, Nov 09, 2013 at 03:19:01PM +0530, Shobhit Kumar wrote:
> > Hi All -
> > These patches enhance the current support for MIPI DSI for Baytrail. They
> > continue on the sub-encoder design and adds few more dev_ops to handle
> >
It's been 5 years since kms support was merged and roughly 4 years
since UMS support was ripped out from userspace drivers.
Thus far it's not been a big burden to keep the ums paths alive, and
we've made some good progress in better separating it from the kms
code by sprinkling DRIVER_MODESET chec
Thus far we've tried to carefully work around the fact that old
userspace relied on the AGP-backed legacy buffer mapping ioctls for a
bit too long. But it's really horribly, and now some new users for it
started to show up again:
http://www.mail-archive.com/mesa-dev@lists.freedesktop.org/msg45547.
Most platforms din't hit this condition, but if we want to allow
building without agp we should also make this allowed on gen3.
Cc: Ville Syrjälä
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/
Hi all,
Spurred by Ian's abuse of drmAgpSize I've figued it's time we accelerate the
demisse of the fake agp stuff and our ums code a bit. The idea is to send out
the same probe the radone guys have done and deprecate legacy stuff for now.
Then (presuming we don't get any reports from hurt users)
On Fri, 08 Nov 2013, Jani Nikula wrote:
> I've tested this so far on ILK and IVB, trying carefully keep it working
> commit by commit to keep things bisectable. More testing across
> platforms is very much needed. We have a history with backlight...
I've now tested this on PNV and SNB too, seems
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