Re: [Intel-gfx] [PATCH] drm/i915/bdw: PIPE_[BC] I[ME]R moved to powerwell

On Sat, Nov 09, 2013 at 10:13:21AM +0100, Daniel Vetter wrote: > On Fri, Nov 08, 2013 at 02:29:46PM -0800, Ben Widawsky wrote: > > The pipe B and pipe C interrupt mask and enable registers are now part > > of the pipe, so disabling the pipe power wells will lost the contests of > > the registers. >

Re: [Intel-gfx] [PATCH v2 0/7] drm/i915: Baytrail MIPI DSI support Updated

On Sat, Nov 09, 2013 at 03:19:01PM +0530, Shobhit Kumar wrote: > Hi All - > These patches enhance the current support for MIPI DSI for Baytrail. They > continue on the sub-encoder design and adds few more dev_ops to handle > sequence correctly. Major changes are - > > 1. DSI Clock calculation bas

[Intel-gfx] [PATCH v2 2/7] drm/i915: Use FLISDSI interface for band gap reset

Signed-off-by: Shobhit Kumar Signed-off-by: Yogesh Mohan Marimuthu Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/i915_drv.h |2 ++ drivers/gpu/drm/i915/i915_reg.h |1 + drivers/gpu/drm/i915/intel_dsi.c | 47 ++--- drivers/gpu/drm/i915/in

[Intel-gfx] [PATCH v2 7/7] drm/i915: Parametrize the dphy and other spec specific parameters

The values of these parameters will be different for differnet panel based on dsi rate, lane count, etc. Remove the hardcodings and make these as parameters whch will be initialized in panel specific sub-encoder implementaion. This will also form groundwork for planned generic panel sub-encoder im

[Intel-gfx] [PATCH v2 3/7] drm/i915: Compute dsi_clk from pixel clock

Pixel clock based calculation is recommended in the MIPI host controller documentation v2: Based on review comments from Jani and Ville - Use dsi_clk in KHz rather than converting in Hz and back to MHz - RR formula is retained though not used but return dsi_clk in KHz now - Moved the m

[Intel-gfx] [PATCH v2 6/7] drm/i915: Remove redundant DSI PLL enabling

DSI PLL will get configured during crtc_enable using ->pre_pll_enable and no need to do in ->mode_set Signed-off-by: Shobhit Kumar --- drivers/gpu/drm/i915/intel_dsi.c |3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c ind

[Intel-gfx] [PATCH v2 5/7] drm/i915: Reorganize the DSI enable/disable sequence

Basically ULPS handling during enable/disable has been moved to pre_enable and post_disable phases. PLL and panel power disable also has been moved to post_disable phase. The ULPS entry/exit sequneces as suggested by HW team is as follows - During enable time - set DEVICE_READY --> Clear DEVICE_RE

[Intel-gfx] [PATCH v2 1/7] drm/i915: Add more dev ops for MIPI sub encoder

Some panels require one time programming if they do not contain their own eeprom for basic register initialization. The sequence is Panel Reset --> Send OTP --> Enable Pixel Stream --> Enable the panel v2: Based on review comments from Jani and Ville - Updated the commit message with more det

[Intel-gfx] [PATCH v2 4/7] drm/i915: Try harder to get best m, n, p values with minimal error

Basically check for both +ive and -ive deviation from target clock and pick the one with minimal error. If we get a direct match, break from loop to acheive some optimization. Signed-off-by: Vijayakumar Balakrishnan Signed-off-by: Shobhit Kumar --- drivers/gpu/drm/i915/intel_dsi_pll.c | 26 ++

[Intel-gfx] [PATCH v2 0/7] drm/i915: Baytrail MIPI DSI support Updated

Hi All - These patches enhance the current support for MIPI DSI for Baytrail. They continue on the sub-encoder design and adds few more dev_ops to handle sequence correctly. Major changes are - 1. DSI Clock calculation based on pixel clock 2. Add new dev_ops for better sequencing the enable/disab

Re: [Intel-gfx] [PATCH] drm/i915/bdw: PIPE_[BC] I[ME]R moved to powerwell

On Fri, Nov 08, 2013 at 02:29:46PM -0800, Ben Widawsky wrote: > The pipe B and pipe C interrupt mask and enable registers are now part > of the pipe, so disabling the pipe power wells will lost the contests of > the registers. > > Art totally debugged this one! > > Cc: Art Runyan > Cc: Paulo Zan