GEN8 also needs this workaround.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_pm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index caf31b7..68dc363 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/driv
From: Ben Widawsky
Wa???
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9608f96..2d16363 100644
--- a/drivers/g
From: Paulo Zanoni
They're not the same as the Haswell ones.
Reviewed-by: Art Runyan
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h | 11 +
drivers/gpu/drm/i915/intel_dp.c | 55 ++---
2 files changed, 63 insertions(+), 3 deletions(-
From: Ben Widawsky
Hold vertex data in cache until last reference
BDW-A workaround
? BUG
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_pm.c | 3 +++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/g
From: Ben Widawsky
BDW-A workaround.
BDW Bug #1899812
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8080a4d..
From: Paulo Zanoni
v2: Rebased onto Paulo's MHz->kHz change.
v3: Rebased on top of the Haswell pc8+ adjustements.
Reviewed-by: Jani Nikula
Signed-off-by: Paulo Zanoni (v1)
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_ddi.c | 25 +
From: Ville Syrjälä
Route cursor and sprite data through the pipe CSC unit on BDW.
Primary plane data is already sent through the pipe CSC.
Signed-off-by: Ville Syrjälä
Reviewed-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_sprite.c | 2 +-
2 fi
The current formula we use for HSW is not what is in current docs.
However, changing to the HSW formula on my HSW does not improve power
usage, and decreases performance by about 5% in limited xonotic testing.
For gen8, until we know otherwise, or run experiments, let's use
the HSW formula - which
From: Paulo Zanoni
For now it's just equivalent to IS_GEN8, but in the future we might
want to change that (e.g., on Gen 7 we have IS_VALLEYVIEW,
IS_IVYBRIDGE and IS_HASWELL).
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/dr
From: Damien Lespiau
Just like HSW.
This means we can scan out a mode with a 300Mhz pixel clock with a depth
of 24 bits, but only a 200Mhz one with a 36bits depth.
Signed-off-by: Damien Lespiau
Reviewed-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
1 file changed, 1 insertio
From: Paulo Zanoni
So treat it like Haswell.
Reviewed-by: Art Runyan
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 193c
This implements a workaround for PSR dealing with some vblank issue.
WaPsrDPAMaskVBlankInSRD && WaPsrDPRSUnmaskVBlankInSRD
v2: forgot to git add bogus whitespace fix
v3: Update with workaround names.
Use for_each_pipe() and CHICKEN_PIPESL_1(pipe) macro (Ville)
Cc: Art Runyan
Signed-off-by: Ben
It's no longer a required workaround on BDW.
Signed-off-by: Ben Widawsky
[danvet: Move compile fix from a later patch to this one.]
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_uncore.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/int
From: Art Runyan
Many of the DDI buffer translation values have changed for BDW.
Add new translation tables and selection between HSW and BDW.
v2: s/BUG/WARN/ to avoid breaking future GENs.
v3: Rebase on top of the hdmi translation table changes.
Signed-off-by: Art Runyan (v2)
Signed-off-by:
From: Paulo Zanoni
The platforms we currently have all have LPT LP on them. As such, we
have no way to identify the new WPT PCH that will ship with Broadwell.
NOTE: For all purposes relevant to the driver that this point, LPT and
WPT are equivalent. Therefore there should be no need to actually
From: Ville Syrjälä
Broadwell has bigger display FIFOs than Haswell. Otherwise the
two are very similar.
v2: Fix FBC WM_LP shift for BDW
v3: Rebase on top of the big Haswell wm rework.
Signed-off-by: Ville Syrjälä (v2)
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
BDW caching works differently than the previous generations. Instead of
having bits in the PTE which directly control how the page is cached,
the 3 PTE bits PWT PCD and PAT provide an index into a PAT defined by
register 0x40e0. This style of caching is functionally equivalent to how
it works on HS
Broadwell PSR support is a superset of Haswell. With this simple
register base calculation, everything that worked on HSW for eDP PSR
should work on BDW.
Note that Broadwell provides additional PSR support. This is not
addressed at this time.
v2: Make the HAS_PSR include BDW
v3: Use the correct
From: Ben Widawsky
BDW-A workaround
BDW Bug #1899155
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3ae3751..
v2: Squash in fixup from Ben to synchronize the GT mailbox commands.
CC: Art Runyan
Reviewed-by: Art Runyan
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 36 +
This is mostly what we have for HSW with the exceptions of:
no writes:
GEN6_RC1_WAKE_RATE_LIMIT
GEN6_RC6pp_WAKE_RATE_LIMIT
GEN6_RC1e_THRESHOLD
GEN6_RC6p_THRESHOLD
GEN6_RC6pp_THRESHOLD
GEN6_RP_DOWN_TIMEOUT - use 1s instead of 1.28s
Don't try to overclock, or program ring/IA frequency tab
From: Ben Widawsky
Implement WaSingleSubspanDispatchOnAALinesAndPoints
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.
PIPE_CONTROL added the high address dword. I'm not sure how the
simulator let me get away with this. I've explicitly left out all the
workarounds from Gen7 because in the minimal digging that I did, most
don't seem necessary, and the simulator doesn't complain without them
Note that BLT and BSD ri
From: Ben Widawsky
BDW-A workaround
BDW Bug #1899532
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 2 ++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2d16363.
From: Ben Widawsky
We've done insufficient testing on them thus far, so keep them disabled
until we do test.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv
From: Paulo Zanoni
So you can use the panel fitter while the power well is disabled and
you also don't need to set the "pipe" bit.
v2: Rebased on top of Jesse's pfit refactor, which moved pfit state
into the pipe_config.
v3: Rebase on top of the latest Haswell/panel fitter rework, which
neatly
From: Paulo Zanoni
Use the eDP values on platforms where port D is eDP. This doesn't
affect Haswell since it uses the same DDI buffer values for eDP and
DP.
Reviewed-by: Art Runyan
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_ddi.c | 7 ++-
1 file changed, 6 insertions(+), 1
All the gen8 debugfs stuff I wasn't too lazy to update. We'll need more
later, I am certain.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_debugfs.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i
Probing gen8 is similar to gen6. To make the code cleaner and more
maintainable however we can use the probe functions to split it out.
v2: Rebased on top of update gtt probe infrastructure.
v3: Rebased on top of Kenneth' Graunke's ->pte_encode refactoring.
V4: Resolve conflicts with Ben's lates
From: Ville Syrjälä
v2: Resolve rebase conflicts and switch to gen < 8 color for GenX
checking.
v3: Rebase on top of the address space refactoring.
Reviewed-by: Ben Widawsky
Signed-off-by: Ville Syrjälä (v1)
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ++-
1 fil
The upcoming clear and insert routines will expect that PDEs all point
to valid Page Directories. Doing that lazily doesn't really buy us
anything.
The page allocation is done regardless earlier in init so it shouldn't
hurt set the PDEs.
v2: Squash in patches to implement fixed PDE write function
v2: Squash in fix from Ben: Set PPGTT batches as necessary
This fixes the regression in the last couple of days when we enabled
PPGTT.
v3: Squash in fixup to still use GTT for secure batches from Ville:
BDW doesn't have a separate secure vs. non-secure bit in
MI_BATCH_BUFFER_START. So for secure
The command to emit batch buffers has changed to address 48b addresses.
It seemed reasonable that we could still use the old instruction where
emitting 0 for length would do the right thing, but it seems to bother
the simulator when the code does that.
Now the second dword in the command has the u
Aside from the potential size increase of the PPGTT, the primary
difference from previous hardware is the Page Directories are no longer
carved out of the Global GTT.
Note that the PDE allocation is done as a 8MB contiguous allocation,
this needs to be eventually fixed (since driver reloading will
The code is more verbose than necessary for the reader's sake, hopefully
the compiler optimizes away the if.
Reviewed-by: Ville Syrjälä
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 22 ++
1 file changed, 18 insertions(+), 4 deletions(-)
diff --g
Legacy PPGTT on GEN8 requires programming 4 PDP registers per ring.
Since all rings are using the same address space with the current code
the logic is simply to program all the tables we've setup for the PPGTT.
v2: Turn on PPGTT in GFX_MODE
v3: v2 was the wrong patch
v4: Resolve conflicts due t
It's not so much that the information is terribly useful, but rather
that the gen6/7 information is completely useless.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_debugfs.c | 49 +++--
1 file changed, 42 insertions(+), 7 deletions(-)
diff --git a/d
From: Paulo Zanoni
Just make Broadwell follow the same code paths as Haswell here,
instead of running code for the even-older platforms.
v2: Shuffle around Ben's vma prep work.
Reviewed-by: Ville Syrjälä
Signed-off-by: Paulo Zanoni (v1)
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/
GEN8 PPGTT range clearing is very similar to GEN6 if we assume that our
PDEs are all valid, which they should be.
v2: Rebase on top of the address space refactoring.
v3: Rebase on top of the bool use_scratch addition to the clear_range interface.
Reviewed-by: Imre Deak
Signed-off-by: Ben Widaws
Implements WaVSRefCountFullforceMissDisable
Implements WaDSRefCountFullforceMissDisable
v2: Rebased on the HSW patch (which fixed the bug from v1)
commit 41c0b3a88c7bae96d8e2ee60c7ed91f57fd152d7
Author: Ben Widawsky
Date: Sat Jan 26 11:52:00 2013 -0800
drm/i915: Implement WaVSRefCountFullf
Just enough to make the code not barf...
Init BDW display to look like HSW. For the simulator this should be
fine, but this will probably require more work.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_display.c | 3 ++-
drivers/gpu/drm/i915/intel_sprite.c | 1 +
2 files changed,
GEN8 insertion is very similar to GEN6.
v2: Rebase on top of Imre's for_each_sg_page helpers.
v3: Fixup my conversion (spotted by Ville).
v4: Rebase on top of the address space refactoring.
Signed-off-by: Ben Widawsky (v1)
Reviewed-by: Imre Deak
Signed-off-by: Daniel Vetter
---
drivers/gpu/
From: Paulo Zanoni
Broadwell has different DDI buffer translations for eDP and DP, so add
support for the missing eDP and keep Haswell the same.
A future patch addresses the suggestion from Art to check for eDP on
port D and use the eDP values there, too.
Reviewed-by: Art Runyan
Signed-off-by:
From: Paulo Zanoni
And it inherits some bits from the previous TRANS_CONF (aka PIPE_CONF
on previous gens).
v2: Rebase on to of the pipe config bpp handling rework.
v3: Rebased on top of the pipe_config->dither refactoring.
v4: Drop the read-modify-write cycle for PIPEMISC, similarly to how we
v2: Add missed ring interrupt info
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_debugfs.c | 50 +++--
1 file changed, 48 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 5c45e
BDW context sizes varies a bit.
v2: Squash in fixup for the hw context size from Ben.
Signed-off-by: Ben Widawsky (v1)
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_gem_context.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 6 insertions(+)
diff --git
With gen6 PTE type in place, pave the way for the new gen8 type.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c6d38d0..8bf
From: Paulo Zanoni
Just like Haswell, but with the small twist that the panel fitter for pipe A is
now also in the always-on power well.
v2: Use the new HAS_POWER_WELL macro.
v3: Rebase on top of intel_using_power_well patches.
v4: This time actually update the PFIT check correctly so that the
With the PTE clarifications, the bind and clear functions can now be
added for gen8.
v2: Use for_each_sg_pages in gen8_ggtt_insert_entries.
v3: Drop dev argument to pte encode functions, upstream lost it. Also
rebase on top of the scratch page movement.
v4: Rebase on top of the new address space
This was an oversight and should have been in a previous series
somewhere.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem.c | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 5be1a15..12bbd5e 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++
It is my honor and privilege to submit basic Broadwell support on behalf
of Intel.
The patch series includes support for Broadwell which should bring it up
to feature parity with Haswell. As you'll note, the patches have
received some revisions and review already. This is due to our new
process (m
v2: Squash in "drm/i915/bdw: Add BDW to the HAS_DDI check" as
suggested by Damien.
v3: Squash in VEBOX enabling from Zhao Yakui
v4: Rebase on top of Jesse's patch to extract all pci ids to
include/drm/i915_pciids.h.
v4: Replace Halo by its marketing moniker Iris. Requested by Ben.
v5: Switch
No PCI ids yet, so nothing should happen.
Rebase-Note: This one needs replacement ;-)
Signed-off-by: Ben Widawsky
Reviewed-by: Damien Lespiau
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.
Reviewed-by: Ville Syrjälä
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem.c | 1 +
drivers/gpu/drm/i915/i915_gpu_error.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e7b39d7..5be1a15 100644
---
We don't actually return any to userspace yet, however we can pretend
like we do now so userspace will support it when it happens.
This is just to please Chris as the code itself isn't ready for > 64b
relocations.
v2: Rebase on top of the refactored relocate_entry_gtt|cpu functions.
v3: Squash i
Clock gating init is really a catch all function for registers we need
to write early in loading the driver.
Atm just the bare metal stuff we need, more will surely come.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_pm.c | 11 +++
1 file changed, 11 insertions(+)
diff --g
From: Damien Lespiau
v2: Rebase (Paulo Zanoni)
v3: Rebase on top of num_pipes having moved to intel_device_info.
Signed-off-by: Damien Lespiau (v1)
Signed-off-by: Paulo Zanoni (v2)
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_drv.c | 4 ++--
1 file changed, 2 insertions(+), 2
From: Daniel Vetter
This will be changed once the gen8 code is fully implemented.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c4c42e7.
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way i
All the BARs have the ability to grow.
v2: Pulled out the simulator workaround to a separate patch.
Rebased.
v3: Rebase onto latest vlv patches from Jesse.
v4: Rebased on top of the early stolen quirk patch from Jesse.
Cc: Ingo Molnar
Cc: H. Peter Anvin
Signed-off-by: Ben Widawsky (v2)
Signe
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gpu_error.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 3d01eae..a55ebe8 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/
GEN8 removes the GT FIFO which we've all come to know and love. Instead
it offers a wider range of optimized registers which always keep a
shadowed copy, and are fed to the GPU when it wakes.
How this is implemented in hardware is still somewhat of a mystery. As
far as I can tell, the basic design
On Fri, Nov 01, 2013 at 05:02:52PM -0700, Ben Widawsky wrote:
> On Sandybridge we must set the "PPGTT Render Target Base Address Valid
> for FBC" bit as noted in the programming guide. We did this at clock
> gating init. Thisbit is not saved and restored with RC6 power context,
> so the resetting i
El 01/11/13 17:20, Daniel Vetter escribió:
Ok, gpu hang. Unfortunately this particular kernel doesn't bother to
dump the hang state in this case, so can you please test with the
latest drm-intel-nightly branch from
http://cgit.freedesktop.org/~danvet/drm-intel/
Dmesg should politely tell you t
El 01/11/13 19:18, Daniel Vetter escribió:
Wut, that was not the expected response. Just to check: You didn't
upgrade any userspace drivers at the same time?
No, userspace side remains the same (xf86-video-intel 2.99.905)
Otherwise can you please attempt a reverse bisect so that we can find
On Sat, Nov 02, 2013 at 10:49:32AM -0200, Rodrigo Vivi wrote:
> On Fri, Nov 1, 2013 at 8:39 AM, Chris Wilson wrote:
> > On Thu, Oct 31, 2013 at 09:07:09PM -0200, Rodrigo Vivi wrote:
> >> If Userspace isn't using MI_PREDICATE all slices must be enabled for
> >> backward compatibility.
> >>
> >> If
On Fri, Nov 1, 2013 at 8:39 AM, Chris Wilson wrote:
> On Thu, Oct 31, 2013 at 09:07:09PM -0200, Rodrigo Vivi wrote:
>> If Userspace isn't using MI_PREDICATE all slices must be enabled for
>> backward compatibility.
>>
>> If I915_EXEC_USE_PREDICATE isn't set and defaul is set to half, kernel will
On Fri, Nov 1, 2013 at 5:56 PM, Daniel Vetter wrote:
> So here's my idea to solve this for real:
> - split long-term pinned objects into two classes: Those that might
> need to be access through the mappable gtt mmio window (like scanout
> buffers) and those that don't (like hw contexts).
> - Pin
Signed-off-by: Daniel Vetter
---
tests/Makefile.am | 6 ++---
tests/NAMING-CONVENTION | 2 ++
tests/core_getclient.c | 61 +
tests/core_getstats.c | 50
tests/core_getversion.c | 49 +++
I was a bit on the fence about the basic pipe CRC test since that
doesn't really test kms, but debug infrastructure in debugfs.
Otoh running this one for a full kms testrun is always good, to make
sure that all the other (real) CRC based tests work sanely.
Signed-off-by: Daniel Vetter
---
tests
Hi all,
Spurred by the ongoing discussions about improving our tests I've started to
document some of the naming patterns a bit. I've also added a few new ones and
renamed a bunch of tests.
The idea is that developers can use this patterns to construct add-hoc test
groups with piglit's -t/-x opti
Just a start and we need more work here. Some follow-up patches will
clear up some of the historical confusion.
While at it rename the pc8 "basic" test to "rte".
Signed-off-by: Daniel Vetter
---
README | 3 +++
tests/NAMING-CONVENTION | 56 +
Signed-off-by: Daniel Vetter
---
tests/.gitignore | 2 +-
tests/Makefile.am | 10 +--
tests/NAMING-CONVENTION | 2 +
tests/ZZ_hangman | 70 ---
tests/ZZ_missed_irq | 72 ---
tests/debugfs_reader | 9 ---
tests/drv_deb
On Fri, Nov 01, 2013 at 05:02:52PM -0700, Ben Widawsky wrote:
> On Sandybridge we must set the "PPGTT Render Target Base Address Valid
> for FBC" bit as noted in the programming guide. We did this at clock
> gating init. Thisbit is not saved and restored with RC6 power context,
> so the resetting i
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