If Userspace isn't using MI_PREDICATE all slices must be enabled for
backward compatibility.
If I915_EXEC_USE_PREDICATE isn't set and defaul is set to half, kernel will
force
all slices on.
v2: fix the inverted logic for backwards compatibility
USE_PREDICATE unset force gt_full when defaul i
On gmch platforms the normal pipe source CRC registers don't work for
DP and TV encoders. And on newer platforms the single pipe CRC has
been replaced by a set of CRC at different stages in the platform.
Now most of our userspace tests don't care one bit about the exact
CRC, they simply want somet
Hi Jani,
Applied this patchset to danvet/drm-intel-next-queued and did a quick test
on VLV2 with mutter. Tested eDP + VGA hotplug, test failed.
Hot-plugging VGA with eDP active resulted in the eDP's backlight being
kicked off. Then, after unplugging and replugging, the eDP backlight returned.
Ru
On Thu, Oct 31, 2013 at 9:14 PM, Paulo Zanoni wrote:
> 2013/8/28 Daniel Vetter :
>> We already have a big splashing *ERROR* for all the relevant cases of
>> hangs, so this one here is redudant. And it results in an unclean
>> dmesg when running with simulated hangs. Regression has been
>> introduc
Hi
2013/8/28 Daniel Vetter :
> We already have a big splashing *ERROR* for all the relevant cases of
> hangs, so this one here is redudant. And it results in an unclean
> dmesg when running with simulated hangs. Regression has been
> introduced in
Bug https://bugs.freedesktop.org/show_bug.cgi?id=
From: Jeff McGee
Hello all,
Posting my first patch to the list. I have tested this fix on Android
kernel 3.9.1 and only compile-checked on drm-intel-nightly. I have
reviewed the changes to reset and rps/rc6 stuff and believe there
should be no hidden gotchas.
As I hope this to be the first of m
From: Jeff McGee
A check of rps/rc6 state after i915_reset determined that the ring
MAX_IDLE registers were returned to their hardware defaults and that
the GEN6_PMIMR register was set to mask all interrupts. This change
restores those values to their pre-reset states by re-initializing
rps/rc6 i
On Thu, Oct 31, 2013 at 10:18:00AM -0700, Jesse Barnes wrote:
> On Thu, 31 Oct 2013 18:46:22 +0200
> ville.syrj...@linux.intel.com wrote:
>
> > From: Ville Syrjälä
> >
> > On VLV both ports B and C can support either DP or eDP. Try to
> > initialize eDP first on each port, and if that fails fall
On Thu, 31 Oct 2013 18:46:22 +0200
ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> On VLV both ports B and C can support either DP or eDP. Try to
> initialize eDP first on each port, and if that fails fall back to
> regular DP connector.
>
> intel_dp_init_typed() is now like the
On Thu, Oct 31, 2013 at 1:01 PM, Jani Nikula
wrote:
> On Thu, 31 Oct 2013, Josh Boyer wrote:
>> On Thu, Oct 31, 2013 at 10:58 AM, Jani Nikula
>> wrote:
>>> On Fri, 25 Oct 2013, Joseph Salisbury
>>> wrote:
On 10/16/2013 05:02 PM, Daniel Vetter wrote:
> It's by far not that simple. Jani
On Thu, 31 Oct 2013, Josh Boyer wrote:
> On Thu, Oct 31, 2013 at 10:58 AM, Jani Nikula
> wrote:
>> On Fri, 25 Oct 2013, Joseph Salisbury wrote:
>>> On 10/16/2013 05:02 PM, Daniel Vetter wrote:
It's by far not that simple. Jani is working on both the underlying bug
and a better w/a. See
Hi all -
I was going to pick up [1], rebase, add a few small things on top. I
forget what those small things were going to be, but I ended up with
per-connector backlight handling and chip specific backlight hooks. Oh
well.
This is still completely untested. I tried to be careful with each
change
The backlight code has grown rather hairy, not least because the
hardware registers and bits have repeatedly been shuffled around. And
this isn't expected to get any easier with new hardware. Make things
easier for our (read: my) poor brains, and split the code up into chip
specific functions.
The
ALthough usually there's only one connector that supports backlight,
this also finds the correct connector. Before, we only updated the
connector on pipe A, which might not be the one with backlight. (This
only made a difference on BYT.)
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_
I've always felt the backlight device conditional build has been all
backwards. Make it feel right.
Gently move things towards connector based stuff while at it.
There should be no functional changes, except for a slight
reordering/interleaving of connector backlight and sysfs destroy calls.
Sig
Move from dev_priv to connector->panel.
We still don't allow multiple sysfs interfaces, though.
There should be no functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_dma.c |2 +-
drivers/gpu/drm/i915/i915_drv.h |9 +---
drivers/gpu/drm/i915/i915_suspen
From: Jesse Barnes
On VLV/BYT, backlight controls a per-pipe, so when adjusting the
backlight we need to pass the correct info. So make the externally
visible backlight functions take a connector argument, which can be used
internally to figure out the pipe backlight to adjust.
v2: make connect
Doing this has been long overdue anyway, but now we really need it in
preparation for per connector backlight handling.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/intel_opregion.c | 20 ++--
2 files changed, 19 insertions
From: Jesse Barnes
With the connector and pipe passed around, we can now set the backlight
on the right pipe on VLV/BYT.
v2: drop combination mode check for VLV (Jani)
add save/restore code for VLV backlight regs (Jani)
check for existing modulation freq when initializing backlight regs
On Thu, Oct 31, 2013 at 10:58 AM, Jani Nikula
wrote:
> On Fri, 25 Oct 2013, Joseph Salisbury wrote:
>> On 10/16/2013 05:02 PM, Daniel Vetter wrote:
>>> It's by far not that simple. Jani is working on both the underlying bug
>>> and a better w/a. See
>>>
>>> https://bugzilla.kernel.org/show_bug.cg
From: Ville Syrjälä
On VLV both ports B and C can support either DP or eDP. Try to
initialize eDP first on each port, and if that fails fall back to
regular DP connector.
intel_dp_init_typed() is now like the old intel_dp_init, except you pass
in the connector type. If you pass DRM_MODE_CONNECTO
Please do not top-post.
On Thu, Oct 31, 2013 at 04:52:54PM +0100, emanoil.kot...@fincom.at wrote:
> Hi, thanks for swift response.
> Yes, without those modules loaded it hangs as well. Perhaps I did
> not understand you well - do you mean unloaded or not
> compiled/installed, or even blacklisted.
On 10/31/2013 10:58 AM, Jani Nikula wrote:
> On Fri, 25 Oct 2013, Joseph Salisbury wrote:
>> On 10/16/2013 05:02 PM, Daniel Vetter wrote:
>>> It's by far not that simple. Jani is working on both the underlying bug
>>> and a better w/a. See
>>>
>>> https://bugzilla.kernel.org/show_bug.cgi?id=59841
On gmch platforms the normal pipe source CRC registers don't work for
DP and TV encoders. And on newer platforms the single pipe CRC has
been replaced by a set of CRC at different stages in the platform.
Now most of our userspace tests don't care one bit about the exact
CRC, they simply want somet
On Thu, Oct 31, 2013 at 01:37:26PM -0200, Paulo Zanoni wrote:
> 2013/10/29 Imre Deak :
> > In
> >
> > commit 6efdf354ddb186c6604d1692075421e8d2c740e9
> > Author: Imre Deak
> > Date: Wed Oct 16 17:25:52 2013 +0300
> >
> > the check for i915_disable_power_well flag was removed by overlook,
> > so
Requested by Paulo.
Signed-off-by: Daniel Vetter
---
tests/.gitignore | 1 +
tests/Makefile.am | 1 +
tests/template.c | 80 +++
3 files changed, 82 insertions(+)
create mode 100644 tests/template.c
diff --git a/tests/.gitignore b/tests/.
Most callers didn't bother checking, so just move the asserts into
the function itself.
Signed-off-by: Daniel Vetter
---
lib/drmtest.c | 15 +++
lib/drmtest.h | 2 +-
lib/igt_debugfs.c | 2 +-
tests/.gitignore | 1 +
tests/kms_flip.c | 2 +-
5 files changed, 11 insertio
All tests agree that this is a letal failure, so no point
to pass it back to callers.
Also add some igt_require calls for the drm_fd where I've
noticed that it's missing.
Signed-off-by: Daniel Vetter
---
lib/drmtest.c| 7 +++
lib/drmtest.h| 2 +-
tests/debugfs_pipe_c
2013/10/31 Imre Deak :
> On Wed, 2013-10-30 at 19:40 -0200, Paulo Zanoni wrote:
>> From: Paulo Zanoni
>>
>> In the current code, at haswell_modeset_global_resources, first we
>> decide if we want to enable/disable the power well, then we decide if
>> we want to enable/disable PC8. On the case wher
2013/10/29 Imre Deak :
> In
>
> commit 6efdf354ddb186c6604d1692075421e8d2c740e9
> Author: Imre Deak
> Date: Wed Oct 16 17:25:52 2013 +0300
>
> the check for i915_disable_power_well flag was removed by overlook,
> so add it back now.
>
> Reported-by: Paulo Zanoni
> Signed-off-by: Imre Deak
Rev
Cc: Ville Syrjälä
Signed-off-by: Daniel Vetter
---
tests/kms_cursor_crc.c | 29 +
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/tests/kms_cursor_crc.c b/tests/kms_cursor_crc.c
index 55b9b7c..cddfe10 100644
--- a/tests/kms_cursor_crc.c
+++ b/tests/kms
No need to sprinkle this all over:
- exit handlers will only be registered once
- they're always called when exiting, so no need to explictly call
them.
This allows us to hide all the pipe crc cleanup in the library.
Cc: Damien Lespiau
Signed-off-by: Daniel Vetter
---
lib/igt_debugfs.c
In the past new testcases with subtest often forgot to add the call to
igt_exit at the end of their main() function. That is now caught with
a bit more obnoxious asserts, but it's still a nuissance.
This little igt_main macro takes care of that (and also of calling the
subtest machinery initializa
On Fri, 25 Oct 2013, Joseph Salisbury wrote:
> On 10/16/2013 05:02 PM, Daniel Vetter wrote:
>> It's by far not that simple. Jani is working on both the underlying bug
>> and a better w/a. See
>>
>> https://bugzilla.kernel.org/show_bug.cgi?id=59841
>>
>> for the full story in its entire glory.
>>
>
On Thu, 31 Oct 2013, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> That explains why I was seeing 2 consecutive "Turning eDP VDD off"
> messages.
>
> Regression introduced by:
> commit bf13e81b904a37d94d83dd6c3b53a147719a3ead
> Author: Jani Nikula
> Date: Fri Sep 6 07:40:05 2013 +03
Makes stuff work on DP ports on gmch platforms automatically.
Cc: Damien Lespiau
Signed-off-by: Daniel Vetter
---
lib/igt_debugfs.c| 3 ++-
lib/igt_debugfs.h| 1 +
tests/debugfs_pipe_crc.c | 11 +++
tests/kms_cursor_crc.c | 12 ++--
4 files changed, 8 inserti
Otherwise the automagic skipping for DP ports on gmch platforms
won't work.
v2: We also need to just skip that connector, not the entire subtest.
kms_cursor_crc still needs to be updated.
Cc: Damien Lespiau
Cc: Ville Syrjälä
Signed-off-by: Daniel Vetter
---
tests/debugfs_pipe_crc.c | 8 +
Otherwise the automagic skipping for DP ports on gmch platforms
won't work.
v2: We also need to just skip that connector, not the entire subtest.
Signed-off-by: Daniel Vetter
---
tests/debugfs_pipe_crc.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/tests/debugfs_p
From: Paulo Zanoni
That explains why I was seeing 2 consecutive "Turning eDP VDD off"
messages.
Regression introduced by:
commit bf13e81b904a37d94d83dd6c3b53a147719a3ead
Author: Jani Nikula
Date: Fri Sep 6 07:40:05 2013 +0300
drm/i915: add support for per-pipe power sequen
Adding intel-gfx@ to CC.
On Thu, Oct 31, 2013 at 03:00:24PM +0100, emanoil.kot...@fincom.at wrote:
> Hi again, just noticed that it happens also without starring at
> youtube, but again in the drm
Right, I can see a bunch of #GPs happening at
drivers/gpu/drm/i915/intel_display.c:8292 check_crtc_
On Thu, Oct 31, 2013 at 1:46 PM, Jani Nikula
wrote:
> On Thu, 31 Oct 2013, Daniel Vetter wrote:
>> On Wed, Oct 30, 2013 at 07:50:28PM -0200, Paulo Zanoni wrote:
>>> From: Paulo Zanoni
>>>
>>> After I reorganized the panel VDD debug messages I was able to spot we
>>> were disabling it one extra t
On Thu, Oct 31, 2013 at 02:30:34PM +0200, Jani Nikula wrote:
> On Thu, 31 Oct 2013, Antti Koskipää wrote:
> > On 10/31/13 09:32, Jani Nikula wrote:
> >> On Wed, 30 Oct 2013, Antti Koskipaa wrote:
> >>> Upcoming hardware will not have the various display pipe register
> >>> ranges evenly spaced in
2013/10/31 Jani Nikula :
> On Thu, 31 Oct 2013, Daniel Vetter wrote:
>> On Wed, Oct 30, 2013 at 07:50:28PM -0200, Paulo Zanoni wrote:
>>> From: Paulo Zanoni
>>>
>>> After I reorganized the panel VDD debug messages I was able to spot we
>>> were disabling it one extra time. The problem is that we'
On Thu, 31 Oct 2013, Daniel Vetter wrote:
> On Wed, Oct 30, 2013 at 07:50:28PM -0200, Paulo Zanoni wrote:
>> From: Paulo Zanoni
>>
>> After I reorganized the panel VDD debug messages I was able to spot we
>> were disabling it one extra time. The problem is that we're missing
>> the call to cance
On Wed, 2013-10-30 at 19:40 -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> In the current code, at haswell_modeset_global_resources, first we
> decide if we want to enable/disable the power well, then we decide if
> we want to enable/disable PC8. On the case where we're enabling PC8
> this w
On Thu, 31 Oct 2013, Antti Koskipää wrote:
> On 10/31/13 09:32, Jani Nikula wrote:
>> On Wed, 30 Oct 2013, Antti Koskipaa wrote:
>>> Upcoming hardware will not have the various display pipe register
>>> ranges evenly spaced in memory. Change register address calculations
>>> into array lookups.
>
On Thu, Oct 31, 2013 at 12:15:17PM +, Ramakutty, SandeepX wrote:
> Hi Ville ,
>
> Thanks for the feedback.
>
> We verified without updating watermarks and found that the video playback,
> 3DMark and GLBenchmark plays fine. There was no underrun error too.
> Cases tried out-
> Pixel format ch
On Wed, Oct 30, 2013 at 11:11:17AM +0800, Chon Ming Lee wrote:
> vlv_dpio_read/write should be describe more in PHY centric instead of
> display controller centric.
> Create a enum dpio_channel for channel index and enum dpio_phy for PHY
> index. This should better to gather for upcoming platform.
Hi Ville ,
Thanks for the feedback.
We verified without updating watermarks and found that the video playback,
3DMark and GLBenchmark plays fine. There was no underrun error too.
Cases tried out-
Pixel format changed to 32BPP when water mark calculated based on 16BPP
Pixel format changed to 16BP
On Thu, Oct 31, 2013 at 01:46:31PM +0200, Ville Syrjälä wrote:
> On Wed, Oct 30, 2013 at 10:05:19AM +0800, Chon Ming Lee wrote:
> > Incorrect definition DPIO_TX3_SWING_CTL4.
> >
> > Signed-off-by: Chon Ming Lee
>
> Reviewed-by: Ville Syrjälä
Queued for -next, thanks for the patch.
> Based on
On Wed, Oct 30, 2013 at 10:05:19AM +0800, Chon Ming Lee wrote:
> Incorrect definition DPIO_TX3_SWING_CTL4.
>
> Signed-off-by: Chon Ming Lee
Reviewed-by: Ville Syrjälä
Based on the specs, the typo meant that HDMI B ended up using
"incorrect" de-emphasis for the TMDS data lanes.
> ---
> driver
On Wed, Oct 30, 2013 at 07:50:28PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> After I reorganized the panel VDD debug messages I was able to spot we
> were disabling it one extra time. The problem is that we're missing
> the call to cancel the delayed work in one of the instances where w
On 10/31/13 09:32, Jani Nikula wrote:
> On Wed, 30 Oct 2013, Antti Koskipaa wrote:
>> Upcoming hardware will not have the various display pipe register
>> ranges evenly spaced in memory. Change register address calculations
>> into array lookups.
>>
>> Tested on SandyBridge.
>>
>> I left the UMS c
On Thu, Oct 31, 2013 at 10:15 AM, Ville Syrjälä
wrote:
> On Thu, Oct 31, 2013 at 09:33:24AM +0800, feng xiangjun wrote:
>> Hello, ville.
>>
>> Latest git commit 7195a50b5c7e00cc3312934fd022c3006b533d12 introduced a
>> warning,
>>
>> +
>> +static void intel_crt_get_config(struct intel_encoder *enc
On Thu, Oct 31, 2013 at 09:33:24AM +0800, feng xiangjun wrote:
> Hello, ville.
>
> Latest git commit 7195a50b5c7e00cc3312934fd022c3006b533d12 introduced a
> warning,
>
> +
> +static void intel_crt_get_config(struct intel_encoder *encoder,
> +struct intel_crtc_conf
Now we have this everywhere. Next up would be to wire up the DP
hotplug pin to speed up panel power sequencing for eDP panels ...
I've decided to leave the has_aux_irq logic in the code, it should
come handy for hw bringup.
For testing/fail-safety the dp aux code already has a timeout when
waitin
On Thu, 31 Oct 2013, Seven Li wrote:
> It seems
> PRMs(https://01.org/linuxgraphics/documentation/driver-documentation-prms)
> doesn't have descriptions for registers like following? ^_^
>
> #define EDP_PSR_BASE(dev) 0x64800
We have PSR hardware support since Haswell, and th
On Wed, 30 Oct 2013, Daniel Vetter wrote:
> Now we have this everywhere. Next up would be to wire up the DP
> hotplug pin to speed up panel power sequencing for eDP panels ...
>
> I've decided to leave the has_aux_irq logic in the code, it should
> come handy for hw bringup.
>
> For testing/fail-s
It seems
PRMs(https://01.org/linuxgraphics/documentation/driver-documentation-prms)
doesn't have descriptions for registers like following? ^_^
#define EDP_PSR_BASE(dev) 0x64800
Thanks,
Seven Li
___
Intel-gfx mailing list
Inte
On the series,
Reviewed-by: Jani Nikula
On Wed, 30 Oct 2013, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> If the eDP output is disabled, then we try to use /dev/i2c-X file to
> do i2c transations, we get a WARN from intel_dp_check_edp() saying
> we're trying to do AUX communication with the p
On Wed, 30 Oct 2013, Antti Koskipaa wrote:
> Upcoming hardware will not have the various display pipe register
> ranges evenly spaced in memory. Change register address calculations
> into array lookups.
>
> Tested on SandyBridge.
>
> I left the UMS cruft untouched.
>
> Signed-off-by: Antti Koskip
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