On Tue, 27 Aug 2013, Ville Syrjälä wrote:
> On Tue, Aug 27, 2013 at 03:12:21PM +0300, Jani Nikula wrote:
>> +#define DSI_PLL_CLK_GATE_MASK (0xf << 5)
>> +#define DSI_PLL_CKK_GATE_DSI0_DSIPLL (1 << 8)
>> +#define DSI_PLL_CKK_GATE_DSI1_DSIPLL (1 <<
From: ymohanma
v2:
- Grab dpio_lock mutex in vlv_enable_dsi_pll().
- Add and call vlv_disable_dsi_pll().
v3: Mostly based on Ville's review comments.
- Only pipe A has DSI PLL lock bit.
- Add more of CCK REG bit definitions for DSI PLL.
- Make tables static.
- Move clock gating out of the
From: Paulo Zanoni
We currently use the recommended values from BSpec, but the VBT
specifies the correct value to use for the hardware we have, so use
it. We also fall back to the recommended value in case we can't find
the VBT.
In addition, this code also provides some infrastructure to parse m
From: Paulo Zanoni
We currently treat the child_device_config as a simple struct, but
this is not correct: new BDB versions change the meaning of some
offsets, so the struct needs to be adjusted for each version.
Since there are too many changes (today we're in version 170!), making
a big versio
If noone hers to them first poke me tomorrow. On an aircraft right now.
Daniel Vetter wrote:
>On Fri, Jul 26, 2013 at 01:32:50PM -0700, Jesse Barnes wrote:
>> These address the comments I've received so far, but omit the new
>E820
>> type for this mem.
>>
>> Chris's patches could go on top if de
On Tue, Aug 27, 2013 at 1:19 PM, Chris Wilson wrote:
> On Tue, Aug 27, 2013 at 11:39:52AM +0200, Daniel Vetter wrote:
>> Patch 17: Should be tested by someone else with a gt3. Who has one?
>
> More missing mails, I haven't got the patch to comment on, so bare with
> me.
No problem... it seems I'l
Please don't merge this one... I'll resend it changing the commit
message and subject soon
On Tue, Aug 27, 2013 at 12:31 PM, Rodrigo Vivi wrote:
> Tested-by: Meng, Mengmeng
>
>
>
> On Mon, Aug 26, 2013 at 7:51 PM, Rodrigo Vivi wrote:
>> Full HSW GT3 power can only be achieved with all Execution
On Tue, Aug 27, 2013 at 03:12:12PM +0300, Jani Nikula wrote:
> Hi all, v3 of [1] addressing (most of) Ville's review comments.
>
> I am not reposting patch 1/15 to dri-devel, as it's unchanged since [2].
Didn't really look at the AUO and VBT patches (15 and 13) since I have
no specs for those. I
On Tue, Aug 27, 2013 at 11:39:52AM +0200, Daniel Vetter wrote:
> Patch 17: Should be tested by someone else with a gt3. Who has one?
More missing mails, I haven't got the patch to comment on, so bare with
me.
The title and changelog is misleading, this is not about enabling Lower
Slice at all.
S
On Tue, Aug 27, 2013 at 03:12:21PM +0300, Jani Nikula wrote:
> From: ymohanma
>
> v2:
> - Grab dpio_lock mutex in vlv_enable_dsi_pll().
> - Add and call vlv_disable_dsi_pll().
>
> v3: Mostly based on Ville's review comments.
> - Only pipe A has DSI PLL lock bit.
> - Add more of CCK REG bit d
Detangle the additional state of whether or not the hw has the pfit
enabled from whether it has zero size. This allows us to cleanly
distinguish in the code when we expect the pfit to be enabled (for
Haswell pc8), and when the BIOS is confused and needs sanitizing.
Reported-by: shui yanwei
Refere
Tested-by: Meng, Mengmeng
On Mon, Aug 26, 2013 at 7:51 PM, Rodrigo Vivi wrote:
> Full HSW GT3 power can only be achieved with all Execution Units turned on.
> This patch enables all EUs present on HSW GT3 by enabling lower slice.
>
> Credits-by: Yejun Guo
> Signed-off-by: Rodrigo Vivi
> ---
On Tue, Aug 27, 2013 at 05:49:24PM +0300, Ville Syrjälä wrote:
> On Mon, Aug 26, 2013 at 07:51:00PM -0300, Rodrigo Vivi wrote:
> > From: Chris Wilson
> >
> > A follow-on to the update of the LLC coherency logic is that we can rely
> > on the LLC being coherent with the CS for rewriting batchbuffe
On Mon, Aug 26, 2013 at 07:51:00PM -0300, Rodrigo Vivi wrote:
> From: Chris Wilson
>
> A follow-on to the update of the LLC coherency logic is that we can rely
> on the LLC being coherent with the CS for rewriting batchbuffers
> irrespective of their cache domain. (This should have no effect
> cu
On Tue, Aug 27, 2013 at 6:39 AM, Daniel Vetter wrote:
> Thanks for doing this Rodrigo. Review plan:
>
> Patches 1-4: Damien
> Patch 5: Some bikeshed pending from earlier review ...
> Patch 6-7: Atm in limbo, I've thought they're merged into the x86 tree
> already.
> Patch 8: Ville
> Patch 9-11: R
On Tue, Aug 27, 2013 at 09:12:40AM -0300, Rodrigo Vivi wrote:
> On Mon, Aug 26, 2013 at 7:51 PM, Rodrigo Vivi wrote:
> > From: Chris Wilson
> >
> > It can be useful to compare at times the current vs requested frequency
> > of the GPU, so provide the contents of RPNSWREQ alonside CAGF.
> >
> > Si
On Mon, Aug 26, 2013 at 7:51 PM, Rodrigo Vivi wrote:
> From: Chris Wilson
>
> It can be useful to compare at times the current vs requested frequency
> of the GPU, so provide the contents of RPNSWREQ alonside CAGF.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 11
Signed-off-by: Jani Nikula
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_drv.h |6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1760808..8b06ab1 100644
--- a/drivers/gpu/drm/i915/in
From: Shobhit Kumar
Initial parsing of the VBT MIPI block. For now, just store the panel id
if found.
Signed-off-by: Shobhit Kumar
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h |5 +
drivers/gpu/drm/i915/intel_bios.c | 16 +++
drivers/gpu/drm/i915/inte
DPLL is not needed for DSI
v2: Rebase due to added DSI PLL assertion patch.
Signed-off-by: Jani Nikula
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_display.c | 50 --
1 file changed, 30 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/dr
From: Shobhit Kumar
Signed-off-by: Shobhit Kumar
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile |1 +
drivers/gpu/drm/i915/auo_dsi_display.c | 182
drivers/gpu/drm/i915/intel_dsi.c |5 +
drivers/gpu/drm/i915/intel_dsi.h
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_display.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index d0e05f1..f526ea9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/
Hi all, v3 of [1] addressing (most of) Ville's review comments.
I am not reposting patch 1/15 to dri-devel, as it's unchanged since [2].
BR,
Jani.
[1] http://mid.gmane.org/cover.1376655793.git.jani.nik...@intel.com
[2] http://mid.gmane.org/1377000330-2904-1-git-send-email-jani.nik...@intel.com
From: Shobhit Kumar
Signed-off-by: Shobhit Kumar
Signed-off-by: ymohanma
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi.c | 48 ++
1 file changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_
For DSI, we need to be asserting DSI PLL, not DPLL.
This is a somewhat stopgap implementation. It's slightly ugly to have to
pass the dsi parameter to intel_enable_pipe().
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_display.c | 44 +++---
1 file chang
This does not include any panel specific sub-encoders yet.
v2: Fix fixed mode handling (Daniel)
v3: Mostly based on Ville's review comments.
- Fix MIPI_HS_TX_TIMEOUT.
- DPI_ENABLE only for video mode.
- Drop ULPS usage for now, use DEVICE_READY only.
- Set MIPI_INIT_COUNT based on txclkesc.
From: ymohanma
v2:
- Grab dpio_lock mutex in vlv_enable_dsi_pll().
- Add and call vlv_disable_dsi_pll().
v3: Mostly based on Ville's review comments.
- Only pipe A has DSI PLL lock bit.
- Add more of CCK REG bit definitions for DSI PLL.
- Make tables static.
- Move clock gating out of the
v2: Rebase due to register bit definition change.
v3: Mostly based on Ville's review comments.
- Use size_t for length all around.
- Reuse dsi_vc_send_short in dsi_vc_send_long.
- Remove stale/incorrect comments.
- Reverse special packet sent interrupt check.
- Use DSI controller regs for rea
The sub-encoder model is copied from DVO.
v2: Add attached_connector to struct intel_dsi.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi.h | 99 ++
1 file changed, 99 insertions(+)
create mode 100644 drivers/gpu/drm/i915/intel_dsi.h
diff --
Add definitions for VLV MIPI DSI registers.
v2: Small fixes per Ville's review comments.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 410 +++
1 file changed, 410 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/d
v2: Add comment this is pipe A only (Ville)
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h |1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5d2bd7ff..e66144e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
For GPIO NC, CCK, CCU, and GPS CORE.
Signed-off-by: Jani Nikula
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/i915_drv.h |8 +
drivers/gpu/drm/i915/i915_reg.h |4 +++
drivers/gpu/drm/i915/intel_sideband.c | 56 +
3 files changed,
From: Shobhit Kumar
Signed-off-by: Shobhit Kumar
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_crtc.c |2 ++
include/uapi/drm/drm_mode.h |2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 54b4169..1acb87a 100644
---
On Tue, Aug 27, 2013 at 12:24:09PM +0300, Imre Deak wrote:
> If need to enable the panel fitter, the crtc timings have to be
> programmed according to the panel's native (fixed) mode. This isn't the
> case atm, since after the encoder changes adjusted_mode to fixed
> mode the crtc_* timing fields o
On Tue, Aug 27, 2013 at 10:12:29AM +, Meng, Mengmeng wrote:
>Hi,
>
>We test performance of this patch set compared to the current mainline
>without these patches applied.
>
>With patches v.s. the current mainline, most of performance change
>little(<2%) except GL benchmark
On Tue, Aug 27, 2013 at 11:39:52AM +0200, Daniel Vetter wrote:
> Thanks for doing this Rodrigo. Review plan:
Please when doing these summaries, include the patch titles.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
___
Intel-gfx mailing
On Mon, Aug 19, 2013 at 04:58:51PM +0100, Damien Lespiau wrote:
> Follow up on v3:
> http://lists.freedesktop.org/archives/dri-devel/2013-August/043696.html
>
> Changes between v3 and v4:
> - Future proof the sending of 3D_Ext_Data
> - Renamed struct hdmi_hdmi_infoframe to hdmi_vendor_infofr
On Mon, Aug 19, 2013 at 04:58:54PM +0100, Damien Lespiau wrote:
[...]
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
[...]
> +static int
> +do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len)
> +{
[...]
> + u8 vic;
> +
> + vic =
Thanks for doing this Rodrigo. Review plan:
Patches 1-4: Damien
Patch 5: Some bikeshed pending from earlier review ...
Patch 6-7: Atm in limbo, I've thought they're merged into the x86 tree already.
Patch 8: Ville
Patch 9-11: Rodrigo
Patch 12: lalala ;-)
Patch 13: I guess this can wait until we al
On Fri, Jul 26, 2013 at 01:32:50PM -0700, Jesse Barnes wrote:
> These address the comments I've received so far, but omit the new E820
> type for this mem.
>
> Chris's patches could go on top if desired; they add a new type and
> resource reservation function for looking up regions by name. That
On Mon, Aug 26, 2013 at 07:51:06PM -0300, Rodrigo Vivi wrote:
> From: Chris Wilson
>
> It appears that Valleyview shares its VGA encoder with more recent
> siblings and requires the same forced detection cycle after a hardware
> reset before we can rely on hotplugging.
>
> Reported-and-tested-by
If need to enable the panel fitter, the crtc timings have to be
programmed according to the panel's native (fixed) mode. This isn't the
case atm, since after the encoder changes adjusted_mode to fixed
mode the crtc_* timing fields of adjusted_mode will stay at their original
non-native values that
On Tue, Aug 27, 2013 at 05:27:21AM +, Biswas, KoushikX wrote:
> Hi Paulo,
> There are some changes in voltage swing levels for Haswell platform. In
> current implementation, macro name are given after the swing values. But
> the values are changed for Haswell. This comment is added to avoid the
Понедельник, 26 августа 2013, 16:22 -07:00 от Eric Anholt :
> Rinat Ibragimov writes:
>
> > Понедельник, 26 августа 2013, 13:40 -07:00 от Eric Anholt :
> >> Ибрагимов Ринат writes:
> >>
> >> > libvdpau uses second DRI driver name to determine which VDPAU driver
> >> > to use. This patch will a
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