On Thu, Aug 15, 2013 at 05:30:25PM -0700, james.aus...@intel.com wrote:
> Hello All-
>
> I'm trying to determine if the ChromeOS-only patches being carried by
> Google still make sense and are the right way to do things in the 3.11+
> world, and Jesse asked me to forward the patches to the list f
From: Todd Broch
BUG=chrome-os-partner:6768
TEST=manual,
- boot kernel
1. cat /sys/module/i915/parameters/i915_enable_rc6
- should equal 1
2. start powertop, goto 'Idle Stats' tab
- make sure that the Package c-states (C6, C7) are entered at some
non-trivial percentage when system is idle
From: Stuart Abercrombie
Doing it on EDP was producing a kernel warning with screen power down.
BUG=chrome-os-partner:17893
TEST=No warning with screen power down. Apple mini DP->VGA adapter still works.
Change-Id: I769c31b43753c7ced7cb0b2f0d50fc96c2486779
[sonnyrao: 3.8: fixup for 3.8]
Review
From: Simon Que
When initializing VBT default values, the alternate BIOS SSC frequency
is selected. This patch allows the non-alternate frequency to be
selected as a default, for specified systems. There is a DMI match list
for systems that are to use the non-alternate frequency. Currently,
on
From: Stéphane Marchesin
This speeds up boot and suspend/resume times.
BUG=chrome-os-partner:13364
TEST=by hand
Change-Id: I8d7b7a22c50bcf32828d492e123ce301cefa297d
Reviewed-on: https://gerrit.chromium.org/gerrit/37047
Reviewed-by: Simon Que
Commit-Ready: Stéphane Marchesin
Tested-by: Stéphan
From: Stéphane Marchesin
The AVI Infoframe disappears on SNB after suspend/resume. This patch
works around what seems to be a hardware issue by doing a dummy register
write on DPMS calls.
BUG=chrome-os-partner:16054
TEST=with the HDMI analyzer: suspend/resume parrot, verify that
TEST=the AVI inf
From: Daniel Erat
Previously, the i915 panel driver would set the backlight to
its maximum level if the level was 0 when turning the
display on. We don't need this (powerd already does it),
and removing it avoids a potential race where we jump to
100% brightness when the brightness-up key is pre
From: Vincent Palatin
On the resume path, wait_for_vblank is called 4 times and waits until its
timeout. To reduce the delays on that path, let's compute the maximum vblank
delay instead of always using the arbitrary 50 ms value.
Signed-off-by: Vincent Palatin
BUG=chrome-os-partner:13364
TEST=
From: Todd Broch
BUG=chrome-os-partner:10516
TEST=manual,
1. Run on several platforms. Measure RAPL power @idle.
2. Check for general platform stability
Change-Id: Ia3c8f1f48eb39ae0fb6e0f6e86b4beb1d214
Signed-off-by: Todd Broch
Reviewed-on: https://gerrit.chromium.org/gerrit/29677
Reviewed
From: Sean Paul
Enable LVDS downclocking in the intel i915 graphics driver. This
will save approximately 200mW when the screen is idle.
Signed-off-by: Sean Paul
BUG=chromium-os:9803
TEST=Tested on alex and lumpy
Change-Id: I6fe403c8d9d520901a01549ad6b5eff80de318f3
Reviewed-on: https://gerrit.
From: Stéphane Marchesin
This abstracts those functions, so that we can plug-in
platform-specific alternatives.
BUG=chrome-os-partner:3276,chrome-os-partner:15248
TEST=by hand: compiles, works
Change-Id: I29dd15722ffed8f5813b34bf0ce4431ce0524cc2
Reviewed-on: https://gerrit.chromium.org/gerrit/3
From: Sean Paul
Lower the RPS thresholds and make them symmetric. This patch increases
the rate of change of the GPU clock, allowing it to clock up more
quickly, and more importantly, clock down when necessary. The problem
this patch solves is that a heavy workload would inflate the clock, and
th
From: Stéphane Marchesin
The thresholds for GPU reclocking are highly asymetrical. This creates an
interesting phenomenon on Chrome startup where the clock ramps up very
quickly, and then the blinking cursor is enough to keep it up. Obviously
having the max GPU clock on the login screen is very b
From: Simon Que
If the firmware did not initialize the backlight PWM registers, set up a
default PWM frequency of 200 Hz. This is determined using the following
formula:
freq = refclk / (128 * pwm_max)
The PWM register allows the max PWM value to be set. So we want to use
the formula, where
From: Simon Que
marcheu added these changes in kernel 3.0:
https://gerrit.chromium.org/gerrit/12367
https://gerrit.chromium.org/gerrit/12368
They were undone in kernel 3.2. This patch restores them.
BUG=chromium-os:27468
TEST=power_x86Settings autotest passes with kernel 3.2
Change-Id: Ic5a
From: Stuart Abercrombie
When in DPMS sleep state the Apple mini DP->VGA adapter doesn't respond.
This led to no external display on boot.
v2: Avoid DPCD check and keep AUX awake for EDID read.
BUG=chrome-os-partner:17063
TEST=Straight DP and various adapters on mini-DP and DP platforms.
Chang
From: Stuart Abercrombie
Higher dot clocks were working because pixel doubling was enabled.
Lower the apparently arbitrary threshold so it's enabled for 2048x1280.
Intel hasn't felt moved to document any of this, so this is purely empirical.
The original threshold was introduced here:
http://c
From: Duncan Laurie
We had been using a DMI table workaround to select the right
frequency for devices, but this is fragile and must be updated
with every new platform.
Instead the default case when VBT is missing is changed to use
120MHz clock for LVDS SSC for these generations.
The docs for 2
From: Sameer Nanda
The i915_min_freq setting was not getting honored on the resume path.
Fixed it.
BUG=chrome-os-partner:16439
TEST="cat /sys/kernel/debug/dri/0/i915_min_freq" and remember the value
returned. Do a suspend/resume cycle. cat the i915_min_freq file again,
it must return the same va
From: Stéphane Marchesin
BUG=chromium:148595
TEST=by hand, connect a mac DP to VGA adapter, machine doesn't reboot.
Change-Id: I29d518a7e2d906291d75da58a0d4a7c6296658cc
Reviewed-on: https://gerrit.chromium.org/gerrit/33489
Reviewed-by: Mandeep Singh Baines
Tested-by: Stéphane Marchesin
Reviewe
From: Stéphane Marchesin
Some adapters return DEFER indefinitely, which results in being stuck in the
kernel, which triggers the watchdog, which reboots. To avoid this, limit to
100 tries, after which we return an error and pring a message.
BUG=chrome-os-partner:15612
TEST=by hand, use the apple
From: Chris Wolfe
Unfortunately some combinations of hardware seem to generate successful
communications on the aux channel, which always report deferred. As a
result native_write can wind up in an infinite loop.
This hack adds a large (~10ms) retry limit to avoid a kernel panic,
while hopefully
Hello All-
I'm trying to determine if the ChromeOS-only patches being carried by
Google still make sense and are the right way to do things in the 3.11+
world, and Jesse asked me to forward the patches to the list for evaluation
and potential upstreaming.
Thanks!
-James
[PATCH] drm/i915: Only
From: Stéphane Marchesin
Otherwise things go very, very dark.
BUG=chromium-os:33854
TEST=by hand
Change-Id: I3122447a255652ba5c98863664c0f60e1859c490
Reviewed-on: https://gerrit.chromium.org/gerrit/31293
Tested-by: Stéphane Marchesin
Reviewed-by: Sean Paul
Commit-Ready: Stéphane Marchesin
[m
From: Stéphane Marchesin
This breaks video decode on SNB, so let's not do it.
BUG=chromium:260836
TEST=by hand, video works after resume
Change-Id: I059b022ba1379599f219ad0828e3b4d0e0195f0b
Reviewed-on: https://gerrit.chromium.org/gerrit/65431
Tested-by: Stéphane Marchesin
Reviewed-by: Ilja H.
From: Stéphane Marchesin
This is basically increasing the delay added by commit:
commit 1d20c4fb51f18461f385ab7f039f695d37b15958
Author: Stéphane Marchesin
Date: Wed Jun 26 15:17:11 2013 -0700
CHROMIUM: drm/i915: Work around PPT chipsets wakeup delays
As it seems the previous delay wasn
From: Sameer Nanda
This is a regression from the initial i915 PC7 sandbox branch to the one
that finally got merged. It is resulting in increased power draw of
~1W due to low PC7 residency. Pulling this in as a CHROMIUM fix for now
till it gets resolved upstream.
BUG=chrome-os-partner:20840
TEST
From: Paul Taysom
drivers/gpu/drm/i915/intel_hdmi.c:785:27: warning: unused variable
'adjusted_mode' [-Wunused-variable]
Deleted unused variable, adjusted_mode.
BUG=chromium:237705
TEST=compile kernel and look for warnings.
Signed-off-by: Paul Taysom
Change-Id: I9407b3a54ebba0a7fba0f6e0d1db7
From: Sameer Nanda
On Sandybridge/Ivybridge platforms, a higher RC6_THRESHOLD is required
for stability reasons. On Haswell, however, this higher setting is
resulting in an additional ~800mW of power consumption in light GPU
usage scenarios such as blinking cursor. Lowering RC6_THRESHOLD to 5
From: Stéphane Marchesin
Apparently 150k doesn't work on snb. After probing the snb I have
here, 125k is the max that the hardware seems to work with, and
luckily it seems stable after 50 power_Resume runs. So let's use
that.
BUG=chromium:251989
TEST=see rc6 residency go up in /sys/kernel/debug/
From: Stéphane Marchesin
Right after resume, panther point chipsets seem to ignore all
register writes. But if you wait a bit and retry, everything works
fine. I empirically measured that the window where it is flakey lasts
around 25ms, so let's sleep 30ms after turning on the PCH clock.
BUG=chr
From: Sonny Rao
Fix the setting of max backlight value in the case where there's no VBIOS.
The earlier port of CHROMIUM: drivers: i915: Default backlight PWM frequency
missed this case.
BUG=chromium:244616
TEST=test lumpy at max brightness and make sure the backlight stays on
Change-Id: I24550c
From: Stéphane Marchesin
Before swapping, the shrinker gets called on all drivers to try
and reclaim some memory before resorting to disk access. For
i915, the shrinker will eventually try to move objects out of
the GTT to make them swappable. However when this happens too
often, this will have t
From: Stéphane Marchesin
i915 resume relies on vt switch in kernel 3.8.
This is wrong on systems which don't vt switch, like Chrome OS.
Instead, we just save and restore the state properly across
suspend/resume by:
- not disabling everthying on suspend
- forcing a modeset on resume
- forcing a r
From: Stéphane Marchesin
intel_crtc_update_cursor takes a drm_crtc but we were passing an
intel_crtc. Fix the warning by passing the base class.
BUG=none
TEST=compiles and runs on link
Change-Id: I487ef1984f7957b47bcc6e3edada8911224d8771
Reviewed-on: https://gerrit.chromium.org/gerrit/51383
Tes
From: Daniel Kurtz
i915 gmbus writes at 400kHz should now work properly.
So, enable 400kHz and the native gmbus algorithm by default, but limit
to known high speed devices:
* atmel_mxt devices on vga ddc
* atmel_mxt devices (app mode and bootloader) on panel ddc
After further testing, this
From: Stéphane Marchesin
This is a partial revert of:
drm/i915: read out the modeset hw state at load and resume time
which fixes modeset on boot on alex on 3.8.
BUG=chromium-os:38961
TEST=boot alex with 3.8, see a picture
Change-Id: Id6efac800f4007ded759d237af5643d94ad839c3
---
drivers/gpu/dr
From: Stéphane Marchesin
During suspend/resume all fences are reset, including their pin
count which is reset to 0. However a framebuffer can be bound across
suspend/resume, which means that after the buffer is unbound on
resume, the pin count for the buffer will be negative. Since the
fence pin
From: Stéphane Marchesin
It's basically the same deal as the RC6+ issues on ivy bridge
(https://gerrit.chromium.org/gerrit/#/c/42655/) except this
time with RC6 on sandy bridge. Like last time the core of the
issue is that the existing timings don't work 100% with our
voltage regulator, so once i
From: Daniel Kurtz
Currently, 400kHz i2c transactions on i915 ddc adapters are gated by
long polling loops in the wait_for() macro.
For the case where the polling loops sleep, make them tighter by
converting a msleep(1) to usleep_range(50, 100);
A better solution might be to eliminate this polli
From: Stéphane Marchesin
The i915 driver stopped doing this in 3.8. Chrome OS machines rely
on this initialization since they don't have a VBIOS.
BUG=chromium:242552
TEST=by hand on a stumpy which doesn't run the vbios: the backlight is non-zero
Change-Id: Ia76238a1e93e89a4f1434e88edb431225062f
From: Benson Leung
The atmel_mxt_ts bootloader mode can support 400khz operation
successfully. Enable it for bootloader at address 0x25 on the
VGADDC adapter.
BUG=chrome-os-partner:9994
TEST=place valid atmel mxt firmware at /lib/firmware/maxtouch.fw
time echo 1 > update_fw
Check that firmware u
From: Benson Leung
Allow 400khz mode on port2, VGADDC address 0x67 for
cyapa i2c touchpads. This will improve firmware
update speed.
BUG=chrome-os-partner:9798
TEST=time echo 1 > /sys/bus/i2c/devices/2-0067/update_fw
Check that the update firmware succeeds, and the time
taken was:
real0m13.8
From: Stéphane Marchesin
This adds device-specific backlight support for Link, and also
enables adaptive backlight by default there.
BUG=chrome-os-partner:13276,chrome-os-partner:15248
TEST=by hand
Change-Id: I9ef546bba9f121657a653aa9cfc6a80bbde55cb0
Reviewed-on: https://gerrit.chromium.org/ger
From: Stéphane Marchesin
When the CPU is loaded and the GPU tries to switch RC6p modes, the GPU
sometimes gets stuck in RC6p mode and doesn't come out of it. I suspect
that our voltage rail is too weak and sometimes falls behind.
This change throttles down the number of RC6p transitions we do to
From: Kees Cook
It is possible to wrap the counter used to allocate the buffer for
relocation copies. This could lead to heap writing overflows.
BUG=chromium-os:39733
TEST=link build, PoC fails
[sending upstream]
Change-Id: Ifdd4ae846042852a4462d70cfa3c3b84d5a9d133
Signed-off-by: Kees Cook
Re
On Fri, 2013-08-16 at 08:49 +1000, Dave Airlie wrote:
> On Fri, Aug 16, 2013 at 8:43 AM, Alex Williamson
> wrote:
> > This is intended to add VGA arbiter support for Intel HD graphics on
> > Core processors. The old GMCH registers no longer exist, so even
> > though it appears that i915 participa
On Fri, Aug 16, 2013 at 8:43 AM, Alex Williamson
wrote:
> This is intended to add VGA arbiter support for Intel HD graphics on
> Core processors. The old GMCH registers no longer exist, so even
> though it appears that i915 participates in VGA arbitration, it doesn't
> work. On Intel HD graphics
This is intended to add VGA arbiter support for Intel HD graphics on
Core processors. The old GMCH registers no longer exist, so even
though it appears that i915 participates in VGA arbitration, it doesn't
work. On Intel HD graphics we already attempt to disable VGA regions
of the device. This m
When VGA decodes change we need to do a bit more evaluation of exactly what
has changed. We don't necessarily give up all the old owns resources and
we need to account for resources with locks. The new algorithm is: If
something is added, update decodes. If legacy resources were added and
none w
I'm trying to add support for VGA arbitration on newer Intel graphics
devices. The existing code attempts to do this, but appear to have
not been updated since GMCH devices roamed the Earth. On newer
devices like Haswell, we can disable VGA memory through an MSR on the
device, but we rely on the
If a device does not own a resource then we don't need to disable it.
This resolves the case where an Intel IGD device can be configured to
disable decode of VGA memory but we still need the arbiter to handle
VGA I/O port routing. When the IGD device is in conflict, only
PCI_COMMAND_IO should be d
On Thu, Aug 15, 2013 at 12:00:17PM +0100, Damien Lespiau wrote:
> On Wed, Aug 14, 2013 at 02:21:16PM -0700, Ben Widawsky wrote:
> > From: "Xiang, Haihao"
> >
> >predicate SEND execsize dst sendleadreg payload directsrcoperand
> > instoptions
> >predicate SEND execsize dst sendleadreg pay
On Thu, Aug 15, 2013 at 04:05:56PM +0200, Daniel Vetter wrote:
> On Wed, Aug 14, 2013 at 10:15:50AM +0200, Daniel Vetter wrote:
> > On Wed, Aug 14, 2013 at 10:06:30AM +0200, Daniel Vetter wrote:
> > > On Tue, Aug 13, 2013 at 06:09:06PM -0700, Ben Widawsky wrote:
> > > > VMAs can be created and not
Hi Dave,
Might as well also send you a pull request and flush out the single
regression fixer I have here.
Cheers, Daniel
The following changes since commit d4e4ab86bcba5a72779c43dc1459f71fea3d89c8:
Linux 3.11-rc5 (2013-08-11 18:04:20 -0700)
are available in the git repository at:
git://
On Wed, Aug 14, 2013 at 10:54:17AM +0100, Simon Farnsworth wrote:
> Reviewed-by: Simon Farnsworth
Thanks for the review, pushed this along with a patch to decode
3D_Ext_Data when Side-by-side (half) is programmed in 3D_structure
--
Damien
___
Intel-gf
On Wed, Aug 14, 2013 at 06:19:13PM +0100, Damien Lespiau wrote:
[...]
> diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h
[...]
> +union hdmi_vendor_infoframe {
> + struct {
> + enum hdmi_infoframe_type type;
> + unsigned char version;
> + unsigned cha
On Wed, Aug 14, 2013 at 06:19:12PM +0100, Damien Lespiau wrote:
[...]
> +#define HDMI_IDENTIFIER 0x000c03
HDMI_IDENTIFIER sounds really generic. Perhaps HDMI_INFOFRAME_OUI_HDMI?
Thierry
pgpsLkgvKVXmx.pgp
Description: PGP signature
___
Intel-gfx mailin
On Wed, Aug 14, 2013 at 06:19:10PM +0100, Damien Lespiau wrote:
[...]
> diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
> index ac84215..59c4748 100644
> --- a/drivers/video/hdmi.c
> +++ b/drivers/video/hdmi.c
> @@ -286,6 +286,94 @@ ssize_t hdmi_audio_infoframe_pack(struct
> hdmi_audio_in
On Wed, Aug 14, 2013 at 06:19:09PM +0100, Damien Lespiau wrote:
> Just like:
>
> Author: Damien Lespiau
> Date: Mon Aug 12 11:53:24 2013 +0100
>
> video/hdmi: Don't let the user of this API create invalid infoframes
>
> But this time for the horizontal/vertical bar data present bits
On Wed, Aug 14, 2013 at 06:19:08PM +0100, Damien Lespiau wrote:
> To set the active aspect ratio value in the AVI infoframe today, you not
> only have to set the active_aspect field, but also the active_info_valid
> bit. Out of the 1 user of this API, we had 100% misuse, forgetting the
> _valid bit
Hi,
when changing the refresh rate of my laptop display with xrandr on 3.11.0-rc5,
like:
xrandr --output LVDS1 --rate 59.9 --mode 1920x1080
The following WARNING is generated:
[ 50.018055] [drm:intel_pipe_config_compare] *ERROR* mismatch in
adjusted_mode.flags (expected 1, found 0)
[ 50.01
From: Paulo Zanoni
Because hsw_pm_irq_handler does exactly what gen6_rps_irq_handler does
and also processes the 2 additional VEBOX bits. So merge those
functions and wrap the VEBOX bits on a HAS_VEBOX check. This
check isn't really necessary since the bits are reserved on
SNB/IVB/VLV, but it's a
From: Paulo Zanoni
On SNB/IVB/VLV we only call gen6_rps_irq_handler if one of the IIR
bits set is part of GEN6_PM_RPS_EVENTS, but at gen6_rps_irq_handler we
add all the enabled IIR bits to the work queue, not only the ones that
are part of GEN6_PM_RPS_EVENTS. But then gen6_pm_rps_work only
proces
On Thu, Aug 15, 2013 at 3:38 PM, Damien Lespiau
wrote:
> On Tue, Aug 13, 2013 at 04:29:43PM +0300, Jani Nikula wrote:
>> Add definitions for VLV MIPI DSI registers.
>>
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 409
>> +++
>> 1
On Wed, Aug 14, 2013 at 10:15:50AM +0200, Daniel Vetter wrote:
> On Wed, Aug 14, 2013 at 10:06:30AM +0200, Daniel Vetter wrote:
> > On Tue, Aug 13, 2013 at 06:09:06PM -0700, Ben Widawsky wrote:
> > > VMAs can be created and not bound. One may think of it as lazy cleanup,
> > > and safely gloss over
On Tue, Aug 13, 2013 at 04:29:43PM +0300, Jani Nikula wrote:
> Add definitions for VLV MIPI DSI registers.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_reg.h | 409
> +++
> 1 file changed, 409 insertions(+)
I wonder if it'd be the right
2013/8/14 Rodrigo Vivi :
> On Tue, Aug 06, 2013 at 06:57:15PM -0300, Paulo Zanoni wrote:
>> From: Paulo Zanoni
>>
>> Just like irq_mask and gt_irq_mask, use it to track the status of
>> GEN6_PMIMR so we don't need to read it again every time we call
>> snb_update_pm_irq.
>>
>> Signed-off-by: Paulo
2013/8/14 Rodrigo Vivi :
> Reviewed-by: Rodrigo Vivi
>
> On Tue, Aug 06, 2013 at 06:57:13PM -0300, Paulo Zanoni wrote:
>> From: Paulo Zanoni
>>
>> Just like we're doing with the other IMR changes.
>>
>> One of the functional changes is that not every caller was doing the
>> POSTING_READ.
>>
>> Si
2013/8/14 Rodrigo Vivi
>
> Reviewed-by: Rodrigo Vivi
>
> .On Tue, Aug 06, 2013 at 06:57:12PM -0300, Paulo Zanoni wrote:
> > From: Paulo Zanoni
> >
> > Just like the functions that touch DEIMR and SDEIMR, but for GTIMR.
> > The new functions contain a POSTING_READ(GTIMR) which was not present
> >
On Thu, Aug 15, 2013 at 11:55:33AM +0100, Damien Lespiau wrote:
> On Tue, Aug 13, 2013 at 04:23:17PM -0700, Josh Triplett wrote:
> > When building kernels for a preliminary hardware target, having to add a
> > kernel command-line option can prove inconvenient. Add a Kconfig option
> > that changes
On Thu, Aug 15, 2013 at 12:07:44PM +0100, Damien Lespiau wrote:
> On Wed, Aug 14, 2013 at 02:40:37PM -0300, Paulo Zanoni wrote:
> > From: Paulo Zanoni
> >
> > Our driver initialization doesn't seem to be ready to load when the
> > power well is disabled: we hit a few "Unclaimed register" messages
On Wed, Aug 14, 2013 at 02:40:37PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> Our driver initialization doesn't seem to be ready to load when the
> power well is disabled: we hit a few "Unclaimed register" messages. So
> do just like we already do for the suspend/resume path: enable the
On Wed, Aug 14, 2013 at 02:21:16PM -0700, Ben Widawsky wrote:
> From: "Xiang, Haihao"
>
>predicate SEND execsize dst sendleadreg payload directsrcoperand
> instoptions
>predicate SEND execsize dst sendleadreg payload imm32reg instoptions
>predicate SEND execsize dst sendleadreg paylo
On Tue, Aug 13, 2013 at 04:23:17PM -0700, Josh Triplett wrote:
> When building kernels for a preliminary hardware target, having to add a
> kernel command-line option can prove inconvenient. Add a Kconfig option
> that changes the default of this option to 1.
FWIW, I like it (and had something si
On Thu, Aug 15, 2013 at 9:24 AM, Chris Wilson wrote:
> On Thu, Aug 15, 2013 at 12:02:40AM +0200, Daniel Vetter wrote:
>> All the gem based kms drivers really want the same function to
>> destroy a dumb framebuffer backing storage object.
>>
>> So give it to them and roll it out in all drivers.
>>
On Wed, 14 Aug 2013, Ville Syrjälä wrote:
> On Tue, Aug 13, 2013 at 04:29:43PM +0300, Jani Nikula wrote:
>> Add definitions for VLV MIPI DSI registers.
>>
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 409
>> +++
>> 1 file change
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