At Fri, 5 Jul 2013 18:19:32 -0300,
Paulo Zanoni wrote:
>
> 2013/7/4 Wang xingchao :
> > On Thu, Jul 04, 2013 at 10:24:15AM -0300, Paulo Zanoni wrote:
> >> 2013/7/4 Wang xingchao :
> >> > On Wed, Jul 03, 2013 at 05:00:51PM -0300, Paulo Zanoni wrote:
> >> >> 2013/6/6 Daniel Vetter :
> >> >> > On Thu
On Fri, Jul 05, 2013 at 11:53:41PM +0100, Chris Wilson wrote:
> On Fri, Jul 05, 2013 at 11:39:50PM +0200, Daniel Vetter wrote:
> > It's not a good idea to also run the pipe_control cleanup.
> >
> > This regression has been introduced whith the original cs tlb w/a in
> >
> > commit b45305fce5bb1ab
On Fri, Jul 05, 2013 at 11:39:50PM +0200, Daniel Vetter wrote:
> It's not a good idea to also run the pipe_control cleanup.
>
> This regression has been introduced whith the original cs tlb w/a in
>
> commit b45305fce5bb1abec263fcff9d81ebecd6306ede
> Author: Daniel Vetter
> Date: Mon Dec 17 16
2013/6/28 Rodrigo Vivi :
> Required function to disable PSR when going to console mode.
> But also can be used whenever PSR mode entry conditions changed.
>
> v2: Add it before PSR Hook. Update function not really been called yet.
> v3: Fix coding style detected by checkpatch by Paulo Zanoni.
>
> C
2013/7/1 Rodrigo Vivi :
> Adding Enable and Disable PSR functionalities. This includes setting the
> PSR configuration over AUX, sending SDP VSC DIP over the eDP PIPE config,
> enabling PSR in the sink via DPCD register and finally enabling PSR on
> the host.
>
> This patch is based on initial PSR
On Fri, Jul 5, 2013 at 11:58 PM, Paulo Zanoni wrote:
>>> My interpretation of the spec is that we need to wait until exactly
>>> after the VSync so we don't send incomplete packets, but we don't have
>>> a good way to do this, and intel_wait_for_vblank doesn't help us with
>>> that. If you take a
On Friday, July 05, 2013 11:40:02 PM Rafael J. Wysocki wrote:
> On Friday, July 05, 2013 10:00:55 PM Rafael J. Wysocki wrote:
> > On Friday, July 05, 2013 02:20:14 PM Rafael J. Wysocki wrote:
> > > On Sunday, June 09, 2013 07:01:39 PM Matthew Garrett wrote:
> > > > Windows 8 leaves backlight contro
On Fri, Jul 05, 2013 at 02:41:06PM -0700, Ben Widawsky wrote:
> Embedding the node in the obj is more natural in the transition to VMAs
> which will also have embedded nodes. This change also helps transition
> away from put_block to remove node.
>
> Though it's quite an uncommon occurrence, it's
Hi
Sorry for the delay.
2013/7/1 Rodrigo Vivi :
> On Fri, Jun 28, 2013 at 4:31 PM, Paulo Zanoni wrote:
>> Hi
>>
>> 2013/6/28 Rodrigo Vivi :
>>> Adding Enable and Disable PSR functionalities. This includes setting the
>>> PSR configuration over AUX, sending SDP VSC DIP over the eDP PIPE config,
>
On Fri, Jul 05, 2013 at 12:29:14PM -0700, Ben Widawsky wrote:
> On Thu, Jul 04, 2013 at 08:49:44PM +0200, Daniel Vetter wrote:
> > At least for the common cases where we only need special file
> > operations. The forcewake file is still rather more special.
> >
> > v2: Fix up the debugfs unregiste
It's not a good idea to also run the pipe_control cleanup.
This regression has been introduced whith the original cs tlb w/a in
commit b45305fce5bb1abec263fcff9d81ebecd6306ede
Author: Daniel Vetter
Date: Mon Dec 17 16:21:27 2012 +0100
drm/i915: Implement workaround for broken CS tlb on i8
On Fri, Jul 05, 2013 at 06:34:46PM -0300, Paulo Zanoni wrote:
> 2013/7/4 Daniel Vetter :
> > On Thu, Jul 04, 2013 at 12:28:35PM +0100, Chris Wilson wrote:
> >> Sanity check that the memory region found through the Graphics Base
> >> of Stolen Memory is reserved and hidden from the rest of the syste
Soon we want to gut a lot of our existing assumptions how many address
spaces an object can live in, and in doing so, embed the drm_mm_node in
the object (and later the VMA).
It's possible in the future we'll want to add more getter/setter
methods, but for now this is enough to enable the VMAs.
v
From: Chris Wilson
Clients like i915 needs to segregate cache domains within the GTT which
can lead to small amounts of fragmentation. By allocating the uncached
buffers from the bottom and the cacheable buffers from the top, we can
reduce the amount of wasted space and also optimize allocation o
Embedding the node in the obj is more natural in the transition to VMAs
which will also have embedded nodes. This change also helps transition
away from put_block to remove node.
Though it's quite an uncommon occurrence, it's somewhat convenient to not
fail at bind time because we cannot allocate
With the getters in place from the previous patch this members serves no
purpose other than saving one spare pointer chase, which will be killed
in the next patch anyway.
Moving to VMAs, this members adds unnecessary confusion since an object
may exist at different offsets in different VMs.
v2: P
This reverts commit 7dedae28b41000539b6c18bcf72107c97e4937e4.
Conflicts:
drivers/gpu/drm/i915/i915_drv.h
---
drivers/gpu/drm/i915/i915_drv.h| 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c| 2 +-
drivers/gpu/drm/i915/i915_gem_stolen.c | 2 +-
3 files changed, 3 insertions(+), 3 del
With the previous patch we no longer actually create a node, we simply
find the correct hole and occupy it. This very well could have been
squashed with the last patch, but since I already had David's review, I
figured it's easiest to keep it distinct.
Also update the users in i915. Conveniently t
For an upcoming patch where we introduce the i915 VMA, it's ideal to
have the drm_mm_node as part of the VMA struct (ie. it's pre-allocated).
Part of the conversion to VMAs is to kill off obj->gtt_space. Doing this
will break a bunch of code, but amongst them are 2 callers of
drm_mm_create_block(),
This reverts commit a6b27b42fbb01a6b6523ff1ab6a6d440d0eba1ae.
---
drivers/gpu/drm/i915/i915_drv.h| 7 +++
drivers/gpu/drm/i915/i915_gem.c| 2 ++
drivers/gpu/drm/i915/i915_gem_stolen.c | 1 +
3 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drive
This reverts commit 3c7354329d77c333dab8647676c3de342f022dc9.
---
drivers/gpu/drm/i915/i915_debugfs.c| 26 -
drivers/gpu/drm/i915/i915_drv.h| 31 ---
drivers/gpu/drm/i915/i915_gem.c| 89 +++---
drivers/gpu/drm/i915/i915_gem_co
2013/7/4 Daniel Vetter :
> On Thu, Jul 04, 2013 at 12:28:35PM +0100, Chris Wilson wrote:
>> Sanity check that the memory region found through the Graphics Base
>> of Stolen Memory is reserved and hidden from the rest of the system
>> through the use of the resource API.
>>
>> v2: "Graphics Stolen M
On Friday, July 05, 2013 10:00:55 PM Rafael J. Wysocki wrote:
> On Friday, July 05, 2013 02:20:14 PM Rafael J. Wysocki wrote:
> > On Sunday, June 09, 2013 07:01:39 PM Matthew Garrett wrote:
> > > Windows 8 leaves backlight control up to individual graphics drivers
> > > rather
> > > than making AC
2013/7/4 Wang xingchao :
> On Thu, Jul 04, 2013 at 10:24:15AM -0300, Paulo Zanoni wrote:
>> 2013/7/4 Wang xingchao :
>> > On Wed, Jul 03, 2013 at 05:00:51PM -0300, Paulo Zanoni wrote:
>> >> 2013/6/6 Daniel Vetter :
>> >> > On Thu, May 30, 2013 at 10:07:07PM +0800, Wang Xingchao wrote:
>> >> >> Hi a
On Mon, Jul 01, 2013 at 05:47:39PM -0300, Rodrigo Vivi wrote:
> Again, Thank you very much for your comments.
>
> Replying what I did and why I didn't here and patches coming later.
Paulo asked me to drop by maintainer bikeshed on this patch. So here I'l
comply ;-)
>
>
> On Fri, Jun 28, 2013 a
On Fri, Jul 05, 2013 at 11:02:48PM +0300, Ville Syrjälä wrote:
> On Fri, Jul 05, 2013 at 12:51:54PM -0700, Ben Widawsky wrote:
> > On Fri, Jul 05, 2013 at 04:48:18PM +0300, ville.syrj...@linux.intel.com
> > wrote:
> > > I was going over the workaround database with VLV mainly in mind, but I
> > >
On Fri, Jul 05, 2013 at 12:51:54PM -0700, Ben Widawsky wrote:
> On Fri, Jul 05, 2013 at 04:48:18PM +0300, ville.syrj...@linux.intel.com wrote:
> > I was going over the workaround database with VLV mainly in mind, but I
> > ended up stumbling on quite a few others as well.
> >
> > This series adds
On Friday, July 05, 2013 02:20:14 PM Rafael J. Wysocki wrote:
> On Sunday, June 09, 2013 07:01:39 PM Matthew Garrett wrote:
> > Windows 8 leaves backlight control up to individual graphics drivers rather
> > than making ACPI calls itself. There's plenty of evidence to suggest that
> > the Intel dri
On Fri, Jul 05, 2013 at 04:48:18PM +0300, ville.syrj...@linux.intel.com wrote:
> I was going over the workaround database with VLV mainly in mind, but I
> ended up stumbling on quite a few others as well.
>
> This series adds the workarounds names in a bunch of places where we
> missed them, adds
On Fri, Jul 05, 2013 at 04:48:28PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Certain SNB steppings need to disable DOP clock gating, and the only
> way to do that is to use the MISCCPCTL register.
>
> Just disable it for every SNB, and then I suppose we may not have t
On Fri, Jul 05, 2013 at 09:25:35PM +0200, Daniel Vetter wrote:
> On Thu, Jul 04, 2013 at 10:32:27PM +0200, David Herrmann wrote:
> > Hi
> >
> > On Thu, Jul 4, 2013 at 10:14 PM, Ben Widawsky wrote:
> > > For an upcoming patch where we introduce the i915 VMA, it's ideal to
> > > have the drm_mm_nod
On Fri, Jul 05, 2013 at 03:21:45PM +, Zhang, Xiong Y wrote:
> I found this issue when I read code. I don't have testcase.
Ok, merged to -fixes, thanks for the patch.
-Daniel
>
> thanks
> -Original Message-
> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vett
On Thu, Jul 04, 2013 at 08:49:44PM +0200, Daniel Vetter wrote:
> At least for the common cases where we only need special file
> operations. The forcewake file is still rather more special.
>
> v2: Fix up the debugfs unregister code.
>
> v3: Actually squash in the right fixup.
>
> Signed-off-by:
On Thu, Jul 04, 2013 at 10:32:27PM +0200, David Herrmann wrote:
> Hi
>
> On Thu, Jul 4, 2013 at 10:14 PM, Ben Widawsky wrote:
> > For an upcoming patch where we introduce the i915 VMA, it's ideal to
> > have the drm_mm_node as part of the VMA struct (ie. it's pre-allocated).
> > Part of the conve
On Thu, Jul 04, 2013 at 12:42:15PM -0700, Ben Widawsky wrote:
> Setting the node directly is good enough. We don't need a special value
> to store the gtt_offset, and we no longer have the pointer to tuck
> things away neatly.
>
> This is temporarily broken since:
> commit 7dedae28b41000539b6c18bc
On Fri, Jul 05, 2013 at 09:12:05AM +0200, Daniel Vetter wrote:
> On Thu, Jul 04, 2013 at 11:24:46PM +0200, Daniel Vetter wrote:
> > On Thu, Jul 04, 2013 at 12:42:15PM -0700, Ben Widawsky wrote:
> > > Setting the node directly is good enough. We don't need a special value
> > > to store the gtt_offs
On Fri, Jul 05, 2013 at 02:51:36PM -0300, Paulo Zanoni wrote:
> 2013/7/5 :
> > From: Ville Syrjälä
> >
> > There is a major problem with the watermark registers; they're not
> > double buffered. So we need to make sure we update them at the correct
> > time when messing about with planes. The cor
On Fri, Jul 05, 2013 at 02:46:44PM -0300, Paulo Zanoni wrote:
> 2013/7/5 Ville Syrjälä :
> > On Fri, Jul 05, 2013 at 10:37:08AM +0100, Chris Wilson wrote:
> >> On Fri, Jul 05, 2013 at 11:57:42AM +0300, ville.syrj...@linux.intel.com
> >> wrote:
> >> > From: Ville Syrjälä
> >> >
> >> > There is a m
On Fri, Jul 05, 2013 at 02:41:02PM -0300, Paulo Zanoni wrote:
> 2013/7/5 Ville Syrjälä :
> > On Fri, Jul 05, 2013 at 01:54:02PM -0300, Paulo Zanoni wrote:
> >> 2013/7/5 :
> >> > Here's my big ILK+ watermark rewrite. The main idea of the series is to
> >> > write the watermark registers at vblank t
2013/7/5 Ville Syrjälä :
> On Fri, Jul 05, 2013 at 10:37:08AM +0100, Chris Wilson wrote:
>> On Fri, Jul 05, 2013 at 11:57:42AM +0300, ville.syrj...@linux.intel.com
>> wrote:
>> > From: Ville Syrjälä
>> >
>> > There is a major problem with the watermark registers; they're not
>> > double buffered.
2013/7/5 :
> From: Ville Syrjälä
>
> The linetime watermarks don't change, except when doing a full modeset,
> so having them as part of the full dynamic watermarks code is pointless.
>
> Just move the linetime watermark setup to occur just before enabling the
> pipe on HSW, and leave it alone af
2013/7/5 Ville Syrjälä :
> On Fri, Jul 05, 2013 at 01:54:02PM -0300, Paulo Zanoni wrote:
>> 2013/7/5 :
>> > Here's my big ILK+ watermark rewrite. The main idea of the series is to
>> > write the watermark registers at vblank to make the changes (almost) in
>> > sync with the plane changes that cau
On Fri, Jul 05, 2013 at 02:19:59PM -0300, Paulo Zanoni wrote:
> 2013/7/5 :
> > From: Ville Syrjälä
> >
> > Want to see them w/ debugs turned off.
>
> And what about PCH FIFO underruns?
Ideally we'd want this patch, and yes, other underrun types too. But
I'm thinking that we don't want it before
On Fri, Jul 05, 2013 at 02:19:22PM -0300, Paulo Zanoni wrote:
> 2013/7/5 :
> > From: Ville Syrjälä
> >
> > Don't want to lose them in the noise. Just let them happen.
>
> When I was experimenting with this, I noticed that when we get
> underruns, we get thousands of underruns per second, until w
On Fri, Jul 05, 2013 at 01:54:02PM -0300, Paulo Zanoni wrote:
> 2013/7/5 :
> > Here's my big ILK+ watermark rewrite. The main idea of the series is to
> > write the watermark registers at vblank to make the changes (almost) in
> > sync with the plane changes that caused the change in watermarks.
>
2013/7/5 :
> From: Ville Syrjälä
>
> Want to see them w/ debugs turned off.
And what about PCH FIFO underruns?
> ---
> drivers/gpu/drm/i915/i915_irq.c | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915
2013/7/5 :
> From: Ville Syrjälä
>
> Don't want to lose them in the noise. Just let them happen.
When I was experimenting with this, I noticed that when we get
underruns, we get thousands of underruns per second, until we fix the
condition that is causing the underruns. With this we'll get tons
2013/7/5 :
> Here's my big ILK+ watermark rewrite. The main idea of the series is to
> write the watermark registers at vblank to make the changes (almost) in
> sync with the plane changes that caused the change in watermarks.
>
> I sent a massive RFC patch a while back, and this is now the somewh
From: Ville Syrjälä
I just got confirmation that we're using some old values for the PLL
LPF coefficients for DP RBR/HDMI/DAC on VLV. The
VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_9 document lists both values
by mistake, and apparently we had picked the wrong one. Change the
coefficients to the
I found this issue when I read code. I don't have testcase.
thanks
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter
Sent: Friday, July 05, 2013 9:41 PM
To: Zhang, Xiong Y
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 2/
On Fri, Jul 05, 2013 at 04:48:26PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> WaMiSetContext_Hang tells us that a MI_NOOP must follow MI_SET_CONTEXT.
>
> The other thing WaMiSetContext_Hang seems to say is that URB_FENCE isn't
> allowed to straddle two cachelines. But
On Fri, Jul 05, 2013 at 06:53:01PM +0800, Xiong Zhang wrote:
> dev_priv->mm.gtt_list has been removed. All the gtt are tracked in
> dev_pirv->mm.bound_list and dev_priv->mm.unbound_list
>
> Signed-off-by: Xiong Zhang
Tbh I've only tried to use this once, and besides that it made everything
reall
From: Ville Syrjälä
I can't see WaDisableDopClockGating listed for IVB in W/A database.
Also I'm not quite sure we were even disabling the right thing. Register
0x9424 has one DOP clock gating disable bit, amd 0xe4f4/0xf4f4 appears
to have another one, but I don't actually know which is the one
From: Ville Syrjälä
The current comments indicate that this function implements
WaVSRefCountFullforceMissDisable, which is only true for HSW.
The original purpose of the function is to implement
WaVSThreadDispatchOverride (and a bit more). Fix up the comments
to match reality.
Signed-off-by: Vil
From: Ville Syrjälä
WaDisable4x2SubspanOptimization isn't listed for VLV in the workaround
database, but BSpec says that the relevant bit must be set. Add a
comment to remind people of this.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 4
1 file changed, 4 insertions
From: Ville Syrjälä
Call gen7_setup_fixed_func_scheduler() on VLV as well.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 22cbe68..49e
From: Ville Syrjälä
BSpec states that the thread override values set by
gen7_setup_fixed_func_scheduler() are invalid for HSW. So let's not
muck around with them.
Since gen7_setup_fixed_func_scheduler() now has two totally independent
parts, one for IVB and one for HSW, move the HSW part directl
From: Ville Syrjälä
WaDisableRCZUnitClockGating was needed with early HSW steppings only.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d8f60e2..8b
From: Ville Syrjälä
WaDisableTDLUnitClockGating is only relevant for early steppings of VLV.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9153e6d..847f
From: Ville Syrjälä
WaDisableVDSUtnitClockGating was only relevant for early steepings of
VLV.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b11bb70.
From: Ville Syrjälä
WaApplyL3ControlAndL3ChickenMode is only relevant to early HSW
steppings..
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8b6d3
From: Ville Syrjälä
Only early VLV steppings needed thist. Should no longer be relevant.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 14 +++---
1 file changed, 3 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/i
From: Ville Syrjälä
Someone copy pasted the comment from the SNB code w/o reading it.
We never actually implemented the workaround to disable RCPB unit
clock gating on IVB. It would have been needed for early steppings,
but we don't care about those anymore, so just remove the stale
comment.
Sig
From: Ville Syrjälä
WaApplyL3ControlAndL3ChickenMode is only listed for IVB and HSW in
W/A database and BSpec.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
From: Ville Syrjälä
Can't find WaDisableRHWOOptimizationForRenderHang listed for HSW.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 82665d5..22f1053
From: Ville Syrjälä
Can't find WaDisableRHWOOptimizationForRenderHang listed for VLV.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 22f1053..40393ef
From: Ville Syrjälä
WaDisableRCCUnitClockGating is only relevant for SNB.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 576f648..8
From: Ville Syrjälä
WaDisableRCCUnitClockGating is only relevant for SNB.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b24a4c2..5
From: Ville Syrjälä
Can't find any mention of WaDisableVDSUnitClockGating ever being
relevant for SNB. Remove it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers
From: Ville Syrjälä
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 6 ++
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 035ae03..29172fb 100644
--- a/drivers/
From: Ville Syrjälä
Both Bspec and the W/A database state that WaDisablePSDDualDispatchEnable
is only needed for IVB GT1.
The only real confusion here is that the the W/A database also says to
write to the GT2 only register as well, which is strange if the W/A is
only for GT1.
Signed-off-by: Vi
From: Ville Syrjälä
IVB GT2 has two registers for these things, and both must be written.
To add a bit more confusion both Bspec and the W/A database state that
WaDisablePSDDualDispatchEnable is only needed for IVB GT1, but the W/A
database also says to write even the second GT2 only register. S
From: Ville Syrjälä
Certain SNB steppings need to disable DOP clock gating, and the only
way to do that is to use the MISCCPCTL register.
Just disable it for every SNB, and then I suppose we may not have to
worry about WaRevertDopClockGateFix2.
There's also another seemingly related workaround
From: Ville Syrjälä
This register exists already on SNB.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_gem.c | 8
drivers/gpu/drm/i915/i915_irq.c | 8
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
drivers/gpu/drm/i915/i915_sysfs.c | 6 +++---
4 files changed, 1
From: Ville Syrjälä
WaMiSetContext_Hang tells us that a MI_NOOP must follow MI_SET_CONTEXT.
The other thing WaMiSetContext_Hang seems to say is that URB_FENCE isn't
allowed to straddle two cachelines. But we don't issue those from the
kernel so we don't care.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 69d4693..b6d8d81 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i9
From: Ville Syrjälä
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2884a32..69d4693 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/
From: Ville Syrjälä
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9a562aa..2884a32 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/
From: Ville Syrjälä
The w/a database lists both WaPsdDispatchEnable and
WaDisablePSDDualDispatchEnable for VLV. They appear to be the same
thing, so list both names.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu
From: Ville Syrjälä
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 76796b1..fc2af13 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++
I was going over the workaround database with VLV mainly in mind, but I
ended up stumbling on quite a few others as well.
This series adds the workarounds names in a bunch of places where we
missed them, adds a few workarounds we seem to have missed, drops some
that were never supposed to be there
From: Ville Syrjälä
WaGsvBringDownFreqInRc6:vlv tells us to switch to RPe from a timer.
Which is what we do.
There's another workaround by the name of
WaGsvBringDownFreqBeforeRenderRC6:vlv which instructs us to keep render
always awake, and then drop the freq to 200MHz and allow RC6 just before
From: Ville Syrjälä
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f675215..15c9c3b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i9
Despite being a unified memory architecture (UMA) some bits of memory
are more equal than others. In particular we have the thorny issue of
stolen memory, memory stolen from the system by the BIOS and reserved
for igfx use. Stolen memory is required for some functions of the GPU
and display engine,
On Fri, Jul 05, 2013 at 06:53:29PM +0800, Xiong Zhang wrote:
> obj->mm_list link to dev_priv->mm.inactive_list/active_list
> obj->global_list link to dev_priv->mm.unbound_list/bound_list
>
> Signed-off-by: Xiong Zhang
Oh dear have I screwed this up.
This fixes a regression introduced in
commit
On Sunday, June 09, 2013 07:01:39 PM Matthew Garrett wrote:
> Windows 8 leaves backlight control up to individual graphics drivers rather
> than making ACPI calls itself. There's plenty of evidence to suggest that
> the Intel driver for Windows doesn't use the ACPI interface, including the
> fact t
On Fri, Jul 05, 2013 at 10:19:29AM +0100, Chris Wilson wrote:
> On Fri, Jul 05, 2013 at 11:57:21AM +0300, ville.syrj...@linux.intel.com wrote:
> > @@ -2593,10 +2598,11 @@ static void haswell_update_wm(struct drm_device
> > *dev)
> > struct hsw_wm_maximums lp_max_1_2, lp_max_5_6;
> > struct
obj->mm_list link to dev_priv->mm.inactive_list/active_list
obj->global_list link to dev_priv->mm.unbound_list/bound_list
Signed-off-by: Xiong Zhang
---
drivers/gpu/drm/i915/i915_gem.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/driver
dev_priv->mm.gtt_list has been removed. All the gtt are tracked in
dev_pirv->mm.bound_list and dev_priv->mm.unbound_list
Signed-off-by: Xiong Zhang
---
drivers/gpu/drm/i915/i915_gem.c | 63 ---
1 file changed, 39 insertions(+), 24 deletions(-)
diff --git a/
On Fri, Jul 05, 2013 at 10:37:08AM +0100, Chris Wilson wrote:
> On Fri, Jul 05, 2013 at 11:57:42AM +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > There is a major problem with the watermark registers; they're not
> > double buffered. So we need to make sure we update
On Fri, Jul 05, 2013 at 11:57:42AM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> There is a major problem with the watermark registers; they're not
> double buffered. So we need to make sure we update them at the correct
> time when messing about with planes. The correct t
On Fri, Jul 05, 2013 at 11:57:41AM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Passing the appropriate crtc to intel_update_watermarks() should help
> in avoiding needless work in the future.
>
> Also make the call intel_update_watermarks() just once during the
> modese
On Fri, Jul 05, 2013 at 11:57:21AM +0300, ville.syrj...@linux.intel.com wrote:
> @@ -2593,10 +2598,11 @@ static void haswell_update_wm(struct drm_device *dev)
> struct hsw_wm_maximums lp_max_1_2, lp_max_5_6;
> struct hsw_pipe_wm_parameters params[3];
> struct hsw_wm_values results
From: Ville Syrjälä
Print how long watermark programming took. Seems to be ~5 usec on ILK
and IVB at the moment.
---
drivers/gpu/drm/i915/intel_pm.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 782c644..1
From: Ville Syrjälä
Want to see them w/ debugs turned off.
---
drivers/gpu/drm/i915/i915_irq.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 10554bf..a55a231 100644
--- a/drivers/gpu/drm/i915
From: Ville Syrjälä
Don't want to lose them in the noise. Just let them happen.
---
drivers/gpu/drm/i915/i915_irq.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index ee5127f..10554bf 100644
--- a
From: Ville Syrjälä
We're going to want to know the crtc in the watermark code to avoid
doing more work than we have to. We should also pass the plane we're
disabling so that we know where to stick our watermark parameters
without having to go look the plane up.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d2cbc94..782c644 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i9
From: Ville Syrjälä
Let's call hsw_lp_wm_result intel_wm_level from now on and move it to
i915_drv.h for later use.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 8
drivers/gpu/drm/i915/intel_pm.c | 20 ++--
2 files changed, 14 insertions(+), 14 d
From: Ville Syrjälä
The linetime watermarks don't change, except when doing a full modeset,
so having them as part of the full dynamic watermarks code is pointless.
Just move the linetime watermark setup to occur just before enabling the
pipe on HSW, and leave it alone after that.
Signed-off-by
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