Hi all,
Today's linux-next merge of the drm-intel tree got a conflict in
drivers/gpu/drm/i915/intel_dp.c between commit 657445fe8660 ("Revert
"drm/i915: revert eDP bpp clamping code changes"") from Linus' tree and
commits c6bb353815c3 ("drm/i915: move dp clock computations to
encoder->compute_conf
On Fri, 3 May 2013 19:44:07 +0200
Egbert Eich wrote:
> From: Imre Deak
>
> Currently the driver's assumed behavior for a modeset with an attached
> FB is that the corresponding connector will be switched to DPMS ON mode
> if it happened to be in DPMS OFF (or another power save mode). This
> wa
Hi all,
New testing round with a bit fewer patches since I've been travelling
last week. Usual pace should pick up again ;-) Highlights:
- fbc support for Haswell (Rodrigo)
- streamlined workaround comments, including an igt tool to grep for
them (Damien)
- sdvo and TV out cleanups, including a fi
On Thu, May 16, 2013 at 12:57:38PM +0200, brag...@free.fr wrote:
> This patch add dvo detection for the Chrontel 7010B on some old hardware.
>
> References: https://bugzilla.kernel.org/show_bug.cgi?id=55101
> Signed-off-by: Braggle
Looks innocent enough. Queued for -next, thanks for the patch.
-
90% of core speed (=180MHz dot clock) is too high for 2048x1280 to get
pixel doubling on Pineview, which it needs to avoid underruns, so
lower this to 85%.
Signed-off-by: Stuart Abercrombie
---
drivers/gpu/drm/i915/intel_display.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff -
On Thu, May 09, 2013 at 05:13:41PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> We were previously calling sandybridge_update_wm on HSW, but the SNB
> function didn't really match the HSW specification, so we were just
> writing the wrong values. For example, I was not seeing any LP
> wate
On Fri, May 03, 2013 at 05:23:42PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> With this, that 338 can finally become the correct 337500.
>
> Due to the change we need to adjust the intel_dp_aux_ch function to
> set the correct value, so adjust the division and also use
> DIV_ROUND_CLOSE
On Fri, May 03, 2013 at 05:23:43PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> Remove the "placeholder" comment and set the actual value described by
> the specification. We still don't enable IPS, but it won't hurt to
> already have the value set here.
>
> While at it, fully set the reg
On Fri, May 03, 2013 at 05:23:41PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> If we're using DP/eDP, adjusted_mode->clock may be just the port link
> clock, but we also can't use mode->clock because it's wrong when we're
> using the using panel fitter.
>
> Signed-off-by: Paulo Zanoni
On Fri, May 03, 2013 at 05:23:40PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> Move the "*8" calculation to the left side so we don't propagate
> rounding errors. Also use DIV_ROUND_CLOSEST because that's what the
> spec says we need to do.
>
> Signed-off-by: Paulo Zanoni
Reviewed-by:
On Thu, May 09, 2013 at 04:55:50PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> The spec says the linetime watermarks must be programmed before
> enabling any display low power watermarks, but we're currently
> updating the linetime watermarks after we call intel_update_watermarks
> (and o
On Fri, May 03, 2013 at 05:23:39PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> ... instead of mode->crtc_display. The spec says "pipe horizontal
> total number of pixels" and the "Haswell Watermark Calculator" tool
> uses the "Pipe H Total" instead of "Pipe H Src" as the value.
>
> Signe
On Fri, May 03, 2013 at 05:23:37PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> So don't call intel_update_linetime_watermarks from
> ironlake_crtc_mode_set. Only Haswell has these watermarks.
>
> Signed-off-by: Paulo Zanoni
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/int
On Fri, May 03, 2013 at 05:23:44PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> And the SNB_READ_WM0_LATENCY macro is not valid anymore because we
> have the "New WM0" at 63:56, so the "Old WM0" could maybe be zero if
> the new one is not zero.
>
> Signed-off-by: Paulo Zanoni
Reviewed-b
On Fri, May 03, 2013 at 05:23:45PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> Commit 1544d9d57396d5c0c6b7644ed5ae1f4d6caad07a added a workaround
> inside haswell_init_clock_gating and mentioned it is "a workaround for
> early silicon revisions and should be removed later". This workaroun
Hi Jesse,
> -Original Message-
> From: Barnes, Jesse
> Sent: Friday, May 17, 2013 11:44 PM
> To: Wang Xingchao
> Cc: ti...@suse.de; dan...@ffwll.ch; Girdwood, Liam R;
> david.hennings...@canonical.com; Lin, Mengdong; Li, Jocelyn;
> alsa-de...@alsa-project.org; intel-gfx@lists.freedesktop.o
Hi all,
This is V4 and here're some changes notes:
change between V3-->V4:
- add new structure i915_power_well
- initialize drm_device pointer at module init time
- change function name
change between V2-->V3:
- make SND_HDA_I915 selectable
- use snd_printdd to output mes
For Intel Haswell chip, HDA controller and codec have
power well dependency from GPU side. This patch added support
to request/release power well in audio driver. Power save
feature should be enabled to get runtime power saving.
Signed-off-by: Wang Xingchao
---
sound/pci/hda/Kconfig | 10 +
Haswell Display audio depends on power well in graphic side, it should
request power well before use it and release power well after use.
I915 will not shutdown power well if it detects audio is using.
This patch protects display audio crash for Intel Haswell C3 stepping board.
Signed-off-by: Wang
Hi Jesse,
> -Original Message-
> From: Barnes, Jesse
> Sent: Friday, May 17, 2013 11:44 PM
> To: Wang Xingchao
> Cc: ti...@suse.de; dan...@ffwll.ch; Girdwood, Liam R;
> david.hennings...@canonical.com; Lin, Mengdong; Li, Jocelyn;
> alsa-de...@alsa-project.org; intel-gfx@lists.freedesktop.
Here is a system for example:
Pentium M processor with 32bits address pins,
Intel 440FX chip,
A PCI device with 32bits address pins.
See the ascii picture below.
Assume that the pci device BAR0 is in memory space, 10Mb in size.
After initialization, BAR0 is assigned an address. I don't
un
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