On Mon, 29 Apr 2013 19:15:35 +0100
Damien Lespiau wrote:
> This will allow us to explicitely blacklist tests we don't want to run
> on simulation.
>
> Signed-off-by: Damien Lespiau
> ---
> lib/drmtest.c | 12
> lib/drmtest.h | 1 +
> 2 files changed, 13 insertions(+)
>
> diff --
On Mon, Apr 29, 2013 at 07:15:36PM +0100, Damien Lespiau wrote:
> Let's start by a small set of tests, to eventually consider running
> more.
>
> The current list should then be:
>
> gem_mmap
> gem_pread_after_blit
> gem_ring_sync_loop
> gem_ctx_basic
> gem_pipe_control_store_loop
> gem_storedw_l
On Thu, Apr 25, 2013 at 05:24:19PM +0300, Mika Kuoppala wrote:
> Daniel Vetter writes:
>
> > This does duplicate the logic in intel_crtc_mode_get a bit, but the
> > issue is that we also should handle interlace modes and other insanity
> > correctly.
> >
> > Hence I've opted for a sligthly more e
On Thu, Apr 25, 2013 at 01:28:45PM +0300, Jani Nikula wrote:
>
> The version at Daniel's fdi-dither branch (which is without the hack in
> "drm/i915: force bpp for eDP panels") is
>
> Tested-by: Jani Nikula
Meh, I've accidentally merged the broken patch, but that's now fixed
again.
-Daniel
>
On Mon, Apr 29, 2013 at 05:59:53PM +0300, Imre Deak wrote:
> On Mon, 2013-04-29 at 16:43 +0200, Daniel Vetter wrote:
> > On Mon, Apr 29, 2013 at 05:02:20PM +0300, Imre Deak wrote:
> > > On Fri, 2013-04-19 at 11:24 +0200, Daniel Vetter wrote:
[snip]
> > > > @@ -7714,10 +7733,23 @@ intel_modeset_pi
Let's start by a small set of tests, to eventually consider running
more.
The current list should then be:
gem_mmap
gem_pread_after_blit
gem_ring_sync_loop
gem_ctx_basic
gem_pipe_control_store_loop
gem_storedw_loop_render
gem_storedw_loop_blt
gem_storedw_loop_bsd
gem_render_linear_blits
gem_tiled
We tweak the tests marked as runnable in simulation to run more quickly,
more often then not at the expense of stress testing (which is of an
arguable interest for the initial bring up in simulation). Hopefully the
values chosen still test something, which is not always straightforward.
It does ru
This will allow us to explicitely blacklist tests we don't want to run
on simulation.
Signed-off-by: Damien Lespiau
---
lib/drmtest.c | 12
lib/drmtest.h | 1 +
2 files changed, 13 insertions(+)
diff --git a/lib/drmtest.c b/lib/drmtest.c
index 6e5b636..cafc8bc 100644
--- a/lib/drm
It's more accurate this way as the quick mode is really useful for in
the simulation environment.
v2: Use the INTEL_ prefix to have a chance to share the same environment
variable as piglit OpenGL tests
Signed-off-by: Damien Lespiau
---
lib/drmtest.c | 10 +-
lib/drmtest.h | 4 ++--
Otherwise gcc complains that the function hasn't been declared.
---
lib/intel_gpu_tools.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/lib/intel_gpu_tools.h b/lib/intel_gpu_tools.h
index 77aac5d..faa948c 100644
--- a/lib/intel_gpu_tools.h
+++ b/lib/intel_gpu_tools.h
@@ -45,6 +45,8 @@ int
Signed-off-by: Damien Lespiau
---
tools/intel_reg_dumper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/intel_reg_dumper.c b/tools/intel_reg_dumper.c
index 66d05bd..113fd50 100644
--- a/tools/intel_reg_dumper.c
+++ b/tools/intel_reg_dumper.c
@@ -1721,6 +1721,7 @@ DEBUGSTRING(hsw_debu
Also sort them.
Signed-off-by: Damien Lespiau
---
tests/.gitignore | 24 ++--
tools/.gitignore | 5 +
2 files changed, 19 insertions(+), 10 deletions(-)
diff --git a/tests/.gitignore b/tests/.gitignore
index fd30412..b406d0c 100644
--- a/tests/.gitignore
+++ b/tests/.gi
---
lib/intel_chipset.h | 0
1 file changed, 0 insertions(+), 0 deletions(-)
mode change 100755 => 100644 lib/intel_chipset.h
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
old mode 100755
new mode 100644
--
1.8.1.4
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Intel-gfx mailing list
-q will prevent grep from writing to stdout and print "root" when make
test is running as root.
Signed-off-by: Damien Lespiau
---
tests/Makefile.am | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/Makefile.am b/tests/Makefile.am
index 9bc5302..834fb7c 100644
--- a/tests/
To be a bit more correct (they were understandable though).
Signed-off-by: Damien Lespiau
---
README | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/README b/README
index be29177..c484a93 100644
--- a/README
+++ b/README
@@ -27,17 +27,17 @@ tests/
Run this tes
Second installment of this series.
Patches 1-6 are trivial general cleanups I came across while doing this,
patches 7-10 are the real thing.
The changes from the last version are:
• Move from a white list of tests to run to a black list of tests to skip
• Name the environment variable that co
This nicely allows us to drop some hacks which have only been used
to work around modeset failures due to lack of fdi lanes.
v2: Implement proper checking for Haswell platforms - the fdi link to
the LPT PCH has only 2 lanes. Note that we already filter out
impossible modes in intel_crt_mode_valid.
v2: Introduce some nice #defines for the FDI lane width fields and put
them to good use. Suggested by Ville.
v3: Fixup the mask vs. shift copy&pasta fail Imre Deak spotted, and
use the shift #define also in the mask.
Cc: Imre Deak
Cc: Ville Syrjälä
Signed-off-by: Daniel Vetter
---
drivers/gpu
This hack is getting a bit messy, but this plugs the leak for now
until we have the cpu_transcoder properly pipe_config'ed.
Cc: Imre Deak
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_display.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_display.
This hack is getting a bit messy, but this plugs the leak for now
until we have the cpu_transcoder properly pipe_config'ed.
Cc: Imre Deak
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_display.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_display.
According to BSpec the link training sequence for eDP on HSW port-A
should be as follows:
1. link training: clock recovery
2. link training: equalization
3. link training: set idle transmission mode
4. display pipe enable
5. link training: disable (set normal mode)
Contrary to this at the moment
On Sat, 27 Apr 2013 13:35:29 +0200
Daniel Vetter wrote:
> On Sat, Apr 27, 2013 at 09:20:39AM +, Wang, Xingchao wrote:
> > Let me throw a basic proposal on Audio driver side, please give your
> > comments freely.
> >
> > it contains the power well control usage points:
> > #1: audio request
On Mon, 2013-04-29 at 16:43 +0200, Daniel Vetter wrote:
> On Mon, Apr 29, 2013 at 05:02:20PM +0300, Imre Deak wrote:
> > On Fri, 2013-04-19 at 11:24 +0200, Daniel Vetter wrote:
> > > So on a bunch of setups we only have 2 fdi lanes available, e.g. hsw
> > > VGA or 3 pipes on ivb. And seemingly a lo
On Mon, Apr 29, 2013 at 05:02:20PM +0300, Imre Deak wrote:
> On Fri, 2013-04-19 at 11:24 +0200, Daniel Vetter wrote:
> > So on a bunch of setups we only have 2 fdi lanes available, e.g. hsw
> > VGA or 3 pipes on ivb. And seemingly a lot of modes don't quite fit
> > into this, among them the default
On Fri, 2013-04-19 at 11:24 +0200, Daniel Vetter wrote:
> So on a bunch of setups we only have 2 fdi lanes available, e.g. hsw
> VGA or 3 pipes on ivb. And seemingly a lot of modes don't quite fit
> into this, among them the default 1080p mode.
>
> The solution is to dither down the pipe a bit so
On Fri, 2013-04-19 at 11:24 +0200, Daniel Vetter wrote:
> This allows us to use all 4 fdi lanes on fdi B when the cpu eDP is
> running on pipe C. Yay!
>
> v2: Encapsulate test into a little helper function, as suggested by
> Chris Wilson.
>
> Signed-off-by: Daniel Vetter
Reviewed-by: Imre Deak
On Mon, 2013-04-22 at 17:13 +0200, Daniel Vetter wrote:
> This nicely allows us to drop some hacks which have only been used
> to work around modeset failures due to lack of fdi lanes.
>
> v2: Implement proper checking for Haswell platforms - the fdi link to
> the LPT PCH has only 2 lanes. Note th
On Fri, 2013-04-19 at 11:24 +0200, Daniel Vetter wrote:
> Again in preparation to move the configuration checks into the
> pipe_config computation stage of the modeset sequence.
>
> Signed-off-by: Daniel Vetter
Reviewed-by: Imre Deak
> ---
> drivers/gpu/drm/i915/intel_display.c | 31 +
On Fri, 2013-04-19 at 11:24 +0200, Daniel Vetter wrote:
> Now that it's split up, we can easily move it around and precompute
> the fdi lane configuration.
>
> Signed-off-by: Daniel Vetter
Reviewed-by: Imre Deak
> ---
> drivers/gpu/drm/i915/intel_display.c | 71
> +---
On Mon, Apr 29, 2013 at 01:02:55PM +0300, Jani Nikula wrote:
> Enable asle pipestat earlier in i915/i965 irq postinstall to not need
> irq_lock in i915_enable_asle_pipestat().
>
> Signed-off-by: Jani Nikula
Reviewed-by: Damien Lespiau
--
Damien
___
On Mon, Apr 29, 2013 at 01:02:54PM +0300, Jani Nikula wrote:
> Both intel_opregion_enable_asle() and intel_enable_asle() have shrunk
> considerably. Merge them together into a static function in i915_irq.c,
> and rename to better reflect the purpose and the related platforms.
>
> No functional cha
On Mon, Apr 29, 2013 at 12:29:24PM +0100, Damien Lespiau wrote:
> On Mon, Apr 29, 2013 at 01:02:52PM +0300, Jani Nikula wrote:
> > Stop calling intel_opregion_enable_asle() and consequently
> > intel_enable_asle() on opregion init. It should not be necessary for
> > these reasons:
> >
> > 1) On PC
On Mon, Apr 29, 2013 at 01:02:53PM +0300, Jani Nikula wrote:
> Realize that intel_enable_asle() is never called on PCH-split platforms
> or on VLV. Rip out the GSE irq enable for PCH-split platforms, which
> also happens to be incorrect for IVB+.
>
> This should not cause any functional changes.
>
On Mon, Apr 29, 2013 at 01:02:52PM +0300, Jani Nikula wrote:
> Stop calling intel_opregion_enable_asle() and consequently
> intel_enable_asle() on opregion init. It should not be necessary for
> these reasons:
>
> 1) On PCH split platforms, it only enables GSE interrupt, which is
>enabled in i
On Mon, Apr 29, 2013 at 01:02:52PM +0300, Jani Nikula wrote:
> Stop calling intel_opregion_enable_asle() and consequently
> intel_enable_asle() on opregion init. It should not be necessary for
> these reasons:
>
> 1) On PCH split platforms, it only enables GSE interrupt, which is
>enabled in i
On Mon, Apr 29, 2013 at 01:02:51PM +0300, Jani Nikula wrote:
> Only set ASLE driver readiness (ARDY) and technology enabled indicator
> (TCHE) once per opregion init. There should be no need to do that at irq
> postinstall time. Also clear driver readiness at fini.
>
> While at it, add defines for
On Mon, Apr 29, 2013 at 01:02:50PM +0300, Jani Nikula wrote:
> Move near other defines, add TCHE in the name. No functional changes.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Damien Lespiau
--
Damien
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On Wed, 2013-04-24 at 15:30 +0200, Daniel Vetter wrote:
> v2: Introduce some nice #defines for the FDI lane width fields and put
> them to good use. Suggested by Ville.
>
> Cc: Ville Syrjälä
> Signed-off-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/i915_reg.h | 11 +++
> drivers/
On Fri, 2013-04-19 at 11:24 +0200, Daniel Vetter wrote:
> We need this for two reasons:
> - Correct handling of shared fdi lanes on ivb with fastboot.
> - Handling fdi link bw limits when we only have two fdi lanes by
> dithering down a bit.
>
> Just search&replace in this patch, no functional c
On Fri, 2013-04-19 at 11:24 +0200, Daniel Vetter wrote:
> Totally untested due to lack of screens supporting more than 8bpc. But
> now we should have closed all holes in our bpp handling, so this
> should be safe. The last missing piece was 10bpc support for g4x/vlv,
> since we directly use the pip
Stop calling intel_opregion_enable_asle() and consequently
intel_enable_asle() on opregion init. It should not be necessary for
these reasons:
1) On PCH split platforms, it only enables GSE interrupt, which is
enabled in irq postinstall anyway. Moreover, the irq enable uses the
wrong bit on
Enable asle pipestat earlier in i915/i965 irq postinstall to not need
irq_lock in i915_enable_asle_pipestat().
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_irq.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drive
Both intel_opregion_enable_asle() and intel_enable_asle() have shrunk
considerably. Merge them together into a static function in i915_irq.c,
and rename to better reflect the purpose and the related platforms.
No functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h
Realize that intel_enable_asle() is never called on PCH-split platforms
or on VLV. Rip out the GSE irq enable for PCH-split platforms, which
also happens to be incorrect for IVB+.
This should not cause any functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_irq.c | 16
Only set ASLE driver readiness (ARDY) and technology enabled indicator
(TCHE) once per opregion init. There should be no need to do that at irq
postinstall time. Also clear driver readiness at fini.
While at it, add defines for driver readiness.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i9
Move near other defines, add TCHE in the name. No functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_opregion.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_opregion.c
b/drivers/gpu/drm/i915/intel_opreg
This series is a stab at untangling some of the opregion code,
particularly related to opregion asle enable. The only "real" change
should be clearing the driver readiness status in patch 2; otherwise it
*should* be just non-functional cleanup. I've split this up into perhaps
more patches than woul
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