On Wed, Apr 17, 2013 at 03:54:58PM -0700, Jesse Barnes wrote:
> Uses slightly different interfaces than other platforms.
>
> v2: track actual set freq, not requested (Rohit)
> fix debug prints in init code (Jesse)
> v3: don't write sleep reg (Jesse)
> re-add RC6 wake limit write (Ben)
>
On Wed, Apr 17, 2013 at 12:43 AM, 熊 <546496...@qq.com> wrote:
> Yah, you mean the DRI driver i965 does not support my device 945GM ?
> but according to
> https://01.org/linuxgraphics/downloads/2012/2012q4-intel-graphics-stack-release,
> it should support my device.
No, that means that they also te
Periodically check the scratch page to see if it changes. Scratch page
changes almost always indicate something is wrong.
We never expect a non-zero filled page, so potentially we could directly
put that md5 value for checking. I think the code as it is will be a bit
more robust.
Pretty RFC here
From: Pallavi G
For high res modes m n p calculation is fixed for VLV platform.
v2: use 64 bit types and math (Ville)
Signed-off-by: Pallavi G
Signed-off-by: Vijay Purushothaman
Signed-off-by: Yogesh M
Signed-off-by: Gajanan Bhat
---
drivers/gpu/drm/i915/intel_display.c | 25
Just 5 more to go! Daniel, please apply these or I'll be forced to fly
to Europe and hunt you down.
I know 3 and 4 have some coding style issues, but either fix those up
when you apply or let me do that after they're applied as I need to get
my patch count up and don't want to rebase yet again!!!
In Valleyview voltage swing, pre-emphasis and lane control registers can
be programmed only through the h/w side band fabric. Update
vlv_update_pll, i9xx_crtc_enable, and intel_enable_pll with the
appropriate programming.
We need to make sure that the tx lane reset occurs in both the full mode
se
From: Pallavi G
Program few Tx buffer Swing control settings through DPIO.
Signed-off-by: Pallavi G
Signed-off-by: Yogesh M
Signed-off-by: Gajanan Bhat
---
drivers/gpu/drm/i915/intel_display.c |3 +-
drivers/gpu/drm/i915/intel_dp.c | 114 +-
drivers/
Uses slightly different interfaces than other platforms.
v2: track actual set freq, not requested (Rohit)
fix debug prints in init code (Jesse)
v3: don't write sleep reg (Jesse)
re-add RC6 wake limit write (Ben)
fixup thresholds to match other platforms (Ben)
clean up mem freq calc
When requesting frequency changes or querying status from the Punit, we
need to use an opcode that corresponds to the frequency, taking into
account the memory frequency.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.h |2 ++
drivers/gpu/drm/i915/intel_pm.c | 56 +++
From: Paulo Zanoni
This should prevent mode set failures on LPT.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c |5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 413877d..15ff0ac 100644
--- a/dri
On Wed, Apr 17, 2013 at 01:40:56PM -0700, Jesse Barnes wrote:
> On Wed, 17 Apr 2013 20:01:39 +0200
> Daniel Vetter wrote:
>
> > Oops.
> >
> > This regression has been introduced in
> >
> > commit 5d2d38ddcac991f71c19d03d95bde8e14abc0352
> > Author: Daniel Vetter
> > Date: Wed Mar 27 00:45:01
On Wed, Apr 17, 2013 at 11:18:02PM +0300, Imre Deak wrote:
> Also add a subtest for the fd=handle_to_fd(), fd2=dup(fd), close(fd)
> case (idea from Kristian Høgsberg).
>
> Signed-off-by: Imre Deak
>
> v2:
> - add a new subtest instead of modifying the original test (Daniel)
> - add a new subtest
On Wed, 17 Apr 2013 20:01:39 +0200
Daniel Vetter wrote:
> Oops.
>
> This regression has been introduced in
>
> commit 5d2d38ddcac991f71c19d03d95bde8e14abc0352
> Author: Daniel Vetter
> Date: Wed Mar 27 00:45:01 2013 +0100
>
> drm/i915: clean up pipe bpp confusion
>
> Reported-by: Jesse
2013/4/17 :
> This series attempts to make our CEA mode matching recognize both the
> 60Hz and 59.94Hz variants of the modes (and similarly for 24/23.97,
> 30/29.97, etc.).
>
> The benefits should include:
> - Send the correct VIC in the AVI infoframe
> - Pick the correct RGB quantization range in
Also add a subtest for the fd=handle_to_fd(), fd2=dup(fd), close(fd)
case (idea from Kristian Høgsberg).
Signed-off-by: Imre Deak
v2:
- add a new subtest instead of modifying the original test (Daniel)
- add a new subtest for testing dup (Kristian)
---
tests/Makefile.am |2 +-
tests
On Wed, 2013-04-17 at 16:05 -0300, Paulo Zanoni wrote:
> Hi
>
> 2013/4/17 Imre Deak :
> > For the device to enter D3 we should enable PCH clock gating.
> >
> > v2:
> > - use HAS_PCH_LPT instead of IS_HASWELL (Ville, Paolo)
> > - rename lpt_allow_clock_gating to lpt_suspend_hw (Paolo)
> >
>
> s/Pa
Hi
2013/4/17 :
> From: Ville Syrjälä
>
> drm_mode_equal_no_clocks() is like drm_mode_equal() except it doesn't
> compare the clock or vrefresh values. drm_mode_equal() is now
> implemented by first doing the clock checks, and then calling
> drm_mode_equal_no_clocks().
>
> Signed-off-by: Ville Sy
Hi
2013/4/17 Imre Deak :
> For the device to enter D3 we should enable PCH clock gating.
>
> v2:
> - use HAS_PCH_LPT instead of IS_HASWELL (Ville, Paolo)
> - rename lpt_allow_clock_gating to lpt_suspend_hw (Paolo)
>
s/Paolo/Paulo/ :)
Besides this, the patch looks fine. But I can't test it right n
On Wed, Apr 17, 2013 at 03:09:50PM -0300, Paulo Zanoni wrote:
> 2013/4/17 Daniel Vetter :
> > For a bunch of reason we need to more accurately track this:
> > - hw pipe state readout for Haswell needs the cpu transcoder.
> > - We need to know the right cpu transcoder in a bunch of places in
> > -
2013/4/17 Daniel Vetter :
> For a bunch of reason we need to more accurately track this:
> - hw pipe state readout for Haswell needs the cpu transcoder.
> - We need to know the right cpu transcoder in a bunch of places in
> ->disable and other modeset callbacks.
>
> In the future we need to add h
Oops.
This regression has been introduced in
commit 5d2d38ddcac991f71c19d03d95bde8e14abc0352
Author: Daniel Vetter
Date: Wed Mar 27 00:45:01 2013 +0100
drm/i915: clean up pipe bpp confusion
Reported-by: Jesse Barnes
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_display.c
On Wed, 2013-04-17 at 19:06 +0200, Daniel Vetter wrote:
> On Wed, Apr 17, 2013 at 07:10:00PM +0300, Imre Deak wrote:
> > Signed-off-by: Imre Deak
>
> I'm a bit confused what this does ... can you please elaborate?
It creates a second GEM buffer on fd1, exports it, imports it on fd2 and
check if
On Wed, Apr 17, 2013 at 08:04:52PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Instead of locking all modeset locks during plane updates, use just
> a single CRTC mutex. To make that work, track the CRTC that "owns"
> the plane currently. During enable/update that means
On Wed, Apr 17, 2013 at 06:25:29PM +0100, Chris Wilson wrote:
> On Wed, Apr 17, 2013 at 08:11:58PM +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > The docs say that the trickle feed disable bit is present (for primary
> > planes only, not video sprites) on BLC and CTG,
From: Ville Syrjälä
drm_match_cea_mode() should be able to match both the 60Hz version,
and the 59.94Hz version of modes.
We only store one pixel clock value per mode in edid_cea_modes, so the
other value must be calculated. Depending on the mode, edid_cea_modes
contains the pixel clock for eith
From: Ville Syrjälä
Well have use for the vrefresh information of CEA modes later. Just
populate the information into the table to avoid having to calculate
it.
I'm too lazy to check if someone relies on newly allocated CEA
modes having 0 vrefresh, so just clear vrefresh back to 0 when
adding th
From: Ville Syrjälä
drm_mode_equal_no_clocks() is like drm_mode_equal() except it doesn't
compare the clock or vrefresh values. drm_mode_equal() is now
implemented by first doing the clock checks, and then calling
drm_mode_equal_no_clocks().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm
From: Ville Syrjälä
No need to zero initialize .vrefresh in DRM_MODE() since it's using
desgignated initializers.
This will also avoid some duplicate initialization warnings later.
Signed-off-by: Ville Syrjälä
---
include/drm/drm_crtc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
d
This series attempts to make our CEA mode matching recognize both the
60Hz and 59.94Hz variants of the modes (and similarly for 24/23.97,
30/29.97, etc.).
The benefits should include:
- Send the correct VIC in the AVI infoframe
- Pick the correct RGB quantization range in automatic mode
__
On Wed, Apr 17, 2013 at 08:11:58PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> The docs say that the trickle feed disable bit is present (for primary
> planes only, not video sprites) on BLC and CTG, and that it must be set
> for ELK. Just set it for all g4x chipset.
>
From: Ville Syrjälä
The docs say that the trickle feed disable bit is present (for primary
planes only, not video sprites) on BLC and CTG, and that it must be set
for ELK. Just set it for all g4x chipset.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 3 +++
1 file cha
From: Ville Syrjälä
DSPPOS/DSPSIZE for planes A/B doesn't exist on Gen4+, so don't write
them.
Also the pipe selection for planes A and B is only relevant for Gen3
and earlier. Gen4 moved to fixed plane<->pipe mapping. Plane C is
still movable between pipes on Gen4, but that fact is not relevant
From: Ville Syrjälä
According to the docs CTG and BLC have similar video sprites
as ILK/SNB.
This is what the docs say about video sprite features:
CTG and BLC have video sprites, and in addition CTG-B has YUV byte
order selection, live surface registers, and sprite scale registers.
I'm not sur
From: Ville Syrjälä
Gen2-4 have a non-scalable sprite C, which can be assigned to either
pipe A or pipe B dynamically. Expose sprite C as a drm_plame.
I've tested this only on 85x (8086:3582) and 946 (8086:2972).
Gen2/3 chipsets should also be able to re-assign the primary plane B
to act as a s
For a bunch of reason we need to more accurately track this:
- hw pipe state readout for Haswell needs the cpu transcoder.
- We need to know the right cpu transcoder in a bunch of places in
->disable and other modeset callbacks.
In the future we need to add hw state readout&check support, too. B
From: Ville Syrjälä
Instead of locking all modeset locks during plane updates, use just
a single CRTC mutex. To make that work, track the CRTC that "owns"
the plane currently. During enable/update that means the new
CRTC, and during disable it means the old CRTC.
Since the plane state is no long
On Wed, Apr 17, 2013 at 07:10:00PM +0300, Imre Deak wrote:
> Signed-off-by: Imre Deak
I'm a bit confused what this does ... can you please elaborate?
-Daniel
> ---
> tests/prime_self_import.c | 33 ++---
> 1 file changed, 22 insertions(+), 11 deletions(-)
>
> diff
On Wed, Apr 17, 2013 at 08:49:51AM -0700, Jesse Barnes wrote:
> On Tue, 16 Apr 2013 23:09:25 -0700
> Ben Widawsky wrote:
>
> > The sample usage is in reg_access.dpio_read(). We should add some
> > semantics to the text files to detect DPIO registers, and do the right
> > thing.
> >
> > Cc: Jesse
Hi
2013/4/17 Daniel Vetter :
> On Wed, Apr 17, 2013 at 03:43:54PM +0100, Chris Wilson wrote:
>> On Wed, Apr 17, 2013 at 03:31:44PM +0200, Daniel Vetter wrote:
>> > For a bunch of reason we need to more accurately track this:
>> > - hw pipe state readout for Haswell needs the cpu transcoder.
>> > -
Signed-off-by: Imre Deak
---
tests/prime_self_import.c | 33 ++---
1 file changed, 22 insertions(+), 11 deletions(-)
diff --git a/tests/prime_self_import.c b/tests/prime_self_import.c
index 111ed4d..a17e942 100644
--- a/tests/prime_self_import.c
+++ b/tests/prime_se
On Tue, 16 Apr 2013 23:09:25 -0700
Ben Widawsky wrote:
> The sample usage is in reg_access.dpio_read(). We should add some
> semantics to the text files to detect DPIO registers, and do the right
> thing.
>
> Cc: Jesse Barnes
> Signed-off-by: Ben Widawsky
> ---
> tools/quick_dump/Makefile.am
On Tue, Apr 16, 2013 at 01:33:44PM -0300, Rodrigo Vivi wrote:
> This patch introduce Frame Buffer Compression (FBC) support for HSW.
> It adds a new function haswell_enable_fbc to avoid getting
> ironlake_enable_fbc messed with many IS_HASWELL checks.
>
> v2: Fixes from Ville.
> * Fix Plane
On Wed, Apr 17, 2013 at 11:23:41AM -0400, bob295 wrote:
> Thanks for the speedy response.How do I go about upgrading to v3.8? It
> wasn't clear from the website what to do. Am I likely to encounter that
> ./configure problem I had with the intel-gpu-tools?
The answer is to use your dis
On Wed, Apr 17, 2013 at 05:48:46PM +0300, ville.syrj...@linux.intel.com wrote:
> After spotting one open coded pipe_name() some form of OCD kicked in
> and I had to fix it all.
OCD approved, entire pile shovelled on top of dinq.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0
On Wed, Apr 17, 2013 at 03:43:54PM +0100, Chris Wilson wrote:
> On Wed, Apr 17, 2013 at 03:31:44PM +0200, Daniel Vetter wrote:
> > For a bunch of reason we need to more accurately track this:
> > - hw pipe state readout for Haswell needs the cpu transcoder.
> > - We need to know the right cpu trans
On Wed, Apr 17, 2013 at 10:25:42AM -0400, icanprog...@295.ca wrote:
> I'm new to your mailing list, so I'm not sure exactly how to report this.
>
> My KDE system is quite flaky.The Xorg.0.log and dmesg both are reporting
> that my GPU is hung out to dry.I have other issues in KDE, b
On Wed, Apr 17, 2013 at 10:25:42AM -0400, icanprog...@295.ca wrote:
> I'm new to your mailing list, so I'm not sure exactly how to report this.
>
> My KDE system is quite flaky.The Xorg.0.log and dmesg both are reporting
> that my GPU is hung out to dry.I have other issues in KDE, b
From: Ville Syrjälä
Add sprite_name() macro which should be used with the kind of sprites
that are fixed to pipes (gen4.5+).
Also use dev_priv->num_plane to calculate the sprite index insted
assuming two sprites per pipe. This should make it print the right
name.
Signed-off-by: Ville Syrjälä
-
From: Ville Syrjälä
Alway use the alphabetical names in debug/error messages for planes,
pipes and ports, instead of using decimal numbers occasionally.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_ddi.c | 10 -
drivers/gpu/drm/i915/intel_display.c | 42 +
From: Ville Syrjälä
Print the alphabetical name for transcoders. The code already used the
pipe_name() macro for transcoders, so I did the same. But we do have the
(unused) transcoder_name() macro which could be used instead.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.
From: Ville Syrjälä
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0aa2ef0..3af983f 100644
--- a/drivers/gpu/drm/i915
From: Ville Syrjälä
Get rid of the few remaining open coded copies of
pipe_name() and port_name().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/d
After spotting one open coded pipe_name() some form of OCD kicked in
and I had to fix it all.
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Wed, Apr 17, 2013 at 03:31:44PM +0200, Daniel Vetter wrote:
> For a bunch of reason we need to more accurately track this:
> - hw pipe state readout for Haswell needs the cpu transcoder.
> - We need to know the right cpu transcoder in a bunch of places in
> ->disable and other modeset callback
For a bunch of reason we need to more accurately track this:
- hw pipe state readout for Haswell needs the cpu transcoder.
- We need to know the right cpu transcoder in a bunch of places in
->disable and other modeset callbacks.
In the future we need to add hw state readout&check support, too. B
On Wed, Apr 17, 2013 at 11:04:23AM +0200, Daniel Vetter wrote:
> Hi Paulo,
>
> On Fri, Mar 22, 2013 at 02:14:13PM -0300, Paulo Zanoni wrote:
> > From: Paulo Zanoni
> >
> > It returns true if we've requested to turn the power well on and it's
> > really on. It also returns true for all the previous
For the device to enter D3 we should enable PCH clock gating.
v2:
- use HAS_PCH_LPT instead of IS_HASWELL (Ville, Paolo)
- rename lpt_allow_clock_gating to lpt_suspend_hw (Paolo)
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/i915_drv.c |2 ++
drivers/gpu/drm/i915/i915_drv.h |
If context has recently submitted a faulty batchbuffers guilty of
gpu hang and decides to keep submitting more crap, ban it permanently.
v2: Store guilty ban status bool in gpu_error instead of pointers
that might become danling before hang is declared.
v3: Use return value for banned status
Hi Paulo,
On Fri, Mar 22, 2013 at 02:14:13PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> It returns true if we've requested to turn the power well on and it's
> really on. It also returns true for all the previous gens.
>
> For now there's just one caller, but I'm going to add more.
>
>On Wed, Apr 17, 2013 at 02:34:30PM +0800, ?? wrote:
>>Hi All,
>>
>> I am working for video accelerating for intel card (945GM), but the
> > driver can not run well. Please help me .
> >
> >1. vainfo
>> libva info: VA-API version 0.33.0
>>
On Tue, Apr 16, 2013 at 01:47:44PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> This patch implements "Display Sequences for Package C8", from the
> "Display Mode Set Sequence" section from the Haswell documentation.
>
> Signed-off-by: Paulo Zanoni
> ---
>
> Hi
>
> This patch was teste
On Wed, Apr 17, 2013 at 02:34:30PM +0800, 熊 wrote:
>Hi All,
>
> I am working for video accelerating for intel card (945GM), but the
>driver can not run well. Please help me .
>
> 1. vainfo
> libva info: VA-API version 0.33.0
> libva inf
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