Hi All,
I am working for video accelerating for intel card (945GM), but the
driver can not run well. Please help me .
1. vainfo
libva info: VA-API version 0.33.0
libva info: va_getDriverName() returns 0
libva info: Trying to open /usr/lib/dri
The sample usage is in reg_access.dpio_read(). We should add some
semantics to the text files to detect DPIO registers, and do the right
thing.
Cc: Jesse Barnes
Signed-off-by: Ben Widawsky
---
tools/quick_dump/Makefile.am | 3 ++-
tools/quick_dump/chipset.i | 2 ++
tools/quick_dump/reg_ac
On Tue, Apr 16, 2013 at 2:49 PM, Ville Syrjälä <
ville.syrj...@linux.intel.com> wrote:
> On Tue, Apr 16, 2013 at 01:33:44PM -0300, Rodrigo Vivi wrote:
> > This patch introduce Frame Buffer Compression (FBC) support for HSW.
> > It adds a new function haswell_enable_fbc to avoid getting
> > ironlak
On Tue, Apr 16, 2013 at 10:22 PM, Egbert Eich wrote:
> On Tue, Apr 16, 2013 at 08:07:09PM +0200, Daniel Vetter wrote:
>> On Tue, Apr 16, 2013 at 01:36:58PM +0200, Egbert Eich wrote:
>> > We disable hoptplug detection when we encounter a hotplug event
>> > storm. Still hotplug detection is required
On Tue, Apr 16, 2013 at 08:07:09PM +0200, Daniel Vetter wrote:
> On Tue, Apr 16, 2013 at 01:36:58PM +0200, Egbert Eich wrote:
> > We disable hoptplug detection when we encounter a hotplug event
> > storm. Still hotplug detection is required on some outputs (like
> > Display Port). The interrupt sto
Hi,
On 16.04.2013 09:50, Zhigang Gong wrote:
> [Gong, Zhigang] As I know, Simon implemented ICD for Beignet and it may need
> some time to rebase to the latest beignet code base.
> If you are interested, this is the link http://psi5.com/~geier/beignet.git.
I've rebased on top of the release 0.1
On Tue, 2013-04-16 at 14:50 -0300, Paulo Zanoni wrote:
> 2013/4/16 Imre Deak :
> > On Tue, 2013-04-16 at 14:35 +0300, Ville Syrjälä wrote:
> >> On Tue, Apr 16, 2013 at 02:25:16PM +0300, Imre Deak wrote:
> >> > For the device to enter D3 we should enable PCH clock gating.
> >> >
> >> > Signed-off-by
On Wed, Apr 10, 2013 at 06:23:25PM +0300, Imre Deak wrote:
> On Mon, 2013-04-08 at 15:48 -0300, Paulo Zanoni wrote:
> > From: Paulo Zanoni
> >
> > Bits 30 and 24:0 are PBC, so don't zero them. Some of the other bits
> > are being zeroed, but I couldn't find a reason for this, so leave them
> > as
On Tue, Apr 16, 2013 at 01:36:58PM +0200, Egbert Eich wrote:
> We disable hoptplug detection when we encounter a hotplug event
> storm. Still hotplug detection is required on some outputs (like
> Display Port). The interrupt storm may be only temporary (on certain
> Dell Laptops for instance it hap
2013/4/16 Imre Deak :
> On Tue, 2013-04-16 at 14:35 +0300, Ville Syrjälä wrote:
>> On Tue, Apr 16, 2013 at 02:25:16PM +0300, Imre Deak wrote:
>> > For the device to enter D3 we should enable PCH clock gating.
>> >
>> > Signed-off-by: Imre Deak
>> > ---
>> > drivers/gpu/drm/i915/i915_drv.c |
On Tue, Apr 16, 2013 at 01:33:44PM -0300, Rodrigo Vivi wrote:
> This patch introduce Frame Buffer Compression (FBC) support for HSW.
> It adds a new function haswell_enable_fbc to avoid getting
> ironlake_enable_fbc messed with many IS_HASWELL checks.
>
> v2: Fixes from Ville.
> * Fix Plane
On Tue, Apr 16, 2013 at 3:41 PM, Paulo Zanoni wrote:
>> All patches merged to dinq, thanks.
>
> I thought patch 2 would go to -fixes. We need it even for older Kernels.
>
This late in the release cycle -fixes is for severe regressions and
black-screen level non-regression issues only. Hence merge
From: Paulo Zanoni
This patch implements "Display Sequences for Package C8", from the
"Display Mode Set Sequence" section from the Haswell documentation.
Signed-off-by: Paulo Zanoni
---
Hi
This patch was tested and the machines do enter C8+, so it shows our driver is
not preventing C8+. There
This patch introduce Frame Buffer Compression (FBC) support for HSW.
It adds a new function haswell_enable_fbc to avoid getting
ironlake_enable_fbc messed with many IS_HASWELL checks.
v2: Fixes from Ville.
* Fix Plane. FBC is tied to primary plane A in HSW
* Fix DPFC initial writ
On 04/15/2013 05:52 PM, Chad Versace wrote:
Signed-off-by: Chad Versace
---
intel/intel_chipset.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index b73fa0f..da2fbee 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_ch
Hi Nanhai,
I'm a developer for AMD working on an Open Source OpenCL implementation
for our GPUs. I am very familiar with a number of the active Open
Source OpenCL projects, and I have a few comments:
> It is not really true to say that the code is duplicated.
>
Have you done a survey of a
On Mon, 15 Apr 2013 21:48:03 -0700
Ben Widawsky wrote:
> Caused by me with v2 of
>
> commit 219f4fdbed5570f1d2e8da0af1c298dd3622060e
> Author: Ben Widawsky
> Date: Fri Mar 15 11:17:54 2013 -0700
>
> drm/i915: Introduce GEN7_FEATURES for device info
>
> I don't have a VLV to test it with
On Tue, Apr 16, 2013 at 06:16:10PM +0300, Ville Syrjälä wrote:
> On Tue, Apr 16, 2013 at 03:49:58PM +0100, Chris Wilson wrote:
[snip]
> > Dare I ask you to split patch 4 so that you
> > can convince me with a solid changelog?
>
> So you'd like me to implement strict checks first, and then relax th
On Tue, Apr 16, 2013 at 03:49:58PM +0100, Chris Wilson wrote:
> On Tue, Apr 16, 2013 at 05:14:14PM +0300, Ville Syrjälä wrote:
> > On Tue, Apr 16, 2013 at 02:42:34PM +0100, Chris Wilson wrote:
> > > On Tue, Apr 16, 2013 at 01:47:20PM +0300, ville.syrj...@linux.intel.com
> > > wrote:
> > > > diff -
This patch introduce Frame Buffer Compression (FBC) support for HSW.
It adds a new function haswell_enable_fbc to avoid getting
ironlake_enable_fbc messed with many IS_HASWELL checks.
v2: Fixes from Ville.
* Fix Plane. FBC is tied to primary plane A in HSW
* Fix DPFC initial writ
On Tue, Apr 16, 2013 at 05:14:14PM +0300, Ville Syrjälä wrote:
> On Tue, Apr 16, 2013 at 02:42:34PM +0100, Chris Wilson wrote:
> > On Tue, Apr 16, 2013 at 01:47:20PM +0300, ville.syrj...@linux.intel.com
> > wrote:
> > > diff --git a/include/drm/drm_rect.h b/include/drm/drm_rect.h
> > > index 2b727
On Tue, Apr 16, 2013 at 02:37:24PM +0100, Chris Wilson wrote:
> On Tue, Apr 16, 2013 at 01:47:22PM +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Properly clip the source when the destination gets clipped
> > by the pipe dimensions.
> >
> > Sadly the video sprite har
On Tue, Apr 16, 2013 at 02:42:34PM +0100, Chris Wilson wrote:
> On Tue, Apr 16, 2013 at 01:47:20PM +0300, ville.syrj...@linux.intel.com wrote:
> > diff --git a/include/drm/drm_rect.h b/include/drm/drm_rect.h
> > index 2b7278c..de24f16 100644
> > --- a/include/drm/drm_rect.h
> > +++ b/include/drm/dr
On Tue, Apr 16, 2013 at 02:32:13PM +0300, Mika Kuoppala wrote:
> If context has recently submitted a faulty batchbuffers guilty of
> gpu hang and decides to keep submitting more crap, ban it permanently.
>
> v2: Store guilty ban status bool in gpu_error instead of pointers
> that might become
uhm, got your point... I'm getting exactly this values, because fence
number is 0 here,
so it is a coincidence and I should remove obj->fence_reg of FBC_CTL set,
right?
On Tue, Apr 16, 2013 at 10:37 AM, Ville Syrjälä <
ville.syrj...@linux.intel.com> wrote:
> On Tue, Apr 16, 2013 at 10:23:17AM
On Tue, Apr 16, 2013 at 01:47:20PM +0300, ville.syrj...@linux.intel.com wrote:
> diff --git a/include/drm/drm_rect.h b/include/drm/drm_rect.h
> index 2b7278c..de24f16 100644
> --- a/include/drm/drm_rect.h
> +++ b/include/drm/drm_rect.h
> @@ -128,5 +128,17 @@ bool drm_rect_intersect(struct drm_rect
Hi
2013/4/16 Daniel Vetter :
> On Mon, Apr 15, 2013 at 09:45:00PM +0100, Chris Wilson wrote:
>> On Fri, Apr 12, 2013 at 06:16:53PM -0300, Paulo Zanoni wrote:
>> > From: Paulo Zanoni
>> >
>> > We may have DDI_BUF_CTL(PORT_A) configured with 2 lanes and still not
>> > have CRT, so just check for !I
On Tue, Apr 16, 2013 at 10:23:17AM -0300, Rodrigo Vivi wrote:
> Yeah, this makes sense. Yes, I tested many times here, with 0 at bit 28 I
> always got that bug with missing updates, In the way it is it always worked
> fine.
So did you actually test with this config?
FBC_CTL
28 = 1
0:3 = 0
DPFC_C
On Tue, Apr 16, 2013 at 01:47:22PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Properly clip the source when the destination gets clipped
> by the pipe dimensions.
>
> Sadly the video sprite hardware is rather limited so it can't do proper
> sub-pixel postitioning. Reso
This patch introduce Frame Buffer Compression (FBC) support for HSW.
It adds a new function haswell_enable_fbc to avoid getting
ironlake_enable_fbc messed with many IS_HASWELL checks.
v2: Fixes from Ville.
* Fix Plane. FBC is tied to primary plane A in HSW
* Fix DPFC initial writ
Yeah, this makes sense. Yes, I tested many times here, with 0 at bit 28 I
always got that bug with missing updates, In the way it is it always worked
fine.
On Tue, Apr 16, 2013 at 7:28 AM, Ville Syrjälä <
ville.syrj...@linux.intel.com> wrote:
> On Mon, Apr 15, 2013 at 06:14:46PM -0300, Rodrigo V
Zou, Nanhai intel.com> writes:
>
> Hi,
> We have just released the open source Linux OpenCL project
Beignet Version 0.1.
>
> If you are interested in this project. Please try it and provide feedback
to us.
> We welcome developers to join this project.
It appears that CMakeLists.txt
On Tue, 2013-04-16 at 14:35 +0300, Ville Syrjälä wrote:
> On Tue, Apr 16, 2013 at 02:25:16PM +0300, Imre Deak wrote:
> > For the device to enter D3 we should enable PCH clock gating.
> >
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/i915_drv.c |2 ++
> > drivers/gpu/drm/
Instead of calling into the DRM helper layer to poll all connectors for
changes in connected displays probe only those connectors which have
received a hotplug event.
Signed-off-by: Egbert Eich
Reviewed-by: Jani Nikula
v2: Resolved conflicts with changes in previous commits.
Renamed functio
This allows to add code which limits 're'-detect() of displays to connectors
that have received an HPD event.
v2: Reordered drm_i915_private: Move hpd_event_bits to hpd state tracking.
v3: Fixed merge conflicts with previous patches, removed some noisy debug
logging as suggested by Jani Nikula
We disable hoptplug detection when we encounter a hotplug event
storm. Still hotplug detection is required on some outputs (like
Display Port). The interrupt storm may be only temporary (on certain
Dell Laptops for instance it happens at certain charging states of
the system). Thus we enable it aft
This patch disables hotplug interrupts if an 'interrupt storm'
has been detected.
Noise on the interrupt line renders the hotplug interrupt useless:
each hotplug event causes the devices to be rescanned which will
will only increase the system load.
Thus disable the hotplug interrupts and fall back
To disable previously enabled HPD IRQs we need to reset them and
set the enabled ones individually.
Signed-off-by: Egbert Eich
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_irq.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i91
When an encoder is shared on several connectors there is only
one hotplug line, thus this line needs to be shared among these
connectors.
If HPD detect only works reliably on a subset of those connectors,
we want to poll the others. Thus we need to make sure that storm
detection doesn't mess up the
Add a hotplug IRQ storm detection (triggered when a hotplug interrupt
fires more than 5 times / sec).
Rationale:
Despite of the many attempts to fix the problem with noisy hotplug
interrupt lines we are still seeing systems which have issues:
Once cause of noise seems to be bad routing of the hotpl
On Tue, Apr 16, 2013 at 02:25:16PM +0300, Imre Deak wrote:
> For the device to enter D3 we should enable PCH clock gating.
>
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/i915_drv.c |2 ++
> drivers/gpu/drm/i915/i915_drv.h |1 +
> drivers/gpu/drm/i915/intel_display.c
Hi Jani,
I've rebased and regenerated all the patches now, as there
were some other bikesheds i had not adressed. I've also
included all Reviewed-By:
This should make it easier to integrate the patches.
Some comments below:
On Thu, Apr 11, 2013 at 12:32:29PM +0300, Jani Nikula wrote:
> > +
If context has recently submitted a faulty batchbuffers guilty of
gpu hang and decides to keep submitting more crap, ban it permanently.
v2: Store guilty ban status bool in gpu_error instead of pointers
that might become danling before hang is declared.
Signed-off-by: Mika Kuoppala
---
driv
For the device to enter D3 we should enable PCH clock gating.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/i915_drv.c |2 ++
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/intel_display.c |5 +
drivers/gpu/drm/i915/intel_drv.h |1 +
drivers/gpu/
From: Ville Syrjälä
Properly clip the source when the destination gets clipped
by the pipe dimensions.
Sadly the video sprite hardware is rather limited so it can't do proper
sub-pixel postitioning. Resort to truncating the source coordinates to
(macro)pixel boundary.
The scaling checks are don
From: Ville Syrjälä
Add a debug function to print the rectangle in a human readable format.
v2: Renamed drm_region to drm_rect, the function from drm_region_debug
to drm_rect_debug_print(), and use %+d instead of +%d in the format.
v3: Use %d format for width/height in the non fixed point ca
From: Ville Syrjälä
These functions calculcate the scaling factor based on the source and
destination rectangles.
There are two version of the functions, the strict ones that will
return an error if the min/max scaling factor is exceeded, and the
relaxed versions that will adjust the src/dst rec
From: Ville Syrjälä
struct drm_rect represents a simple rectangle. The utility
functions are there to help driver writers.
v2: Moved the region stuff into its own file, made the smaller funcs
static inline, used 64bit maths in the scaled clipping function to
avoid overflows (instead it w
I'm re-sending this whole plane clipping series, as it has been a quite
while since the last time I posted it.
Laurent went through patch 1 and I made the requested changes, and I also
fixed a minor issue in patch 3 that I spotted myself.
The other patches are unchanged and looking for volunteers
On Mon, Apr 15, 2013 at 06:14:46PM -0300, Rodrigo Vivi wrote:
> On Wed, Apr 10, 2013 at 5:18 AM, Ville Syrjälä <
> ville.syrj...@linux.intel.com> wrote:
>
> > On Tue, Apr 09, 2013 at 03:13:10PM -0300, Rodrigo Vivi wrote:
> > > On Tue, Apr 9, 2013 at 5:35 AM, Ville Syrjälä <
> > ville.syrj...@linux
Hi Jani,
On Thu, Apr 11, 2013 at 12:32:29PM +0300, Jani Nikula wrote:
>
> Hi Egbert -
>
> Up front, I haven't been following this series or read any of the
> previous review comments. Please bear with me, and feel free to direct
> me to earlier comments if I'm in contradiction.
Sorry for the la
On Mon, Apr 15, 2013 at 09:45:00PM +0100, Chris Wilson wrote:
> On Fri, Apr 12, 2013 at 06:16:53PM -0300, Paulo Zanoni wrote:
> > From: Paulo Zanoni
> >
> > We may have DDI_BUF_CTL(PORT_A) configured with 2 lanes and still not
> > have CRT, so just check for !IS_ULT. This problem happened on a re
On Mon, Apr 15, 2013 at 08:56:28PM -0300, Rodrigo Vivi wrote:
> This patch introduce Frame Buffer Compression (FBC) support for HSW.
> It adds a new function haswell_enable_fbc to avoid getting
> ironlake_enable_fbc messed with many IS_HASWELL checks.
>
> v2: Fixes from Ville.
> * Fix Plane
On Tue, Apr 16, 2013 at 08:52:16AM +0100, Chris Wilson wrote:
> On Mon, Apr 15, 2013 at 09:48:03PM -0700, Ben Widawsky wrote:
> > Caused by me with v2 of
> >
> > commit 219f4fdbed5570f1d2e8da0af1c298dd3622060e
> > Author: Ben Widawsky
> > Date: Fri Mar 15 11:17:54 2013 -0700
> >
> > drm/i9
On Mon, Apr 15, 2013 at 09:48:03PM -0700, Ben Widawsky wrote:
> Caused by me with v2 of
>
> commit 219f4fdbed5570f1d2e8da0af1c298dd3622060e
> Author: Ben Widawsky
> Date: Fri Mar 15 11:17:54 2013 -0700
>
> drm/i915: Introduce GEN7_FEATURES for device info
>
> I don't have a VLV to test it
> -Original Message-
> From:
> intel-gfx-bounces+zhigang.gong=linux.intel@lists.freedesktop.org
> [mailto:intel-gfx-bounces+zhigang.gong=linux.intel.com@lists.freedesktop.
> org] On Behalf Of Zou, Nanhai
> Sent: Tuesday, April 16, 2013 2:47 PM
> To: Dave Airlie
> Cc: intel-gfx@lists.f
On Fri, Apr 12, 2013 at 07:10:13PM +0100, Chris Wilson wrote:
> Haswell introduces a separate frequency domain for the ring (uncore). So
> where we used to increase the CPU (IA) clock with GPU busyness, we now
> need to scale the ring frequency directly instead. As the ring limits
> our memory band
On Fri, Apr 12, 2013 at 11:00:20AM -0700, Kees Cook wrote:
> On Fri, Apr 12, 2013 at 2:10 AM, Mika Kuoppala
> wrote:
> > commit 647416f9eefe7699754b01b9fc82758fde83248c
> > Author: Kees Cook
> > Date: Sun Mar 10 14:10:06 2013 -0700
> >
> > drm/i915: use simple attribute in debugfs routines
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