Increase the RC6p threshold from 10 to 15, there is no power difference
between the two values.
for example:
(1) I915_WRITE(GEN6_RC6p_THRESHOLD, 10);
video time: 11'
video avg watt 31.3
watt-hour: 5.6
(2) I915_WRITE(GEN6_RC6p_THRESHOLD, 15);
video time: 11'
video avg watt 31.2
wat
On 02/26/2013 05:47 PM, Ian Romanick wrote:
On 02/26/2013 03:05 AM, Mika Kuoppala wrote:
For arb-robustness, every context needs to have it's own
reset state tracking. Default context will be handled in a identical
way as the no-context case in further down in the patch set.
For no-context case,
On 02/26/2013 03:05 AM, Mika Kuoppala wrote:
For arb-robustness, every context needs to have it's own
reset state tracking. Default context will be handled in a identical
way as the no-context case in further down in the patch set.
For no-context case, the reset state will be stored in
the file_p
On Tue, Feb 26, 2013 at 01:05:08PM +0200, Mika Kuoppala wrote:
> In preparation to track per ring progress in hangcheck,
> add i915_hangcheck_ring_hung.
>
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_irq.c | 31 +++
> 1 file changed, 19 insertion
Hi
2013/2/26 Paulo Zanoni :
> Hi
>
> 2013/2/25 Rodrigo Vivi :
>> Yet according to pm spec pcode read/write operations
>> aren't necessary for HSW.
>>
>> Signed-off-by: Rodrigo Vivi
>
> Reviewed-by: Paulo Zanoni
Where's the "undo send email" button?
drivers/gpu/drm/i915/intel_pm.c:2674:9: warni
On Tue, Feb 26, 2013 at 01:05:06PM +0200, Mika Kuoppala wrote:
> In preparation for next commit, pass seqno as a parameter
> to i915_hangcheck_ring_idle as it will be used inside
> i915_hangcheck_elapsed.
>
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_irq.c | 11 +++
Hi
2013/2/25 Rodrigo Vivi :
> Yet according to pm spec pcode read/write operations
> aren't necessary for HSW.
>
> Signed-off-by: Rodrigo Vivi
Reviewed-by: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/intel_pm.c | 26 --
> 1 file changed, 26 deletions(-)
>
> diff --git a/
Hi
2013/2/25 Rodrigo Vivi :
> According to HSW PM Programming guide it is not needed touch this registers
> or setting these values anymore.
>
> Signed-off-by: Rodrigo Vivi
Reviewed-by: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/intel_pm.c | 11 ++-
> 1 file changed, 2 insertions(+), 9
On Tue, Feb 26, 2013 at 01:05:05PM +0200, Mika Kuoppala wrote:
> In preparation to do analysis of which context was
> guilty of gpu hung, store kreffed context pointer
> into request struct.
>
> This allows us to inspect contexts when gpu is reset
> even if those contexts would already be released
Hi
2013/2/25 Rodrigo Vivi :
> According to HSW PM programming guide, frequency bits starts at
> 24 instead of 25
This looks incomplete. Please check all the cases where RPNSWREQ is
used, I think we need to fix them too. Also, according to the PM
programming guide, all the other RPNSWREQ bits are
Hi
2 comments below:
2013/2/25 Rodrigo Vivi :
> Power management, in special RC6 enabling, differs across platforms.
> This patch just split out enabling function for HSW.
>
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_pm.c | 158
>
>
On Tue, Feb 26, 2013 at 01:05:04PM +0200, Mika Kuoppala wrote:
> In preparation for the next commit, return context that
> was switch to from i915_switch_context().
>
> Signed-off-by: Mika Kuoppala
I'd suggest using ERR_PTR and PTR_ERR instead of the **ctx
> ---
> drivers/gpu/drm/i915/i915_drv
Hi
2013/2/21 Daniel Vetter :
> Now that we have a useful struct for this, let's use it. Some neat
> pointer-chasing required, but it's all there already.
>
> v2: Rebased on top of the added Haswell limited color range support.
>
> Signed-off-by: Daniel Vetter
This one looks good, except for the
Hi
A few chunks down below:
2013/2/21 Daniel Vetter :
> This is used way too often in the enable/disable paths. And will
> be even more useful in the future.
>
> Note that correct semantics of this change highly depend upon
> correct updating of intel_crtc->config: Like with all other
> modeset s
Hi
2013/2/21 Daniel Vetter :
> Used by SDVO (and hopefully, eventually HDMI, if we ever get around
> to fixing up the low dotclock CEA modes ...).
>
> This required adding a new encoder->mode_set callback to be able to
> pass around the intel_crtc_config.
Again, can we please separate the callbac
Hi
2013/2/21 Daniel Vetter :
> Only used by the lvds encoder. Note that we shouldn't do the same
> simple conversion with the FORCE_6BPC flag, since that's much better
> handled by moving all the pipe_bpc computation around.
>
> Signed-off-by: Daniel Vetter
In addition to Ville's question (which
Hi
2013/2/21 Daniel Vetter :
> To make decent modeset state checking possible (e.g. for the check
> mode with atomic modesetting) we want to have the full pipe
> configuration and state checks done before we touch the hw.
>
> To ensure that all the little bits&pieces that are now moved to the
> pi
Hi
2013/2/22 Daniel Vetter :
> Currently only containing the requested and the adjusted mode. And
> only crtc callbacks are converted somewhat to it, encoders will be
> done on a as-needed basis (simply too much churn in one patch
> otherwise).
>
> Future patches will add tons more useful stuff to
On Tue, Feb 26, 2013 at 05:09:03PM +0200, Mika Kuoppala wrote:
> Chris Wilson writes:
>
> > On Tue, Feb 26, 2013 at 01:05:07PM +0200, Mika Kuoppala wrote:
> >> Instead of relying in acthd, track ring seqno progression
> >> to detect if ring has hung.
> >
> > This needs a comment that it has a use
Chris Wilson writes:
> On Tue, Feb 26, 2013 at 01:05:07PM +0200, Mika Kuoppala wrote:
>> Instead of relying in acthd, track ring seqno progression
>> to detect if ring has hung.
>
> This needs a comment that it has a user visible side-effect of limiting
> batches to a maximum of 1.5s runtime. Bef
On Mon, Feb 25, 2013 at 07:55:18PM -0300, Rodrigo Vivi wrote:
> From: Shobhit Kumar
>
> Signed-off-by: Shobhit Kumar
>
> v2: reuse of just created is_edp_psr and put it at right place.
>
> Signed-off-by: Rodrigo Vivi
> Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_dp.c | 13 +
On Mon, Feb 25, 2013 at 07:55:20PM -0300, Rodrigo Vivi wrote:
> Adding Enable and Disable PSR functionalities. This includes setting the
> PSR configuration over AUX, sending SDP VSC DIP over the eDP PIPE config,
> enabling PSR in the sink via DPCD register and finally enabling PSR on
> the host.
>
On Tue, Feb 26, 2013 at 3:35 PM, Chris Wilson wrote:
> On Tue, Feb 26, 2013 at 03:27:52PM +0100, Sedat Dilek wrote:
>> The comment was introduced with...
>>
>> commit 528dbf9ebb2688f476ef283be59d0f2232159dcb
>> "sna: Fix build on older GCC for cpuid()"
>>
>> ...and is a bit misleading.
>
> The com
On Tue, Feb 26, 2013 at 03:27:52PM +0100, Sedat Dilek wrote:
> The comment was introduced with...
>
> commit 528dbf9ebb2688f476ef283be59d0f2232159dcb
> "sna: Fix build on older GCC for cpuid()"
>
> ...and is a bit misleading.
The comment was a reminder to me as to whether I needed to check
__gnu
The comment was introduced with...
commit 528dbf9ebb2688f476ef283be59d0f2232159dcb
"sna: Fix build on older GCC for cpuid()"
...and is a bit misleading.
[ v2: Point to compatibility with gcc-v4 (e.g. clang) ]
Signed-off-by: Sedat Dilek
---
src/sna/sna_cpu.c | 2 +-
1 file changed, 1 insertion
On Tue, Feb 26, 2013 at 03:11:50PM +0100, Sedat Dilek wrote:
> On Tue, Feb 26, 2013 at 2:50 PM, Chris Wilson
> wrote:
> > On Tue, Feb 26, 2013 at 02:38:14PM +0100, Sedat Dilek wrote:
> >> On Tue, Feb 26, 2013 at 2:33 PM, Chris Wilson
> >> wrote:
> >> > On Tue, Feb 26, 2013 at 02:20:26PM +0100,
The comment was introduced with...
commit 528dbf9ebb2688f476ef283be59d0f2232159dcb
"sna: Fix build on older GCC for cpuid()"
...and is a bit misleading.
Signed-off-by: Sedat Dilek
---
src/sna/sna_cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/sna/sna_cpu.c b/src/
On Tue, Feb 26, 2013 at 01:05:14PM +0200, Mika Kuoppala wrote:
> In order to track down a batch buffer and context which
> caused the ring to hang, store reference to bo and context
> into the request struct. Request can also cause gpu to hang
> after the batch in the flush section in the ring. To
On Tue, Feb 26, 2013 at 01:05:09PM +0200, Mika Kuoppala wrote:
> Add per ring score of possible culprit for gpu hang. If
> ring is busy and not waiting, it will get the highest score
> across calls to i915_hangcheck_elapsed. This way we are
> most likely to find the ring that caused the hang among
Signed-off-by: Sedat Dilek
---
src/sna/sna_damage.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/sna/sna_damage.c b/src/sna/sna_damage.c
index ab693af..53ed635 100644
--- a/src/sna/sna_damage.c
+++ b/src/sna/sna_damage.c
@@ -410,7 +410,7 @@ static void __sna_damage
On Tue, Feb 26, 2013 at 01:05:07PM +0200, Mika Kuoppala wrote:
> Instead of relying in acthd, track ring seqno progression
> to detect if ring has hung.
This needs a comment that it has a user visible side-effect of limiting
batches to a maximum of 1.5s runtime. Before, that limit was softer in
th
On Tue, Feb 26, 2013 at 2:50 PM, Chris Wilson wrote:
> On Tue, Feb 26, 2013 at 02:38:14PM +0100, Sedat Dilek wrote:
>> On Tue, Feb 26, 2013 at 2:33 PM, Chris Wilson
>> wrote:
>> > On Tue, Feb 26, 2013 at 02:20:26PM +0100, Sedat Dilek wrote:
>> >> On Tue, Feb 26, 2013 at 1:58 PM, Chris Wilson
>
On Tue, Feb 26, 2013 at 02:38:14PM +0100, Sedat Dilek wrote:
> On Tue, Feb 26, 2013 at 2:33 PM, Chris Wilson
> wrote:
> > On Tue, Feb 26, 2013 at 02:20:26PM +0100, Sedat Dilek wrote:
> >> On Tue, Feb 26, 2013 at 1:58 PM, Chris Wilson
> >> wrote:
> >> > On Tue, Feb 26, 2013 at 01:35:51PM +0100,
On Tue, Feb 26, 2013 at 2:33 PM, Chris Wilson wrote:
> On Tue, Feb 26, 2013 at 02:20:26PM +0100, Sedat Dilek wrote:
>> On Tue, Feb 26, 2013 at 1:58 PM, Chris Wilson
>> wrote:
>> > On Tue, Feb 26, 2013 at 01:35:51PM +0100, Sedat Dilek wrote:
>> >> With xf86-video-intel-git13461a1 [1] I see this:
On Tue, Feb 26, 2013 at 02:20:26PM +0100, Sedat Dilek wrote:
> On Tue, Feb 26, 2013 at 1:58 PM, Chris Wilson
> wrote:
> > On Tue, Feb 26, 2013 at 01:35:51PM +0100, Sedat Dilek wrote:
> >> With xf86-video-intel-git13461a1 [1] I see this:
> >>
> >> [ build-log ]
> >> ...
> >> CC sna_cpu.lo
>
On Tue, 26 Feb 2013, Rodrigo Vivi wrote:
> Adding Enable and Disable PSR functionalities. This includes setting the
> PSR configuration over AUX, sending SDP VSC DIP over the eDP PIPE config,
> enabling PSR in the sink via DPCD register and finally enabling PSR on
> the host.
>
> This patch is hea
On Tue, Feb 26, 2013 at 1:58 PM, Chris Wilson wrote:
> On Tue, Feb 26, 2013 at 01:35:51PM +0100, Sedat Dilek wrote:
>> With xf86-video-intel-git13461a1 [1] I see this:
>>
>> [ build-log ]
>> ...
>> CC sna_cpu.lo
>> 8 warnings generated.
>> CC sna_damage.lo
>> CC sna_display.lo
>>
On Tue, Feb 26, 2013 at 01:35:51PM +0100, Sedat Dilek wrote:
> With xf86-video-intel-git13461a1 [1] I see this:
>
> [ build-log ]
> ...
> CC sna_cpu.lo
> 8 warnings generated.
> CC sna_damage.lo
> CC sna_display.lo
> sna_cpu.c:47:2: error: implicit declaration of function '__cpui
On Mon, Feb 25, 2013 at 07:55:20PM -0300, Rodrigo Vivi wrote:
> Adding Enable and Disable PSR functionalities. This includes setting the
> PSR configuration over AUX, sending SDP VSC DIP over the eDP PIPE config,
> enabling PSR in the sink via DPCD register and finally enabling PSR on
> the host.
>
erated.
make[4]: *** [sna_cpu.lo] Error 1
make[4]: *** Waiting for unfinished jobs
I checked for installed cpuid.h files, can't say if you this requires
the one from kernel or compiler sources.
In my running Linux-Next (next-20130226) kernel I have no "cpuid.h" h
For guilty batchbuffer analysis later on on ring resets,
mark all waiting rings so that we can skip them when
trying to find a true culprit for the gpu hang.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_irq.c | 11 +--
drivers/gpu/drm/i915/intel_ringbuffer.h |
In order to track down a batch buffer and context which
caused the ring to hang, store reference to bo and context
into the request struct. Request can also cause gpu to hang
after the batch in the flush section in the ring. To detect this
add start of the flush portion offset into the request.
Si
To count context losses, add struct ctx_reset_state for
both i915_hw_context and drm_i915_file_private.
drm_i915_file_private is used when there is no context.
Use kzalloc when allocating drm_i915_file_private to
initialize state.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_dma.c
In preparation to do analysis of which context was
guilty of gpu hung, store kreffed context pointer
into request struct.
This allows us to inspect contexts when gpu is reset
even if those contexts would already be released
by userspace.
v2: track i915_hw_context pointers instead of using ctx_ids
In preparation to track per ring progress in hangcheck,
add i915_hangcheck_ring_hung.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_irq.c | 31 +++
1 file changed, 19 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers
Rework of per ring hangcheck made this obsolete.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.h |1 -
drivers/gpu/drm/i915/i915_irq.c | 21 -
2 files changed, 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv
In preparation for the next commit, return context that
was switch to from i915_switch_context().
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.h|3 ++-
drivers/gpu/drm/i915/i915_gem.c|2 +-
drivers/gpu/drm/i915/i915_gem_context.c| 36 ++
In preparation for next commit, pass seqno as a parameter
to i915_hangcheck_ring_idle as it will be used inside
i915_hangcheck_elapsed.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_irq.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/d
If context has recently submitted a faulty batchbuffers guilty of
gpu hang and decides to keep submitting more crap, ban it permanently.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.c| 23 ++-
drivers/gpu/drm/i915/i915_drv.h|5 +
After hang check timer has declared gpu to be hang,
rings are reset. In ring reset, when clearing
request list, do post mortem analysis to find out
the guilty batch buffer.
Select requests for further analysis by inspecting
the completed sequence number which has been updated
into the HWS page. If
Add per ring score of possible culprit for gpu hang. If
ring is busy and not waiting, it will get the highest score
across calls to i915_hangcheck_elapsed. This way we are
most likely to find the ring that caused the hang among
the waiting ones.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i
For arb-robustness, every context needs to have it's own
reset state tracking. Default context will be handled in a identical
way as the no-context case in further down in the patch set.
For no-context case, the reset state will be stored in
the file_priv part.
v2: handle default context inside ge
Hi,
Revisited patchset for guilty context detection. I have
tried to take into account all feedback received from
RFC series posted earlier.
Kreffed contexts are first in the series and the
hangcheck triggering using seqnos have been split into
multiple smaller patches.
-Mika
Mika Kuoppala (13)
Instead of relying in acthd, track ring seqno progression
to detect if ring has hung.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.h |2 --
drivers/gpu/drm/i915/i915_irq.c | 30 +-
drivers/gpu/drm/i915/intel_ringbuffer.h |2
This is just silly. You are asking the GPU to generate interrupts which
we don't process (other than to discard).
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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