Implements WaVSRefCountFullforceMissDisable as documented in the BSpec
3D workarounds chapter.
Cc: Paulo Zanoni
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 4
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i9
On Fri, Jan 25, 2013 at 04:59:16PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> Instead of setting it at the beginning of haswell_crtc_mode_set, let's
> set it at the beginning of intel_crtc_mode_set. When
> intel_crt_mode_set calls drm_vblank_pre_modeset we already need to
> have the tran
On Fri, Jan 25, 2013 at 04:59:11PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> The current code was wrong in many different ways, so this is a full
> rewrite. We don't have "different power wells for different parts of
> the GPU", we have a single power well, but we have multiple register
On Fri, Jan 25, 2013 at 04:59:10PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> Previously I sent "drm/i915: don't read DP_TP_STATUS(PORT_A)", but
> after some more discussion I was told by a hardware engineer that we
> don't really need to send the idle patterns before the normal pattern
On Fri, Jan 25, 2013 at 09:44:45PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> SR01 needs to be touched to disable VGA on non-UMS setups too.
> So the sequencer registers need to include the appripriate offset
> on VLV.
>
> Signed-off-by: Ville Syrjälä
I've applied pa
On Fri, Jan 25, 2013 at 05:21:01PM +0100, Daniel Vetter wrote:
> On Fri, Jan 25, 2013 at 02:26:24PM +0200, Ville Syrjälä wrote:
> > On Thu, Jan 24, 2013 at 10:37:28PM +0100, Daniel Vetter wrote:
> > > On Thu, Jan 24, 2013 at 03:29:33PM +0200, ville.syrj...@linux.intel.com
> > > wrote:
> > > > From
