Re: [Intel-gfx] [PATCH 5/9] drm/i915: drop unnecessary clearing of pch dp transcoder timings

On Fri, Nov 16, 2012 at 8:52 PM, Paulo Zanoni wrote: > Notice that we have the CPU M/N registers and the PCH M/N registers. > And the PCH M/N registers are only used by DisplayPort, so it makes > sense to zero them for non-DisplayPort. If we really want this, how > about we add this patch only in

Re: [Intel-gfx] [PATCH 5/9] drm/i915: drop unnecessary clearing of pch dp transcoder timings

Hi 2012/11/5 Daniel Vetter : > This has originally been added in > > commit 8db9d77b1b14fd730561f64beea8c00e4478d7c5 > Author: Zhenyu Wang > Date: Wed Apr 7 16:15:54 2010 +0800 > > drm/i915: Support for Cougarpoint PCH display pipeline > > probably to combat issues with hw state left behind

Re: [Intel-gfx] [PATCH 4/9] drm/i915: WARN on !crtc in intel_dp_link_down

Hi 2012/11/5 Daniel Vetter : > This could have happened with the old crtc helper based modeset code, > but can't happen any longer with the new code. > > Hence put in a WARN and adjust the comment. If no one hits this, we > can eventually remove it (like a few other such cases across our > code).

[Intel-gfx] [PATCH] drm/i915: resurrect panel lid handling

But disabled by default. This essentially reverts commit bcd5023c961a44c7149936553b6929b2b233dd27 Author: Dave Airlie Date: Mon Mar 14 14:17:55 2011 +1000 drm/i915: disable opregion lid detection for now but leaves the autodetect mode disabled. There's also the explicit lid status option

Re: [Intel-gfx] [PATCH 2/9] drm/i915: rip out pre-production ilk cpu edp w/a

Hi 2012/11/5 Daniel Vetter : > While reading docs I've noticed that this special workaround to select > the 1.6 GHz DP clock only applies to pre-production ilk machines. > Since the registers we're touching here are rather undocumented and > might be harmful on later chips, rip it out. > > For the

Re: [Intel-gfx] [PATCH 1/9] drm/i915: move set_pll_edp to intel_dp.c

2012/11/5 Daniel Vetter : > Now that we enable the cpu edp pll in intel_dp->pre_enable and no > longer in crtc_mode_set, we can also move the modeset part to the > intel_dp->mode_set callback. Previously this was not possible because > the encoder ->mode_set callbacks are called after the crtc mode

Re: [Intel-gfx] [PATCH 8/8] drm/i915: rip out pre-DDI stuff from haswell_crtc_mode_set

On Fri, Nov 16, 2012 at 7:28 PM, Paulo Zanoni wrote: > Hi > > 2012/11/5 Daniel Vetter : >> Especially getting rid of all things lvds is ... great! >> >> Signed-off-by: Daniel Vetter >> --- >> intel_crtc_update_cursor(crtc, true); >> >> /* determine panel color depth */ >>

Re: [Intel-gfx] [PATCH 8/8] drm/i915: rip out pre-DDI stuff from haswell_crtc_mode_set

Hi 2012/11/5 Daniel Vetter : > Especially getting rid of all things lvds is ... great! > > Signed-off-by: Daniel Vetter > --- > drivers/gpu/drm/i915/intel_display.c | 114 > +-- > 1 file changed, 1 insertion(+), 113 deletions(-) > > diff --git a/drivers/gpu/drm/i

Re: [Intel-gfx] [PATCH 7/8] drm/i915: enable intel_lvds->pre_pll_enable for ilk+, too

Hi 2012/11/5 Daniel Vetter : > Only two things needed adjustment: > - pipe select for PCH_CPT > - There's no dithering bit on ilk+ in the lvds ctl reg > > Signed-off-by: Daniel Vetter Reviewed-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/intel_display.c | 40 > --

Re: [Intel-gfx] [PATCH 6/8] drm/i915: move intel_update_lvds to intel_lvds->pre_pll_enable

Hi 2012/11/5 Daniel Vetter : > A few things needed to change: > - HAS_PCH_SPLIT since ilk+ is not yet converted to this. > - s/LVDS/intel_lvds->reg/ to prep for ilk conversion > - replace the clock.p2 == 7 check with a is_dual_link check > - s/adjusted_mode/intel_lvds->fixed_mode > > v2: Rebase on

Re: [Intel-gfx] [pull] drm-intel-next

On Fri, Nov 16, 2012 at 6:47 PM, Alex Deucher wrote: > Hey, I don't see the drm HPD fixes. Are you planning to put them in > another pull request? It would be nice to get them upstream for 3.8 Since they only refine the drm helpers in the core, I've figured there's no need to merge them through

Re: [Intel-gfx] [pull] drm-intel-next

On Fri, Nov 16, 2012 at 12:17 PM, Daniel Vetter wrote: > Hi Dave, > > Highlights of this -next round: > - ivb fdi B/C fixes > - hsw sprite/plane offset fixes from Damien > - unified dp/hdmi encoder for hsw, finally external dp support on hsw > (Paulo) > - kill-agp and some other prep work in the

Re: [Intel-gfx] [PATCH 5/8] drm/i915: add intel_lvds->reg

Hi 2012/11/5 Daniel Vetter : > To ditch at least some of the PCH_SPLIT ? PCH_LVDS : LVDS code ... > > v2: Rebase on top of Jani Nikula's panel rework. > > Signed-off-by: Daniel Vetter Reviewed-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/intel_lvds.c | 48 > -

Re: [Intel-gfx] [PATCH 4/8] drm/i915: track is_dual_link in intel_lvds

Hi 2012/11/5 Daniel Vetter : > Yeah, all users (both the clock selection special cases and the lvds > pin pair stuff) are still in common code, but this will change. > > v2: Rebase on top of Jani Nikula's panel rework. > > Signed-off-by: Daniel Vetter > --- > drivers/gpu/drm/i915/intel_lvds.c |

Re: [Intel-gfx] [PATCH 3/8] drm/i915: move is_dual_link_lvds to intel_lvds.c

Hi 2012/11/5 Daniel Vetter : > Just a prep patch to make this a property of intel_lvds. Makes more > sense, removes clutter from intel_display.c and eventually I want to > move all the encoder special cases wrt clock handling to encoders > anyway. > > Signed-off-by: Daniel Vetter > --- > drivers

Re: [Intel-gfx] [PATCH 2/8] drm/i915: replace ad-hoc dual-link lvds checks

On Fri, Nov 16, 2012 at 6:07 PM, Paulo Zanoni wrote: > Well, take a look at patch 832cc28d5bc676331e6376d940ae45d5937aa688 > and then read the 4-line comment that's inside the "if" statement. If > we're going to completely remove the I915_READ line, shouldn't we also > update the comment ("if the

[Intel-gfx] [pull] drm-intel-next

Hi Dave, Highlights of this -next round: - ivb fdi B/C fixes - hsw sprite/plane offset fixes from Damien - unified dp/hdmi encoder for hsw, finally external dp support on hsw (Paulo) - kill-agp and some other prep work in the gtt code from Ben - some fb handling fixes from Ville - massive pile o

Re: [Intel-gfx] [PATCH 2/8] drm/i915: replace ad-hoc dual-link lvds checks

Hi 2012/11/16 Daniel Vetter : > On Fri, Nov 16, 2012 at 5:37 PM, Paulo Zanoni wrote: >>> diff --git a/drivers/gpu/drm/i915/intel_display.c >>> b/drivers/gpu/drm/i915/intel_display.c >>> index 1ad6d34..0973391 100644 >>> --- a/drivers/gpu/drm/i915/intel_display.c >>> +++ b/drivers/gpu/drm/i915/in

Re: [Intel-gfx] [PATCH 1/8] drm/i915: add encoder->pre_pll_enable callback

Hi 2012/11/16 Daniel Vetter : > On Fri, Nov 16, 2012 at 5:05 PM, Paulo Zanoni wrote: >> Hi >> >> 2012/11/5 Daniel Vetter : >>> Currently we have two encoder specific bits in the common mode_set >>> functions: >>> - lvds pin pair enabling >>> - dp m/n setting and computation >>> >>> Both need to h

Re: [Intel-gfx] [PATCH 2/8] drm/i915: replace ad-hoc dual-link lvds checks

On Fri, Nov 16, 2012 at 5:37 PM, Paulo Zanoni wrote: >> diff --git a/drivers/gpu/drm/i915/intel_display.c >> b/drivers/gpu/drm/i915/intel_display.c >> index 1ad6d34..0973391 100644 >> --- a/drivers/gpu/drm/i915/intel_display.c >> +++ b/drivers/gpu/drm/i915/intel_display.c >> @@ -690,8 +690,7 @@ i

Re: [Intel-gfx] [PATCH] drm/i915: disable cloning on sdvo

Hi 2012/11/16 Daniel Vetter : > On Fri, Nov 16, 2012 at 12:04:35PM -0200, Paulo Zanoni wrote: >> Hi >> >> 2012/11/13 Daniel Vetter : >> > After the recent pile of disable-cloning patches, e.g. >> > >> > commit e3b86d6941c7e5f90be05d986fce1fcb40c68d6b >> > Author: Egbert Eich >> > Date: Sat Oct

Re: [Intel-gfx] [PATCH 2/8] drm/i915: replace ad-hoc dual-link lvds checks

Hi 2012/11/5 Daniel Vetter : > ... with is_dual_link_lvds introduced in > > commit b03543857fd75876b96e10d4320b775e95041bb7 > Author: Takashi Iwai > Date: Tue Mar 20 13:07:05 2012 +0100 > > drm/i915: Check VBIOS value for determining LVDS dual channel mode, too > > All these checks predate

Re: [Intel-gfx] [PATCH 1/8] drm/i915: add encoder->pre_pll_enable callback

On Fri, Nov 16, 2012 at 5:05 PM, Paulo Zanoni wrote: > Hi > > 2012/11/5 Daniel Vetter : >> Currently we have two encoder specific bits in the common mode_set >> functions: >> - lvds pin pair enabling >> - dp m/n setting and computation >> >> Both need to happen before we enable the pll. > > Not tr

Re: [Intel-gfx] [PATCH] drm/i915: disable cloning on sdvo

On Fri, Nov 16, 2012 at 12:04:35PM -0200, Paulo Zanoni wrote: > Hi > > 2012/11/13 Daniel Vetter : > > After the recent pile of disable-cloning patches, e.g. > > > > commit e3b86d6941c7e5f90be05d986fce1fcb40c68d6b > > Author: Egbert Eich > > Date: Sat Oct 13 14:30:15 2012 +0200 > > > > DRM/i

Re: [Intel-gfx] [PATCH 0/8] lvds cleanup

Hi 2012/11/5 Daniel Vetter : > Hi all, > > This is the first cleanup from my next stab at reworking the modeset code, > with > the ultimate goal that we can compute the entire configuration (fdi config, > pll > config, sharing of global resources) up-front, before touching the hw at all. > Toget

Re: [Intel-gfx] [PATCH 1/8] drm/i915: add encoder->pre_pll_enable callback

Hi 2012/11/5 Daniel Vetter : > Currently we have two encoder specific bits in the common mode_set > functions: > - lvds pin pair enabling > - dp m/n setting and computation > > Both need to happen before we enable the pll. Not true, at least for the docs I checked (gen6+), setting/computing the m

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Restore physical HWS_PGA after resume

On Fri, Nov 16, 2012 at 11:43:20AM +, Chris Wilson wrote: > By always setting up the HWS register for both physical and virtual > address variations during render ring we can reduce the number of > different special cases that get set up at varying different times > during module load. > > Fix

[Intel-gfx] [PATCH] drm/i915: Enable DP audio for Haswell

This patch adds the missing code to send ELD for Haswell DisplayPort, based on Xingchao's original patch. A test was performed with HSW-D machine and NEC EA232Wmi DP monitor. Cc: Xingchao Wang Signed-off-by: Takashi Iwai --- drivers/gpu/drm/i915/intel_ddi.c | 9 + 1 file changed, 9 ins

[Intel-gfx] [PATCH 13/13] drm/i915: Add trace point for atomic flip vblank evade

From: Ville Syrjälä Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_trace.h | 18 ++ drivers/gpu/drm/i915/intel_atomic.c |2 ++ 2 files changed, 20 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace

[Intel-gfx] [PATCH 10/13] HACK: drm/i915: Make non-blocking GPU synchronization optional

From: Ville Syrjälä Add a module parameter that allows one to easily change between blocking and non-blocking GPU synchronization with atomic page flips. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/drm_stub.c |5 ++ drivers/gpu/drm/i915/i915_trace.h | 49 ++ d

[Intel-gfx] [PATCH 12/13] drm/i915: Add post flush DSL readout for surflive debug

From: Ville Syrjälä Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_trace.h | 19 +++ drivers/gpu/drm/i915/intel_atomic.c |4 2 files changed, 23 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_tr

[Intel-gfx] [PATCH 06/13] drm/i915: Clear pending flips in haswell_crtc_disable()

From: Ville Syrjälä Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 48eeed5..acd5aa0 100644 --- a/drivers/gpu/drm/i91

[Intel-gfx] [PATCH 11/13] drm/i915: Add some timing debugs to atomic flips

From: Ville Syrjälä --- drivers/gpu/drm/i915/intel_atomic.c | 15 +++ 1 files changed, 15 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c index 170ac6f..c6531b0 100644 --- a/drivers/gpu/drm/i915/intel_atomic.c +

[Intel-gfx] [PATCH 09/13] drm/i915: Add trace points for flip queue length

From: Ville Syrjälä Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_drv.h |1 + drivers/gpu/drm/i915/i915_trace.h | 15 +++ drivers/gpu/drm/i915/intel_atomic.c |9 - 3 files changed, 24 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/i9

[Intel-gfx] [PATCH 08/13] drm/i915: Add pin count trace point

From: Ville Syrjälä A new trace point for tracking changes to gem object pin count. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_gem.c |6 ++ drivers/gpu/drm/i915/i915_trace.h | 19 +++ 2 files changed, 25 insertions(+), 0 deletions(-) diff --git a/dr

[Intel-gfx] [PATCH 02/13] drm/i915: Refactor atomic flip code

From: Ville Syrjälä Collect the part which takes care of issuing the flips to a new function. This makes the following patch nicer to look at. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_atomic.c | 37 -- 1 files changed, 22 insertions(+), 15 d

[Intel-gfx] [PATCH 00/13] drm/i915: Non-blocking GPU synchronization for atomic page flips (v2)

Here's my second attempt at making atomic page flips synchronize with the GPU in a non-blocking manner. What the code does by default is grap the last_write_seqno from the object, call intel_gem_check_olr() on it, perform the lazy coherency check, and if the seqno still hasn't passed it'll enable

[Intel-gfx] [PATCH 07/13] drm/i915: Drop all flips waiting for the GPU when the CRTC is about to be disabled

From: Ville Syrjälä Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_atomic.c | 36 +++ 1 files changed, 36 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c index 0aa8c93..6bec72b

[Intel-gfx] [PATCH 05/13] drm/i915: Make a copy of the calculated plane regs

From: Ville Syrjälä The register values are computed when the flip ioctl is issued, and they're used only after we've waited for the GPU to finish rendering. The computed values are store in the intel_crtc and intel_plane structs, so issuing another flip before the previous one has been fully com

[Intel-gfx] [PATCH 03/13] drm/i915: Implement a non-blocking GPU synchronization mechanism for atomic page flips

From: Ville Syrjälä After the atomic flip has been split up into individual flip requests for each scanout engine, put each such request into a FIFO. Then for each flip request add new request to the ring(s) in order to get an interrupt once the GPU has finished whatever it was doing with the new

[Intel-gfx] [PATCH 04/13] drm/i915: Release all atomic flips when GPU hangs

From: Ville Syrjälä If the GPU hangs, release all pending atomic flips from the queue. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_irq.c |1 + drivers/gpu/drm/i915/intel_atomic.c | 29 + drivers/gpu/drm/i915/intel_drv.h|1 + 3 files

[Intel-gfx] [PATCH 01/13] drm/i915: Unstatic i915_gem_check_olr()

From: Ville Syrjälä Atomic code might need i915_gem_check_olr(). Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_drv.h |1 + drivers/gpu/drm/i915/i915_gem.c |2 +- 2 files changed, 2 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/dr

Re: [Intel-gfx] [PATCH] drm/i915: disable cloning on sdvo

Hi 2012/11/13 Daniel Vetter : > After the recent pile of disable-cloning patches, e.g. > > commit e3b86d6941c7e5f90be05d986fce1fcb40c68d6b > Author: Egbert Eich > Date: Sat Oct 13 14:30:15 2012 +0200 > > DRM/i915: Don't clone SDVO LVDS with analog > > and a bug report from Chris Wilson indi

Re: [Intel-gfx] [PATCH] drm/i915: Re-enable mt forcewake check for IVB

At Thu, 15 Nov 2012 21:22:41 +0100, Takashi Iwai wrote: > > At Thu, 15 Nov 2012 21:07:33 +0100, > Daniel Vetter wrote: > > > > On Thu, Nov 15, 2012 at 6:03 PM, Takashi Iwai wrote: > > > Some IVB machines seem to need non-MT forcewake. Using MT forcewake > > > on such machines result in broken o

[Intel-gfx] [PATCH 1/2] drm/i915: Restore physical HWS_PGA after resume

By always setting up the HWS register for both physical and virtual address variations during render ring we can reduce the number of different special cases that get set up at varying different times during module load. Fixes regression from commit c630119f43471a8ece356b01dabf07f944f453b3 Author

[Intel-gfx] [PATCH 2/2] drm/i915: Remove save/restore of physical HWS_PGA register

Now that we always restore the HWS registers (both physical and GTT virtual addresses) when re-initialising the rings, we can eliminate the superfluous save/restore of the register across suspend and resume. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_drv.h |1 - drivers/gp

Re: [Intel-gfx] [PATCH] drm/i915: Fix warning in i915_gem_chipset_flush

On Thu, Nov 15, 2012 at 12:06:09PM -0800, Ben Widawsky wrote: > drivers/gpu/drm/i915/i915_drv.h:1545:2: warning: '__f' is static but > declared in inline function 'i915_gem_chipset_flush' which is not static > > Reported-by: kbuild test robot > dri-devel-Reference: <50a4d41c.586vhmwghpukzbkb%

Re: [Intel-gfx] [PATCH 1/2] intel: Sync the parameter of i915_getparma with the kernel

On Fri, Nov 16, 2012 at 2:52 AM, Xiang, Haihao wrote: > On Thu, 2012-11-15 at 12:30 +0100, Daniel Vetter wrote: >> On Wed, Nov 14, 2012 at 12:46:38PM +0800, Xiang, Haihao wrote: >> > From: Zhao Yakui >> > >> > Signed-off-by: Zhao Yakui >> >> Fyi the best way is to simply run >> >> $ make headers