[Intel-gfx] [PATCH 18/18] drm/i915: add I915_PARAM_HAS_VEBOX to i915_getparam

From: "Xiang, Haihao" This will let userland only try to use the new ring when the appropriate kernel is present Signed-off-by: Xiang, Haihao [Order changed, and merge conflict resolved by] Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_dma.c | 3 +++ include/uapi/drm/i915_drm.h

[Intel-gfx] [PATCH 17/18] drm/i915: add I915_EXEC_VEBOX to i915_gem_do_execbuffer()

From: "Xiang, Haihao" A user can run batchbuffer via VEBOX ring. Signed-off-by: Xiang, Haihao [Order changed by] Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 9 + include/uapi/drm/i915_drm.h| 1 + 2 files changed, 10 insertions(+) diff

[Intel-gfx] [PATCH 16/18] drm/i915: add VEBOX into debugfs

From: "Xiang, Haihao" Signed-off-by: Xiang, Haihao [Order changed, and modified by] Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_debugfs.c | 13 + 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c

[Intel-gfx] [PATCH 15/18] drm/i915: Enable vebox interrupts

Similar to a patch originally written by: v2: Reversed the meanings of masked and enabled (Haihao) Made non-destructive writes in case enable/disabler rps runs first (Haihao) CC: Xiang, Haihao Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_irq.c | 25 +++-

[Intel-gfx] [PATCH 14/18] drm/i915: vebox interrupt get/put

v2: Use the correct lock to protect PM interrupt regs, this was accidentally lost from earlier (Haihao) Fix return types (Ben) CC: Xiang, Haihao Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/intel_ringbuffer.c | 46 +++-- drivers/gpu/drm/i915/intel_ringbuffer.

[Intel-gfx] [PATCH 13/18] drm/i915: consolidate interrupt naming scheme

The motivation here is we're going to add some new interrupt definitions and handling outside of the GT interrupts which is all we've managed so far (with some RPS exceptions). By consolidating the names in the future we can make thing a bit cleaner as we don't need to define register names twice,

[Intel-gfx] [PATCH 12/18] drm/i915: Convert irq_refounct to struct

It's overkill on older gens, but it's useful for newer gens. Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/intel_ringbuffer.c | 16 drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +++- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/inte

[Intel-gfx] [PATCH 11/18] drm/i915: Add PM regs to pre install

Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_irq.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index d882d41..4ac4522 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -

[Intel-gfx] [PATCH 10/18] drm/i915: Create an ivybridge_irq_preinstall

Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_irq.c | 30 +++--- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 5533e55..d882d41 100644 --- a/drivers/gpu/drm/i915/i915_irq.c

[Intel-gfx] [PATCH 09/18] drm/i915: make PM interrupt writes non-destructive

PM interrupts have an expanded role on HSW. It helps route the EBOX interrupts. This patch is necessary to make the existing code which touches the mask, and enable registers more friendly to other code paths that also will need these registers. v2: Shouldn't destroy PMIIR or PMIMR VEBOX interrupt

[Intel-gfx] [PATCH 08/18] drm/i915: Create a more generic pm handler for hsw+

HSW has some special requirements for the VEBOX. Splitting out the interrupt handler will make the code a bit nicer and less error prone when we begin to handle those. The slight functional change in this patch (queueing work while holding the spinlock) is intentional as it makes a subsequent patc

[Intel-gfx] [PATCH 07/18] drm/i915: Vebox ringbuffer init

Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_gem.c | 8 drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_ringbuffer.c | 34 - drivers/gpu/drm/i915/intel_ringbuffer.h | 1 + 4 files changed, 43 insertions(+),

[Intel-gfx] [PATCH 06/18] drm/i915: add HAS_VEBOX

From: "Xiang, Haihao" The flag will be useful to help share code between IVB, and HSW as the programming is similar in many places with this as one of the major differences. Signed-off-by: Xiang, Haihao [Commit message + small fix by] Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_

[Intel-gfx] [PATCH 05/18] drm/i915: Rename ring flush functions

Historically we considered the render ring to have special flush semantics and everything else to fall under a more general umbrella. Probably by coincidence more than anything we decided to make the bsd ring have the default *other* flush. As the new vebox ring exposes, the bsd ring is actually th

[Intel-gfx] [PATCH 04/18] drm/i915: Add VECS semaphore bits

Like the other rings, the VECS supports semaphores. The semaphore stuff is a bit wonky so this patch on it's own should be nice for review. This patch should have no functional impact. Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_reg.h | 40 ++---

[Intel-gfx] [PATCH 03/18] drm/i915: Introduce VECS: the 4th ring

The video enhancement command streamer is a new ring on HSW which does what it sounds like it does. This patch provides the most minimal inception of the ring. In order to support a new ring, we need to bump the number. The patch may look trivial to the untrained eye, but bumping the number of rin

[Intel-gfx] [PATCH 02/18] drm/i915: Semaphore MBOX update generalization

This replaces the existing MBOX update code with a more generalized calculation for emitting mbox updates. We also create a sentinel for doing the updates so we can more abstractly deal with the rings. When doing MBOX updates the code must be aware of the /other/ rings. Until now the platforms whi

[Intel-gfx] [PATCH 01/18] drm/i915: Comments for semaphore clarification

Semaphores are tied very closely to the rings in the GPU. Trivial patch adds comments to the existing code so that when we add new rings we can include comments there as well. It also helps distinguish the ring to semaphore mailbox interactions by using the ringname in the semaphore data structures

[Intel-gfx] [PATCH 00/18] [RFC] Introduce the Haswell VECS

The VECS is a new command streamer introduced in Haswell which allows offloading of video post processing to a new engine called the VEBOX. Like other rings, it is up to userspace to take advantage of it. Also like the other rings, the primary enabling is turning on interrupts, adding the new semap

[Intel-gfx] [PATCH] drm/i915: Missed lock change with rps lock

Fixes a WARN_ON in igt/tests/debugfs_reader CC: Jesse Barnes Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_debugfs.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index e842dea..09bc2

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Clear unused fields of mode for framebuffer creation

On Mon, Nov 05, 2012 at 10:25:07PM +, Chris Wilson wrote: > With the stricter checks introduced in > commit ac911edae5960d7dccd9883f5fa5d25b591520de > Author: Ville Syrjälä > Date: Wed Oct 31 17:50:19 2012 +0200 > > drm/i915: Check the framebuffer offset > > (and friends), it became es

Re: [Intel-gfx] [PATCH] drm/i915/crt: fix DPMS standby and suspend mode handling

On Mon, Nov 05, 2012 at 01:51:51PM +0200, Jani Nikula wrote: > PCH platforms and VLV should map DPMS standby and suspend modes to off, but > due to a buggy reversed comparison this is done on pre-PCH platforms > instead. > > Reported-by: Loïc Yhuel > Bugzilla: https://bugs.freedesktop.org/show_bu

[Intel-gfx] [PATCH] drm/i915: Fix sparse warnings in from AGP kill code

Reported-by: Fengguang Wu Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 4d62f32..2383653 100644 --- a/drivers/gpu/drm/i915/i9