Re: [Intel-gfx] [3.0.y, 3.2.y, 3.4.y] Please add LVDS patch for the Zotac ZBOX SD ID13

On Sun, 2012-10-21 at 12:41 -0700, Jonathan Nieder wrote: > Hi Ben and Greg, > > Please consider > > 9756fe38d10b drm/i915: no lvds quirk for Zotac ZDBOX SD ID12/ID13 > > for application to the 3.0.y, 3.2.y, and 3.4.y trees. It was applied > upstream during the 3.6 merge window, so newer kern

[Intel-gfx] [PATCH] drm/i915: add comment about pch pll enabling rules

Atm we have a few funny issues where we enable/disable shared pll clocks. To make it clear that we are not required to enable/ disable the pch plls together with the other pch resources (and so should keep it running when it's used by another pipe in a shared pll configuration) add a comment. This

[Intel-gfx] [PATCH 2/2] drm/i915: move panel connectors to the front

This essentially reverts commit cb0953d734348e8862d6d7edc666cfb3bf6d8fae Author: Adam Jackson Date: Fri Jul 16 14:46:29 2010 -0400 drm/i915: Initialize LVDS and eDP outputs before anything else simply because it doesn't scale: It misses SDVO and DVO panels, and now with DDI encoders on ha

[Intel-gfx] [PATCH 1/2] drm: add helper to sort panels to the head of the connector list

Userspace seems to like this, see commit cb0953d734348e8862d6d7edc666cfb3bf6d8fae Author: Adam Jackson Date: Fri Jul 16 14:46:29 2010 -0400 drm/i915: Initialize LVDS and eDP outputs before anything else This makes them sort to the front in X, which makes them likely to be the prim

[Intel-gfx] [PATCH] drm/i915: check fdi B/C lane sharing constraint

And properly toggle the chicken bit in the pch to enable/disable fdi C rx. If we don't set this bit correctly, the rx gets confused in link training, which can result in an fdi link that silently fails to train the link (since the corresponding register reports success). Note that both fdi link B a

Re: [Intel-gfx] [PATCH 2/9] drm/i915: Write the FDI RX TU size reg at the right time

On Sat, Oct 27, 2012 at 3:18 PM, Paulo Zanoni wrote: > Our mode set sequence says the FDI PLL should be enabled way earlier > than the other FDI/PCH resources, and that's what we currently do, so > I believe it is currently being called at the "right place" or at > least close to the right place.

[Intel-gfx] [PATCH] drm/i915: clarify why we need to enable fdi plls so early

For reference, see "Graphics BSpec: vol4g North Display Engine Registers [IVB], Display Mode Set Sequence", step 4 of the enabling sequence: a. "Enable PCH FDI Receiver PLL, wait for warmup plus DMI latency b. "Switch from Rawclk to PCDclk in FDI Receiver c. "Enable CPU FDI Transmitter PLL, wait f

[Intel-gfx] [PATCH] drm/i915: Write the FDI RX TU size reg at the right time

According to "Graphics BSpec: vol4g North Display Engine Registers [IVB], Display Mode Set Sequence" We need to write the TU size register of the fdi RX unit _before_ starting to train the link. v2: Paulo Zanoni pointed out that the current sequence is already corret - I've been confused by the _v

Re: [Intel-gfx] [PATCH 2/9] drm/i915: Write the FDI RX TU size reg at the right time

2012/10/27 Daniel Vetter : > On Sat, Oct 27, 2012 at 3:03 PM, Paulo Zanoni wrote: >> 2012/10/27 Daniel Vetter : >>> On Sat, Oct 27, 2012 at 1:51 PM, Paulo Zanoni wrote: 2012/10/26 Daniel Vetter : > According to "Graphics BSpec: vol4g North Display Engine Registers [IVB], > Display Mo

[Intel-gfx] Updated -testing

Hi all, Updated -testing branch with tons of stuff: - basic haswell dp support, not yet wire up for external ports (Paulo) - edp support (Paulo) - tons of refactorings to prepare for the above (Paulo) - panel rework, unifiying code between lvds and edp panels (Jani) - panel fitter scaling modes (J

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Fix sprite offset on HSW

2012/10/26 Damien Lespiau : > From: Damien Lespiau > > HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET > register. > > v2: Remove a useless level of indentation (Paulo Zanoni) > > Signed-off-by: Damien Lespiau > Reviewed-by: Paulo Zanoni (v1) Reviewed-by tag still applies to v

Re: [Intel-gfx] [PATCH 2/9] drm/i915: Write the FDI RX TU size reg at the right time

On Sat, Oct 27, 2012 at 3:03 PM, Paulo Zanoni wrote: > 2012/10/27 Daniel Vetter : >> On Sat, Oct 27, 2012 at 1:51 PM, Paulo Zanoni wrote: >>> 2012/10/26 Daniel Vetter : According to "Graphics BSpec: vol4g North Display Engine Registers [IVB], Display Mode Set Sequence" We need to write

Re: [Intel-gfx] [PATCH 9/9] drm/i915: check fdi B/C lane sharing constraint

On Sat, Oct 27, 2012 at 2:56 PM, Paulo Zanoni wrote: > After reading your patch everything looks correct (even though it's > complicated, so a proper testing is better than 1000 reviews here). My > only worry is: do we properly disable all the resources we need to > disable when we fail here? I am

Re: [Intel-gfx] [PATCH 2/9] drm/i915: Write the FDI RX TU size reg at the right time

2012/10/27 Daniel Vetter : > On Sat, Oct 27, 2012 at 1:51 PM, Paulo Zanoni wrote: >> 2012/10/26 Daniel Vetter : >>> According to "Graphics BSpec: vol4g North Display Engine Registers [IVB], >>> Display Mode Set Sequence" We need to write the TU size register >>> of the fdi RX unit _before_ startin

Re: [Intel-gfx] [PATCH 2/9] drm/i915: Write the FDI RX TU size reg at the right time

On Sat, Oct 27, 2012 at 1:51 PM, Paulo Zanoni wrote: > 2012/10/26 Daniel Vetter : >> According to "Graphics BSpec: vol4g North Display Engine Registers [IVB], >> Display Mode Set Sequence" We need to write the TU size register >> of the fdi RX unit _before_ starting to train the link. > > Well, we

Re: [Intel-gfx] [PATCH 4/9] drm/i915: add comment about pch pll enabling rules

On Sat, Oct 27, 2012 at 2:15 PM, Paulo Zanoni wrote: > I'm not sure what's the problem with the current code. Could you > please explain a little bit more? After a brief look at > intel_enable_pch_pll and intel_disable_pch_pll it seems our code does > try to check the pll refcount and behave corre

Re: [Intel-gfx] [PATCH 9/9] drm/i915: check fdi B/C lane sharing constraint

Hi 2012/10/26 Daniel Vetter : > And properly toggle the chicken bit in the pch to enable/disable fdi C > rx. If we don't set this bit correctly, the rx gets confused in link > training, which can result in an fdi link that silently fails to train > the link (since the corresponding register report

Re: [Intel-gfx] [PATCH 8/9] drm/i915: add ->display.modeset_global_resources callback

Hi 2012/10/26 Daniel Vetter : > After all relevant pipes are disabled and after we've updated all the > state with the staged state, but before we call the per-crtc > ->mode_set functions there's a very natural point to set up any > shared/global resources like > - shared plls (obviously only the

Re: [Intel-gfx] [PATCH 4/9] drm/i915: add comment about pch pll enabling rules

Hi 2012/10/26 Daniel Vetter : > Atm we have a few funny issues where we enable/disable shared > pll clocks. To make it clear that we are not required to enable/ > disable the pch plls together with the other pch resources (and > so should keep it running when it's used by another pipe in > a share

Re: [Intel-gfx] [PATCH 3/9] drm/i915: set FDI_RX_MISC to recommended values on CPT/PPT

Hi 2012/10/26 Daniel Vetter : > My machine here has the correct ones already, but better safe > than sorry. IBX has different settings for that register, and > on IBX the device defaults match the recommended values. Hence > I did not add the respective writes for IBX. > > LPT needs the same setti

Re: [Intel-gfx] [PATCH 2/9] drm/i915: Write the FDI RX TU size reg at the right time

2012/10/26 Daniel Vetter : > According to "Graphics BSpec: vol4g North Display Engine Registers [IVB], > Display Mode Set Sequence" We need to write the TU size register > of the fdi RX unit _before_ starting to train the link. Well, we are still writing it before training the link, but it's w