[Intel-gfx] [PATCH v3] drm/i915: fix color order for BGR formats on IVB

2012-08-22 Thread Vijay Purushothaman
This is already fixed for ILK and SNB in the below commit but somehow IVB is missed. commit ab2f9df10dd955f1fc0a8650e377588c98f1c029 Author: Jesse Barnes Date: Mon Feb 27 12:40:10 2012 -0800 drm/i915: fix color order for BGR formats on SNB Had the wrong bits and field

Re: [Intel-gfx] [PATCH v2] drm/i915: fix color order for BGR formats on IVB

2012-08-22 Thread Vijay Purushothaman
On 8/22/2012 6:30 PM, Antti Koskipää wrote: Hi, On 08/22/12 12:17, Vijay Purushothaman wrote: This is already fixed for ILK and SNB in the below commit but somehow IVB is missed. commit ab2f9df10dd955f1fc0a8650e377588c98f1c029 Author: Jesse Barnes Date: Mon Feb 27 12:40:10 2012 -0800

Re: [Intel-gfx] glxdemo/glxpixmap doesn't work, please help

2012-08-22 Thread Meng, David
Hi Ben: Thanks for the further response. Could you explain what type timing issue will be? Any clue will be great help. We are not using Linux kernel. But I doubt this is kernel related issue. It looks like a GPU issue. Regards, David -Original Message- From: Ben Widawsky [mailto:b..

Re: [Intel-gfx] glxdemo/glxpixmap doesn't work, please help

2012-08-22 Thread Ben Widawsky
On Tue, 21 Aug 2012 05:54:42 + "Meng, David" wrote: > Hi Ben: > Thank you for your quick response. > > We will follow the direction to file bug. > > The reason we knew the GPU hangs on 0x64 is because the head of the > render ring buffer is equal to the ox64 and never move again. That > me

[Intel-gfx] Bug: wayland performance halfed when running es2gears_wayland at fedora17

2012-08-22 Thread Alex Wu
Hi all, We are doing some performance profiling on wayland using es2gears and found a issue that mesa-deoms/src/egl/opengles2/es2gears_wayland (running drm backend) on platform-a (sandybridge, fedora 17 with kernel version 3.5) has 30fps but es2gears_x11 60fps, but on platform-b (sandybridge, Ubunt

Re: [Intel-gfx] source-based replacement for video bios on ivybridge -- I'm stuck!

2012-08-22 Thread ron minnich
OK, thanks to the great suggestions and help I found on this list I am now lighting up the display, i.e. clock recovery and so on work, the display is trained, and it seems I am getting data from memory to the display. Now I'm trying to understand some other things. I can set the GTT entries, and

Re: [Intel-gfx] [PATCH 00/58] modeset-rework, the basic conversion

2012-08-22 Thread Daniel Vetter
On Wed, Aug 22, 2012 at 08:13:37PM +0100, Lespiau, Damien wrote: > On Wed, Aug 22, 2012 at 12:03 PM, Lespiau, Damien > wrote: > > On Wed, Aug 22, 2012 at 11:46 AM, Lespiau, Damien > > wrote: > >> On Tue, Aug 21, 2012 at 7:11 PM, Daniel Vetter wrote: > Smoke-tested the new modeset-rework bra

Re: [Intel-gfx] [PATCH 00/58] modeset-rework, the basic conversion

2012-08-22 Thread Lespiau, Damien
On Wed, Aug 22, 2012 at 12:03 PM, Lespiau, Damien wrote: > On Wed, Aug 22, 2012 at 11:46 AM, Lespiau, Damien > wrote: >> On Tue, Aug 21, 2012 at 7:11 PM, Daniel Vetter wrote: Smoke-tested the new modeset-rework branch and found a regression on my IVB with a pristine f17 userland:

[Intel-gfx] [PATCH] drm/i915/contexts: Always use arbitration reset workaround

2012-08-22 Thread Ben Widawsky
VLV needs it, HSW needs it, and it shouldn't hurt on SNB. Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_gem_context.c | 11 +++ 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c ind

[Intel-gfx] [PATCH 3/3 v3] drm/i915: Use new INSTDONE registers (Gen7+)

2012-08-22 Thread Ben Widawsky
Using the extracted INSTDONE reading, and our new register definitions, update our hangcheck detection and error collection to use it. This primarily means changing == to memcmp, and changing = to memcpy. Hopefully this will give more info on error dump, and provide more accurate hangcheck detectio

[Intel-gfx] [PATCH 2/3] [REPOST] drm/i915: Add new INSTDONE registers

2012-08-22 Thread Ben Widawsky
Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_reg.h | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1f97b3f..d0b60f2 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 1/3 v3] drm/i915: Extract reading INSTDONE

2012-08-22 Thread Ben Widawsky
INSTDONE is used in many places, and it varies from generation to generation. This provides a good reason for us to extract the logic to read the relevant information. The patch has no functional change. It's prep for some new stuff. v2: move the memset inside of i915_get_extra_instdone (Jani) v3

Re: [Intel-gfx] [PATCH 27/29] drm/i915: Allocate overlay registers from stolen memory

2012-08-22 Thread Daniel Vetter
On Wed, Aug 22, 2012 at 04:45:45PM +0100, Chris Wilson wrote: > On Mon, 20 Aug 2012 23:17:06 +0200, Daniel Vetter wrote: > > On Sat, Aug 11, 2012 at 03:41:26PM +0100, Chris Wilson wrote: > > > Signed-off-by: Chris Wilson > > > > Since most of the overlay-supporting hw uses physical mem for the o

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Find unclaimed MMIO writes.

2012-08-22 Thread Daniel Vetter
On Mon, Aug 20, 2012 at 04:15:14PM -0700, Ben Widawsky wrote: > ERR_INT on HSW will display unclaimed MMIO accesses. This can be either > the result of a driver bug writing to an invalid addresses, or the > result of RC6. > > Signed-off-by: Ben Widawsky Both patches queued for -next, thanks. -Dan

Re: [Intel-gfx] [PATCH 16/29] drm/i915: Fix location of stolen memory register for SandyBridge+

2012-08-22 Thread Chris Wilson
On Mon, 20 Aug 2012 21:38:04 +0200, Daniel Vetter wrote: > On Sat, Aug 11, 2012 at 03:41:15PM +0100, Chris Wilson wrote: > > A few of the earlier registers where enlarged and so the Base Data of > > Stolem Memory Register (BDSM) was pushed to 0xb0. > > > > Signed-off-by: Chris Wilson > > --- > >

Re: [Intel-gfx] [PATCH 18/29] drm/i915: Delay allocation of stolen space for FBC

2012-08-22 Thread Chris Wilson
On Mon, 20 Aug 2012 21:51:42 +0200, Daniel Vetter wrote: > On Sat, Aug 11, 2012 at 03:41:17PM +0100, Chris Wilson wrote: > > As we may wish to wrap regions preallocated by the BIOS, we need to do > > that before carving out contiguous chunks of stolen space for FBC. > > > > Signed-off-by: Chris W

Re: [Intel-gfx] [PATCH 22/29] drm/i915: Handle stolen objects in pwrite

2012-08-22 Thread Chris Wilson
On Mon, 20 Aug 2012 21:56:08 +0200, Daniel Vetter wrote: > On Sat, Aug 11, 2012 at 03:41:21PM +0100, Chris Wilson wrote: > > Signed-off-by: Chris Wilson > > What about putting kmap/unmap abstractions into obj->ops (like the dma_buf > interface already has)? Since the pwrite/pread code is already

Re: [Intel-gfx] [PATCH 27/29] drm/i915: Allocate overlay registers from stolen memory

2012-08-22 Thread Chris Wilson
On Mon, 20 Aug 2012 23:17:06 +0200, Daniel Vetter wrote: > On Sat, Aug 11, 2012 at 03:41:26PM +0100, Chris Wilson wrote: > > Signed-off-by: Chris Wilson > > Since most of the overlay-supporting hw uses physical mem for the overlay > I think this isn't much worth it: The additional frobbery in >

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Find unclaimed MMIO writes.

2012-08-22 Thread Ben Widawsky
On 2012-08-22 06:15, Paulo Zanoni wrote: 2012/8/20 Ben Widawsky : ERR_INT on HSW will display unclaimed MMIO accesses. This can be either the result of a driver bug writing to an invalid addresses, or the result of RC6. Signed-off-by: Ben Widawsky For both patches: Reviewed-by: Paulo Zanoni

Re: [Intel-gfx] [PATCH v2] drm/i915: Cantiga+ cannot handle a hsync front porch of 0

2012-08-22 Thread Daniel Vetter
On Thu, Jun 21, 2012 at 01:19:59PM +0300, Jani Nikula wrote: > From: Chris Wilson > > This addresses WaPruneModeWithIncorrectHsyncOffset. > > Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=50236 > Signed-off-by: Chris Wilson > Signed-off-by: Jani Nikula Queued for -next (just to close a

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Find unclaimed MMIO writes.

2012-08-22 Thread Paulo Zanoni
2012/8/20 Ben Widawsky : > ERR_INT on HSW will display unclaimed MMIO accesses. This can be either > the result of a driver bug writing to an invalid addresses, or the > result of RC6. > > Signed-off-by: Ben Widawsky For both patches: Reviewed-by: Paulo Zanoni Tested-by: Paulo Zanoni This is a

Re: [Intel-gfx] [PATCH v2] drm/i915: fix color order for BGR formats on IVB

2012-08-22 Thread Antti Koskipää
Hi, On 08/22/12 12:17, Vijay Purushothaman wrote: > This is already fixed for ILK and SNB in the below commit but somehow > IVB is missed. > > commit ab2f9df10dd955f1fc0a8650e377588c98f1c029 > Author: Jesse Barnes > Date: Mon Feb 27 12:40:10 2012 -0800 > > drm/i915: fix color order for BG

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add ERR_INT to gen7 error state

2012-08-22 Thread Antti Koskipää
Both patches look ok. Reviewed-by: Antti Koskipaa On 08/21/12 02:15, Ben Widawsky wrote: > ERR_INT can generate interrupts. However since most of the conditions seem > quite fatal the patch opts to simply report it in error state instead of > adding more complexity to the interrupt handler for l

Re: [Intel-gfx] [PATCH 00/58] modeset-rework, the basic conversion

2012-08-22 Thread Lespiau, Damien
On Wed, Aug 22, 2012 at 11:46 AM, Lespiau, Damien wrote: > On Tue, Aug 21, 2012 at 7:11 PM, Daniel Vetter wrote: >>> Smoke-tested the new modeset-rework branch and found a regression on >>> my IVB with a pristine f17 userland: >>> >>> * start with LVDS + VGA >>> * unplug VGA >>> * LVDS goes black

Re: [Intel-gfx] [PATCH 00/58] modeset-rework, the basic conversion

2012-08-22 Thread Lespiau, Damien
On Tue, Aug 21, 2012 at 7:11 PM, Daniel Vetter wrote: >> Smoke-tested the new modeset-rework branch and found a regression on >> my IVB with a pristine f17 userland: >> >> * start with LVDS + VGA >> * unplug VGA >> * LVDS goes black > > Hm, not yet seen this one here. Can you attach a full dmesg w

Re: [Intel-gfx] [PATCH] drm/i915: fix color order for BGR formats on IVB

2012-08-22 Thread Vijay Purushothaman
On 8/22/2012 1:19 PM, Paul Menzel wrote: Dear Vijay, Am Mittwoch, den 22.08.2012, 11:47 +0530 schrieb Vijay Purushothaman: This is already fixed for ILK and SNB … in what commits? Added the previous commit number which solved this problem on Sandybridge and description in the second version

[Intel-gfx] [PATCH v2] drm/i915: fix color order for BGR formats on IVB

2012-08-22 Thread Vijay Purushothaman
This is already fixed for ILK and SNB in the below commit but somehow IVB is missed. commit ab2f9df10dd955f1fc0a8650e377588c98f1c029 Author: Jesse Barnes Date: Mon Feb 27 12:40:10 2012 -0800 drm/i915: fix color order for BGR formats on SNB Had the wrong bits and field definitions. Signed

Re: [Intel-gfx] Find bugs in i915 driver

2012-08-22 Thread Daniel Vetter
On Tue, Aug 21, 2012 at 09:20:37AM +0200, Daniel Vetter wrote: > On Mon, Aug 13, 2012 at 08:07:43AM +, Xu, Anhua wrote: > > Hi, Paul > > > > Thanks for your advice. I update my patch. Please review, for your > > question, please see my reply below. > > > > From d11080eda81c0503b5035ea40667b

Re: [Intel-gfx] [PATCH] drm/i915: fix color order for BGR formats on IVB

2012-08-22 Thread Paul Menzel
Dear Vijay, Am Mittwoch, den 22.08.2012, 11:47 +0530 schrieb Vijay Purushothaman: > This is already fixed for ILK and SNB … in what commits? > but somehow IVB is missed. > > Signed-off-by: Vijay Purushothaman > Signed-off-by: Ben Lin > --- > drivers/gpu/drm/i915/intel_sprite.c |6 +++---