Re: [Intel-gfx] [PATCH v6 4/4] drm/i915: ironlake_write_eld code cleanup

2012-08-14 Thread Wang, Xingchao
> -Original Message- > From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter > Sent: Tuesday, August 14, 2012 7:49 PM > To: Wang, Xingchao > Cc: dan...@ffwll.ch; przan...@gmail.com; intel-gfx@lists.freedesktop.org > Subject: Re: [PATCH v6 4/4] drm/i915: ironlake_w

Re: [Intel-gfx] [PATCH v7 3/4] drm/i915: Haswell HDMI audio initialization

2012-08-14 Thread Wang, Xingchao
Hi Daniel/Imre, This revised version changelog: - add " Wait for 1 vertical blank" after enable audio output port - configure pipe related transcoder instead of operate all transcoders blindly Thanks --xingchao > -Original Message- > From: Wang, Xingchao > Sent: Wednesday, August 15, 2

[Intel-gfx] [PATCH v7 3/4] drm/i915: Haswell HDMI audio initialization

2012-08-14 Thread Wang Xingchao
Added new haswell_write_eld() to initialize Haswell HDMI audio registers to generate an unsolicited response to the audio controller driver to indicate that the controller sequence should start. Signed-off-by: Wang Xingchao --- drivers/gpu/drm/i915/i915_reg.h |1 + drivers/gpu/drm/i915/

Re: [Intel-gfx] [PATCH v6 3/4] drm/i915: Haswell HDMI audio initialization

2012-08-14 Thread Wang, Xingchao
> -Original Message- > From: Imre Deak [mailto:imre.d...@gmail.com] > Sent: Tuesday, August 14, 2012 8:36 PM > To: Wang, Xingchao > Cc: dan...@ffwll.ch; przan...@gmail.com; intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH v6 3/4] drm/i915: Haswell HDMI audio > initializat

[Intel-gfx] question about vblank

2012-08-14 Thread Xu, Anhua
Hi, All One question puzzle me is the update point of some register like DSPASURF (7019Ch), in Bspec it mentioned that it is at "Start of vertical blank or pipe disbaled". So it means that if pipe disabled, the writing of DSPASURF have effect on hardware status once this writing complete and we

[Intel-gfx] [PATCH 5/5] drm/i915/contexts: Serialize default context init

2012-08-14 Thread Ben Widawsky
This is possible with the new force parameter in do_switch. As stated in that patch, the goal is to get a real context stored at the time of initialization. References: https://bugs.freedesktop.org/show_bug.cgi?id=52429 Tested-by: Guang A Yang Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i91

[Intel-gfx] [PATCH 4/5] drm/i915/contexts: Add forced switches

2012-08-14 Thread Ben Widawsky
A force parameter for switch currently only has one use, the first time we load the default context. Slightly hand-wavy explanation: We want to get the default context actually loaded so that the GPU has some real state to load (instead of garbage) after a reset or resume. The reason it's hand-wav

[Intel-gfx] [PATCH 3/5] drm/i915/contexts: Switch to default on resume

2012-08-14 Thread Ben Widawsky
In order to make the HW state CCID match with what we think it should be, we must order a switch to the default context. The really sad thing here is that the switch can potentially fail, and as such we have to assume contexts no longer work. There is likely room for improvement but until we actua

[Intel-gfx] [PATCH 2/5] drm/i915/contexts: fix list corruption

2012-08-14 Thread Ben Widawsky
After reset we unconditionally reinitialize lists. If the context switch hasn't yet completed before the suspend, the default context object will end up on lists that are going to go away when we resume. The patch forces the context switch to be synchronous before suspend assuring that the active/

[Intel-gfx] [PATCH 1/5] drm/i915: Cleanup instdone state

2012-08-14 Thread Ben Widawsky
Clear the cached instdone state to match what we expect from hardware and prevent us from comparing stale values. Actually, clearing the state is not the same as setting idle state. There would be a known state of idle (ie. all units are done), but since it differs for every platform, we can just

[Intel-gfx] [PATCH 0/5] Some HW context fixes

2012-08-14 Thread Ben Widawsky
Daniel, the first 3 patches I believe are all that's required to fix https://bugs.freedesktop.org/show_bug.cgi?id=52429 The latter 2 are things we've discussed sort of. I've managed to go back and forth several times on whether or not we actually need them, so I'll just let you decide if you want t

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Cleanup instdone state when idle

2012-08-14 Thread Chris Wilson
On Tue, 14 Aug 2012 09:42:07 -0700, Ben Widawsky wrote: > On 2012-08-14 00:39, Chris Wilson wrote: > > On Mon, 13 Aug 2012 22:41:11 -0700, Ben Widawsky > > wrote: > >> The previous state is bogus when we've gone into idle. Actually > >> there > >> would be a known state of idle (ie. all units a

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Cleanup instdone state when idle

2012-08-14 Thread Ben Widawsky
On 2012-08-14 00:39, Chris Wilson wrote: On Mon, 13 Aug 2012 22:41:11 -0700, Ben Widawsky wrote: The previous state is bogus when we've gone into idle. Actually there would be a known state of idle (ie. all units are done), but since it differs for every platform, we can just set 0, and let t

Re: [Intel-gfx] [PATCH 3/4] drm/i915/contexts: Serialize default context init

2012-08-14 Thread Ben Widawsky
On 2012-08-14 00:41, Chris Wilson wrote: On Mon, 13 Aug 2012 22:41:10 -0700, Ben Widawsky wrote: This is possible with the new force paramter in do_switch. As stated in that patch, the goal is to get a real context stored at the time of initialization. References: https://bugs.freedesktop.org

Re: [Intel-gfx] [PATCH] drm/i915: fix hsw uncached pte

2012-08-14 Thread Keith Packard
Paulo Zanoni writes: > +#define HSW_PTE_UNCACHED 0x Are you sure this value should be zero? It seems pretty unlikely to me. -- keith.pack...@intel.com pgptzbyqd415W.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lis

[Intel-gfx] [PATCH] drm/i915: fix hsw uncached pte

2012-08-14 Thread Paulo Zanoni
From: Daniel Vetter They've changed it ... for no apparent reason. Meh. V2: remove unused 'is_hsw' field. Signed-off-by: Daniel Vetter Signed-off-by: Paulo Zanoni --- drivers/char/agp/intel-agp.h|1 + drivers/char/agp/intel-gtt.c| 105 +++

Re: [Intel-gfx] [PATCH] drm/i915: fix hsw uncached pte

2012-08-14 Thread Jani Nikula
On Tue, 14 Aug 2012, Paulo Zanoni wrote: > From: Daniel Vetter > > They've changed it ... for no apparent reason. Meh. > > Signed-off-by: Daniel Vetter > --- > drivers/char/agp/intel-agp.h| 1 + > drivers/char/agp/intel-gtt.c| 107 > > dri

[Intel-gfx] [PATCH] drm/i915: fix hsw uncached pte

2012-08-14 Thread Paulo Zanoni
From: Daniel Vetter They've changed it ... for no apparent reason. Meh. Signed-off-by: Daniel Vetter --- drivers/char/agp/intel-agp.h| 1 + drivers/char/agp/intel-gtt.c| 107 drivers/gpu/drm/i915/i915_gem_gtt.c | 5 +- drivers/gpu/drm/i9

Re: [Intel-gfx] [PATCH v6 3/4] drm/i915: Haswell HDMI audio initialization

2012-08-14 Thread Imre Deak
On Fri, Aug 10, 2012 at 5:52 PM, Wang, Xingchao wrote: > HI Deak, > >> -Original Message- >> From: Imre Deak [mailto:imre.d...@gmail.com] >> Sent: Friday, August 10, 2012 9:15 PM >> To: Wang, Xingchao >> Cc: dan...@ffwll.ch; przan...@gmail.com; intel-gfx@lists.freedesktop.org >> Subject: R

Re: [Intel-gfx] [PATCH v6 4/4] drm/i915: ironlake_write_eld code cleanup

2012-08-14 Thread Daniel Vetter
On Thu, Aug 09, 2012 at 04:52:18PM +0800, Wang Xingchao wrote: > Use _PIPE macro to get correct register definition for IBX/CPT, discard > old variable "i" way. > > Signed-off-by: Wang Xingchao Ok, I've slurped in patches 1,2&4 for -next (with a bit of frobbing since one of the #defines used in

Re: [Intel-gfx] [pull] -fixes for 3.6

2012-08-14 Thread Daniel Vetter
Meh, I've again forgotten about all the cc's ... /me needs coffee On Tue, Aug 14, 2012 at 10:28 AM, Daniel Vetter wrote: > Hi Dave, > > A few important fixers: > - fix various lvds backlight issues, regressed in 3.6 (Takashi Iwai) > - make the retina mbp work (ignore bogus edp bpc value in vbt)

Re: [Intel-gfx] [PATCH] drm/i915: Apply post-sync write for pipe control invalidates

2012-08-14 Thread Daniel Vetter
jk Sat, Aug 11, 2012 at 12:20:19PM -0700, Ben Widawsky wrote: > On Fri, 10 Aug 2012 10:18:10 +0100 > Chris Wilson wrote: > > > When invalidating the TLBs it is documentated as requiring a post-sync > > write. Failure to do so seems to result in a GPU hang. > > > > Exposure to this hang on IVB se

Re: [Intel-gfx] [PATCH 3/4] drm/i915/contexts: Serialize default context init

2012-08-14 Thread Chris Wilson
On Mon, 13 Aug 2012 22:41:10 -0700, Ben Widawsky wrote: > This is possible with the new force paramter in do_switch. As stated in > that patch, the goal is to get a real context stored at the time of > initialization. > > References: https://bugs.freedesktop.org/show_bug.cgi?id=52429 > Tested-by:

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Cleanup instdone state when idle

2012-08-14 Thread Chris Wilson
On Mon, 13 Aug 2012 22:41:11 -0700, Ben Widawsky wrote: > The previous state is bogus when we've gone into idle. Actually there > would be a known state of idle (ie. all units are done), but since it > differs for every platform, we can just set 0, and let the hangcheck > progress as normal. > >

Re: [Intel-gfx] [PATCH] drm/i915: reorder edp disabling to fix ivb MacBook Air

2012-08-14 Thread Daniel Vetter
On Mon, Aug 13, 2012 at 10:35:26PM -0700, Keith Packard wrote: > Daniel Vetter writes: > > > Cc: Keith Packard > > I tried this on top of v3.5, appears to work just fine. Thanks! > > Tested-by: Keith Packard Merged to -fixes, thanks for testing. -Daniel -- Daniel Vetter Mail: dan...@ffwll.c

Re: [Intel-gfx] [PATCH 1/4] drm/i915/contexts: fix list corruption

2012-08-14 Thread Chris Wilson
On Mon, 13 Aug 2012 22:41:08 -0700, Ben Widawsky wrote: > After reset we unconditionally reinitialize lists. If the context switch > hasn't yet completed before the suspend the default context object will > end up on lists that are going to go away when we resume. > > The patch forces the context