Only count interrupts we find came from the GPU.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_irq.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 453ea7c..36732f7 100644
--- a/driver
We can leave vblank interrupts masked but enabled so we're not dependent
on the first client to toggle the disable timer. We can also mask all
render based interrupts, since the ring code will handle unmasking them
for us.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_irq.c | 12 +
Needs some more work and testing.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ccabadd..f44ae6f 100644
--- a/drivers/gpu/drm/i915/i915
With the code in place, we can bind the driver, should make bisect possible.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9e772bd..ae46c3d 100644
-
VLV is a gen7 device, but we don't currently handle that in the switch.
So add it and write the PTEs correctly.
Signed-off-by: Jesse Barnes
---
drivers/char/agp/intel-gtt.c |1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index c1
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_crt.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 1333a65..ac62f24 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.
And restructure the IRQ handling a little. We can use pipestat for most
things, and make sure we don't affect pipe events when enabling and
disabling vblank interupts.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_irq.c | 62 +--
1 file changed,
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_pm.c |7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d0ce2a5..4fa1a78 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
The PTE format is similar to SNB, but we don't support an MLC and don't
need chipset flushing.
Signed-off-by: Jesse Barnes
---
drivers/char/agp/intel-gtt.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.
Since the offsets have all moved around.
v2: switch IS_DISPLAYREG and IS_VALLEYVIEW checks around since the latter is
cheaper (Daniel)
bail out early in IS_DISPLAYREG if the reg is in the new range (Daniel)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.c | 87 +
Add some VLV limit structures and update the PLL code.
v2: resolve conflicts, Vijay to re-post with PLL valid checks and fixed limits
v3: re-add dpio write function
v4: squash in Vijay's fixes for the PLL limits and clean up the m/n finder
Signed-off-by: Shobhit Kumar
Signed-off-by: Vijay Purush
ValleyView is similar to IbexPeak here, but with different register
offsets.
v2: use SDVOB instead ov VLV_HDMIB (Daniel)
drop unnecessary eDP check in DP_C init (Daniel)
eDP support will be coming later from Shobit.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_reg.h |
Might be able to merge this back in at some point, but we're seeing bugs
with ADPA based detection, so keep it separate for now with explicit
hotplug trigger usage.
v2: drop superfluous debug message
v3: comment forced detection, need to debug (Eugeni)
Reviewed-by: Eugeni Dodonov
Signed-off-by:
From: Shobhit Kumar
VLV supports two dp panels, there are two set of panel power sequence
registers which needed to be programmed based on the configured
pipe. This patch add supports for the same
Acked-by: Acked-by: Ben Widawsky
Signed-off-by: Beeresh G
Reviewed-by: Vijay Purushothaman
Revie
On 06/13/2012 02:29 PM, Chris Wilson wrote:
> As a w/a to prevent reads sporadically returning 0, we need to wait for
> the GT thread to return to TC0 before proceeding to read the registers.
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=50243
> Signed-off-by: Chris Wilson
Reviewe
On Fri, Jun 15, 2012 at 10:31:06AM -0700, Jesse Barnes wrote:
> On Fri, 15 Jun 2012 10:34:22 +0300
> Jani Nikula wrote:
> > Hi Jesse, I'm sure you meant to do *something* with that return value. I
> > presume it should be equal to intel_dp->edid_mode_count, but is it
> > possible it's not? Is it b
On Fri, 15 Jun 2012 10:34:22 +0300
Jani Nikula wrote:
> On Thu, 14 Jun 2012, Jesse Barnes wrote:
> > They aren't going anywhere, and probing on DDC can cause the panel to
> > blank briefly, so read them up front and cache them for later queries.
> >
> > v2: fix potential NULL derefs in intel_dp_
On 06/13/2012 04:47 PM, Chris Wilson wrote:
> On Wed, 13 Jun 2012 12:07:19 -0700, Ben Widawsky wrote:
>> On Wed, 13 Jun 2012 18:29:51 +0100
>> Chris Wilson wrote:
>>
>>> Tidy up the routines for interacting with the GT (in particular the
>>> forcewake dance) which are scattered throughout the cod
On 15.06.2012 16:47, Eugeni Dodonov wrote:
> On Fri, Jun 15, 2012 at 11:36 AM, Daniel Vetter wrote:
>
>> Both the MAINTAINERS file in the kernel and our OTC graphics page are
>> updated, see:
>>
>> http://intellinuxgraphics.org/download.html
>>
>> Can you please tell me where Keith's repo is stil
On Fri, Jun 15, 2012 at 11:36 AM, Daniel Vetter wrote:
> Both the MAINTAINERS file in the kernel and our OTC graphics page are
> updated, see:
>
> http://intellinuxgraphics.org/download.html
>
> Can you please tell me where Keith's repo is still referred to?
>
Also, note that by some weird reaso
replaced hardcoded numbers with valid PLL limit values
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/intel_display.c | 52 +
1 files changed, 21 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i9
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/intel_display.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 157dcb0a..0707b7a 100644
--- a/drivers/gpu/drm/i915/intel_di
Fixed the wrong p2 PLL values and replaced all hardcoded numbers in best PLL
calculation. These two patches should be applied on top of Jesse's Jun 14
Valleyview patch set.
Tried to refactor the code to avoid so many nested loops but ended up messing
other VLV code. Any help with code refactorin
On Fri, Jun 15, 2012 at 12:17 PM, Johannes Bauer wrote:
> Hi list,
>
> sorry for this question, but I'm puzzled and cannot figure out the
> correct answer: What is actually the most recently updated GIT
> repository? I'd like to try a newer version (had previously issues with
> sleeping on Sandy B
On Fri, 15 Jun 2012 13:52:04 +0300, Jani Nikula
wrote:
> On Fri, 15 Jun 2012, Chris Wilson wrote:
> > They aren't going anywhere, and probing on DDC can cause the panel to
> > blank briefly, so read them up front and cache them for later queries.
> >
> > Jesse's patch revamped. Gotta love those
On Fri, 15 Jun 2012, Chris Wilson wrote:
> They aren't going anywhere, and probing on DDC can cause the panel to
> blank briefly, so read them up front and cache them for later queries.
>
> Jesse's patch revamped. Gotta love those display_info.raw_edid = NULL!
> ---
> drivers/gpu/drm/i915/intel_d
Hi list,
sorry for this question, but I'm puzzled and cannot figure out the
correct answer: What is actually the most recently updated GIT
repository? I'd like to try a newer version (had previously issues with
sleeping on Sandy Bridge).
Keith's repository (which is referred to by the website) ha
On Thu, Jun 14, 2012 at 10:15:00PM +0200, Daniel Vetter wrote:
> This reverts commit 092945e11c5b84f66dd08f0b87fb729715d377bc.
>
> This commit prevents a DP screen from properly training the link.
> Oddly enough it works, once the machine has been warm-booted with an
> older kernel.
>
> According
They aren't going anywhere, and probing on DDC can cause the panel to
blank briefly, so read them up front and cache them for later queries.
Jesse's patch revamped. Gotta love those display_info.raw_edid = NULL!
---
drivers/gpu/drm/i915/intel_dp.c| 48 +++-
d
On Thu, 14 Jun 2012, Jesse Barnes wrote:
> They aren't going anywhere, and probing on DDC can cause the panel to
> blank briefly, so read them up front and cache them for later queries.
>
> v2: fix potential NULL derefs in intel_dp_get_edid_modes and
> intel_dp_get_edid (Jani)
> copy full
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