Hi Dave,
The last pull I'd like to squeeze into 3.5, safe for the hsw stuff mostly
bugfixes:
- last few patches for basic hsw enabling (Eugeni, infoframe support by
Paulo)
- Fix up infoframe support, we've hopefully squashed all the cargo-culting
in there (Paulo). Among all the issues, this fi
On Wed, Apr 18, 2012 at 5:33 PM, Daniel Vetter wrote:
> Jesse, can you also please check whether we need the same thing on vlv?
> atm the the clock gating functions are almost identical safe for this wrt
> touching registers in the gt core.
Prod.
Now that you have a vlv, no more excuses ;-)
-Dan
On Sun, May 20, 2012 at 08:00:25PM +0200, Daniel Vetter wrote:
> This should fix breakage introduced in
>
> commit ee7b9f93fd96a72e5d09e2b44024c11880873c6b
> Author: Jesse Barnes
> Date: Fri Apr 20 17:11:53 2012 +0100
>
> drm/i915: manage PCH PLLs separately from pipes
>
> v2: Add a DRM_D
On Sun, May 20, 2012 at 11:07:46AM -0700, Daniel Kurtz wrote:
> On Sun, May 20, 2012 at 8:19 AM, Daniel Vetter wrote:
> >
> > On Sat, May 19, 2012 at 10:10:12PM +0200, Daniel Vetter wrote:
> > > ... too much risk for flaky edid transfers.
> > >
> > > This regression has been introduced in
> > >
>
This should fix breakage introduced in
commit ee7b9f93fd96a72e5d09e2b44024c11880873c6b
Author: Jesse Barnes
Date: Fri Apr 20 17:11:53 2012 +0100
drm/i915: manage PCH PLLs separately from pipes
v2: Add a DRM_DEBUG_KMS message to explain why a given pll was
selected, suggested by Chris Wils
This should fix breakage introduced in
commit ee7b9f93fd96a72e5d09e2b44024c11880873c6b
Author: Jesse Barnes
Date: Fri Apr 20 17:11:53 2012 +0100
drm/i915: manage PCH PLLs separately from pipes
v2: Add a DRM_DEBUG_KMS message to explain why a given pll was
selected, suggested by Chris Wils
On Sun, 20 May 2012 18:55:09 +0200, Daniel Vetter
wrote:
> This should fix breakage introduced in
>
> commit ee7b9f93fd96a72e5d09e2b44024c11880873c6b
> Author: Jesse Barnes
> Date: Fri Apr 20 17:11:53 2012 +0100
>
> drm/i915: manage PCH PLLs separately from pipes
>
> Cc: Jesse Barnes
>
The existing assertions were written under the assumption that we wanted
to test the related PLL to a CRTC. With the split of PLL into a
separately managed entity which may be shared amongst CRTCs, we need to
pass in both the CRTC and the PLL to the assertion routine.
Occassionally, this means pass
This should fix breakage introduced in
commit ee7b9f93fd96a72e5d09e2b44024c11880873c6b
Author: Jesse Barnes
Date: Fri Apr 20 17:11:53 2012 +0100
drm/i915: manage PCH PLLs separately from pipes
Cc: Jesse Barnes
Cc: Chris Wilson
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49712
On Mon, May 14, 2012 at 04:55:36PM -0300, Paulo Zanoni wrote:
> 2012/5/12 Daniel Vetter :
> > The CEA spec has a bunch of very peculiar modes. For backwards
> > compatibility it specifies a bunch of modes that are suitable to
> > display old SD TV content. But these modes have such low pixel clocks
On Mon, May 14, 2012 at 06:38:53PM -0300, Eugeni Dodonov wrote:
> On Mon, May 14, 2012 at 5:12 PM, Paulo Zanoni wrote:
>
> > From: Paulo Zanoni
> >
> > Both the control and data registers are completely different now.
> >
> > Signed-off-by: Paulo Zanoni
> >
>
> Both patches are:
> Reviewed-by:
After Daniel split out this code, I think this makes more sense, and
looks nicer. Also added some comments to help the situation.
v2: Make signal_mbox be all rings for symmetric-ness.
v3: submitted the wrong version of the patch before.
v2 had an issue with odd number of rings. The fix is to alw
On Sat, May 19, 2012 at 10:10:12PM +0200, Daniel Vetter wrote:
> ... too much risk for flaky edid transfers.
>
> This regression has been introduced in
>
> commit e646d5773572bf52017983d758bdf05777dc5600
> Author: Daniel Kurtz
> Date: Fri Mar 30 19:46:38 2012 +0800
>
> drm/i915/intel_i2c:
We have one bug report from a validation team that we get the eDP
panel sequencing still somewhat wrong: We need to enable VDD while
switching off the panel and backlight. Unfortunately that reporter
seems to have fallen off the earth :(
For another reporter this actually fixes a black panel issue
On Sun, May 20, 2012 at 11:17:36AM -0300, Eugeni Dodonov wrote:
> On Sat, May 12, 2012 at 3:22 PM, Daniel Vetter wrote:
>
> > At least the worst offenders:
> > - SDVO specifies that the encoder should compute the ecc. Testing also
> > shows that we must not send the ecc field, so copy the dip_inf
On Sat, May 12, 2012 at 3:22 PM, Daniel Vetter wrote:
> At least the worst offenders:
> - SDVO specifies that the encoder should compute the ecc. Testing also
> shows that we must not send the ecc field, so copy the dip_infoframe
> struct to a temporay place and avoid the ecc field. This way the
After Daniel split out this code, I think this makes more sense, and
looks nicer. Also added some comments to help the situation.
v2: Make signal_mbox be all rings for symmetric-ness.
v3: submitted the wrong version of the patch before.
v2 had an issue with odd number of rings. The fix is to alw
After Daniel split out this code, I think this makes more sense, and
looks nicer. Also added some comments to help the situation.
v2: Make signal_mbox be all rings for symmetric-ness.
Reviewed-by (v1): Chris Wilson
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_reg.h | 13
20/05/2012
Dear Intel Linux Graphics Developers,
Good Afternoon, First of all I highly appreciate the quality of Mesa 8.0.3
Intel Driver for my GM45 Graphics accelerator. It has come a long way since
Mesa 7.7.1 in regards to GLSL and FBO.
Now it can run many games with decent quality at least at
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