CC: Jesse Barnes
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_display.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3abebb5..30bcc61 100644
--- a/drivers/gpu/drm/i915/i
On Thu, 5 Apr 2012 20:48:20 +
"Reese, Armin C" wrote:
> The patch file for this change is attached. Had to send it from
> Outlook and wanted to avoid corrupting the patch. Hence, the
> attachment.
>
> Armin
I don't know about the pipe stuff, but anything with gtt_offset should
always be PA
On Fri, 6 Apr 2012 16:07:56 -0700
Ben Widawsky wrote:
> On Fri, 6 Apr 2012 11:46:27 -0700
> Jesse Barnes wrote:
>
> > Just noticed this while verifying the VGA disable code.
> >
> > Signed-off-by: Jesse Barnes
> > ---
> > drivers/gpu/drm/i915/intel_display.c |2 +-
> > 1 files changed,
On Fri, 6 Apr 2012 11:46:27 -0700
Jesse Barnes wrote:
> Just noticed this while verifying the VGA disable code.
>
> Signed-off-by: Jesse Barnes
> ---
> drivers/gpu/drm/i915/intel_display.c |2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/int
When the PCH split occurred, we dropped support for separate hsync and
vsync disable in the VGA DAC. So add a PCH specific DPMS function that
just uses the port enable bit for controlling DPMS states.
Before this fix, when anything other than a full DPMS off occurred,
the VGA port would be left e
Just noticed this while verifying the VGA disable code.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3abebb5..d13e8
