Sun, Yi would like to recall the message, "The Idea on Automating the
Testdisplay with DVMU".
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Hello,
I'm running vaapi-mplayer on debian wheezy, which has fairly up-to-date
intel drivers. (Right now i965-va-driver is outdated, so I use the sid
package of that.)
I do not have any window manager, only X and an xterm. (Really, not even
twm. It is only a test installation.)
Both output
On Fri, Sep 30, 2011 at 10:56:41PM +0100, Chris Wilson wrote:
> Reported-and-tested-by: Bo Wang < bo.b.w...@intel.com>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=36997
> Signed-off-by: Chris Wilson
I've noticed this old patch while strowling through bugzilla, and it
still applies. Q
On Sat, 31 Mar 2012 11:54:01 +0100, Chris Wilson
wrote:
> On Sat, 31 Mar 2012 11:21:57 +0200, Daniel Vetter
> wrote:
> > According to an internal workaround master list, we need to set bit 5
> > of register 9400 to avoid issues with color blits.
>
> This sounds like it could be the root cause
On Sat, 31 Mar 2012 11:21:57 +0200, Daniel Vetter
wrote:
> According to an internal workaround master list, we need to set bit 5
> of register 9400 to avoid issues with color blits.
This sounds like it could be the root cause behind the FBC + BLT hangs.
But not the XY_COPY hangs.
-Chris
--
Chr
On Sat, 31 Mar 2012 11:22:02 +0200, Daniel Vetter
wrote:
> Note that async flush also means things like VT-d IOTLB invalidation.
>
> See Bspec vol1c.4 "Render Engine Command Streamer", Section "ECOSKPD -
> Eco Scratch Pad".
>
> It doesn't seem to help in for any of our VT-d related bugs thoug.
Our workaround list kindly lists that this new default value needs to
be updated in Bspec. Naturally, this did not happen.
Signed-Off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_display.c |4
2 files changed, 5 insertions(+), 0 deletio
Note that async flush also means things like VT-d IOTLB invalidation.
See Bspec vol1c.4 "Render Engine Command Streamer", Section "ECOSKPD -
Eco Scratch Pad".
It doesn't seem to help in for any of our VT-d related bugs thoug.
Signed-Off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_reg.h
According to Bsepc, this should be set by default, but isn't. See vo1c.4
"Render Engine Command Streamer", Section 1.1.14.3 "3D_CHICKEN3"
Bspec also says that we always need to set all mask bits.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i91
For some reason snb has 2 fields to set ppgtt cacheability. This one
here does not exist on gen7.
This might explain why ppgtt wasn't a win on snb like on ivb - not
enough pte caching.
Signed-Off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_gem.c |3 +++
drivers/gpu/drm/i915/i915_reg.h |
Bspec says that we need to set this: vol1c.3 "Blitter Command
Streamer", Section 1.1.2.1 "GAB_CTL_REG - GAB Unit Control Register".
We don't really rely on pagefaults, but who knows what this all
affects.
Signed-Off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_gem.c |7 ++-
drivers/g
Contrary to the other clock gating w/a in GEN6_UCGCTL1, this one is
actually documented in Bspec, vol1g "GT Interface Registers [SNB]",
Section 1.5.1 "UCGCTL1 - Unit Level Clock Gating Control 1".
Supposedly this can prevent hangs on the media ring.
Signed-Off-by: Daniel Vetter
---
drivers/gpu/
According to an internal workaround master list, we need to set bit 5
of register 9400 to avoid issues with color blits.
Signed-Off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_reg.h |3 +++
drivers/gpu/drm/i915/intel_display.c |4
2 files changed, 7 insertions(+), 0 deletio
Hi all,
I've stitched together the following set of workarounds from internal sources in
the vain hope that they fix our VT-d troubles. Unfortunately that's not the
case. I also haven't seen any bug where these could apply to.
Anyway I think it's better to implement them, so please review.
Yours
On Mon, Mar 26, 2012 at 04:43:04PM -0400, Adam Jackson wrote:
> On Mon, 2012-03-26 at 22:37 +0200, Daniel Vetter wrote:
> > Ums is already disabled, but on ilk we can additionally disable gem
> > initialization when using user mode setting. Upstream never support
> > ilk without kernel modesetting
On Fri, Mar 30, 2012 at 09:31:27PM -0700, Ben Widawsky wrote:
> On Fri, 30 Mar 2012 11:28:40 -0700
> Jesse Barnes wrote:
>
> > On Fri, 30 Mar 2012 20:24:35 +0200
> > Daniel Vetter wrote:
> >
> > > vlv, ivb and snb all share the gen6+ gt irq handling. 3 copies of
> > > the same stuff is a bit mu
On Fri, Mar 30, 2012 at 09:31:27PM -0700, Ben Widawsky wrote:
> On Fri, 30 Mar 2012 11:28:40 -0700
> Jesse Barnes wrote:
>
> > On Fri, 30 Mar 2012 20:24:35 +0200
> > Daniel Vetter wrote:
> >
> > > vlv, ivb and snb all share the gen6+ gt irq handling. 3 copies of
> > > the same stuff is a bit mu
17 matches
Mail list logo
