Re: [Intel-gfx] [PATCH 09/26] drm/i915: split PLL update code out of i9xx_crtc_mode_set

On Thu, Mar 22, 2012 at 02:38:51PM -0700, Jesse Barnes wrote: > Makes it more readable and maintainable. ValleyView will add its own > PLL update function in a later patch. > > v2: split LVDS bits out of this patch (Daniel) > > Signed-off-by: Jesse Barnes > --- > drivers/gpu/drm/i915/intel_dis

Re: [Intel-gfx] [PATCH 08/26] drm/i915: add DPIO read/write functions for ValleyView

On Thu, Mar 22, 2012 at 02:38:50PM -0700, Jesse Barnes wrote: > ValleyView and similar hardware (like CedarView) put some display > related registers like the PLL controls and dividers on a DPIO bus. Add > simple indirect register access routines to get to those registers. > > v2: move new wait_f

Re: [Intel-gfx] [PATCH 05/26] drm/i915: PLL defines for VLV

On Thu, Mar 22, 2012 at 02:38:47PM -0700, Jesse Barnes wrote: > --- > drivers/gpu/drm/i915/i915_reg.h |9 + > drivers/gpu/drm/i915/intel_display.c | 10 +- > 2 files changed, 18 insertions(+), 1 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu

Re: [Intel-gfx] [PATCH 04/26] drm/i915: ValleyView watermark support

On Thu, Mar 22, 2012 at 02:38:46PM -0700, Jesse Barnes wrote: > Add support for ValleyView watermark handling. It's like Cantiga with a > few small differences (big FIFO mode and different WM limits). > > Signed-off-by: Jesse Barnes > --- > drivers/gpu/drm/i915/i915_reg.h |9 + > d

[Intel-gfx] [PATCH] drm/i915: add rc6 residency times to debugfs

RC6 residency should be in intervals of 1.28us, and the counter wraps. Here is an example using awk to get the RC6 and RC6+ residency in seconds, since boot. cat /sys/kernel/debug/dri/0/i915_drpc_info | grep residency | awk -F':' -F' ' '{print $5 * 1.28 / 100}' This is primarily for QA, bu

Re: [Intel-gfx] [PATCH 20/26] drm/i915: ValleyView has limited cacheability

On Thu, 22 Mar 2012 14:39:02 -0700 Jesse Barnes wrote: > The GT can snoop CPU writes, but doesn't snoop into the CPU cache when > it does writes, so we can't use the cache bits the same way. > > So map the status and pipe control pages as uncached on ValleyView, and > only set the pages to cache

Re: [Intel-gfx] [PATCH 07/26] drm/i915: add ValleyView clock gating init

On Thu, Mar 22, 2012 at 02:38:49PM -0700, Jesse Barnes wrote: > Set the same bits as IVB plus a few others. > > Signed-off-by: Jesse Barnes > --- > drivers/gpu/drm/i915/i915_reg.h | 18 + > drivers/gpu/drm/i915/intel_display.c | 46 > ++ > 2

Re: [Intel-gfx] [PATCH 03/26] drm/i915: add ValleyView driver structs and IS_VALLEYVIEW macro

On Thu, Mar 22, 2012 at 02:38:45PM -0700, Jesse Barnes wrote: > For use by the rest of the ValleyView code. > > Signed-off-by: Jesse Barnes > --- > drivers/gpu/drm/i915/i915_drv.c | 18 ++ > drivers/gpu/drm/i915/i915_drv.h |2 ++ > 2 files changed, 20 insertions(+), 0 delet

Re: [Intel-gfx] [PATCH 02/26] drm/i915: re-order GT IIR bit definitions

On Thu, Mar 22, 2012 at 02:38:44PM -0700, Jesse Barnes wrote: > They were all over the place, order them by position and add a few. > > v2: add gen indications to the new bits (Ben) > > Signed-off-by: Jesse Barnes Reviewed-by: Ben Widawsky ___ Intel-g

Re: [Intel-gfx] [PATCH 01/26] drm/i915: move NEEDS_FORCE_WAKE to i915_drv.c

On Thu, Mar 22, 2012 at 02:38:43PM -0700, Jesse Barnes wrote: > It's only used by the main read/write functions, so we can keep it with > them. > > Signed-off-by: Jesse Barnes > --- > drivers/gpu/drm/i915/i915_drv.c |6 ++ > drivers/gpu/drm/i915/i915_drv.h |6 -- > 2 files change

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add lvds_channel module option

On Tue, Mar 20, 2012 at 01:07:06PM +0100, Takashi Iwai wrote: > Add a new module optoin lvds_channel to specify the LVDS channel mode > explicitly instead of probing the LVDS register value set by BIOS. > This will be helpful when VBT is broken or incompatible with the > current code. > > Bugzilla

[Intel-gfx] [PATCH 14/26] drm/i915: Enable HDMI on ValleyView

From: Shobhit Kumar HDMI register offsets are different in Valleyview. Add support for the same. v2: drop superfluous comments in HDMI init (Daniel) Signed-off-by: Beeresh G Signed-off-by: Shobhit Kumar Reviewed-by: Vijay Purushothaman Reviewed-by: Jesse Barnes Signed-off-by: Jesse Barnes

[Intel-gfx] [PATCH 15/26] agp/intel: map more registers for use by the GTT code

We need to flush the Gunit TLB when we update GTT PTEs on VLV, but the register for doing so is above the range we normally map. Map the whole register space to make sure we can get it. v2: only map the larger space on gen7+ (Daniel) Signed-off-by: Jesse Barnes --- drivers/char/agp/intel-gtt.c

[Intel-gfx] [PATCH 10/26] drm/i915: split LVDS update code out of i9xx_crtc_mode_set

Just to make things clearer and reduce the size of this monstrosity. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 117 ++ 1 files changed, 63 insertions(+), 54 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gp

[Intel-gfx] [PATCH 11/26] drm/i915: ValleyView mode setting limits and PLL functions

Add some VLV limit structures and update the PLL code. v2: resolve conflicts, Vijay to re-post with PLL valid checks and fixed limits Signed-off-by: Shobhit Kumar Signed-off-by: Vijay Purushothaman --- drivers/gpu/drm/i915/i915_reg.h |1 + drivers/gpu/drm/i915/intel_display.c | 231 +

[Intel-gfx] [PATCH 16/26] agp/intel: add ValleyView AGP driver

But don't bind the PCI ID yet. Signed-off-by: Jesse Barnes --- drivers/char/agp/intel-agp.c |1 + drivers/char/agp/intel-agp.h |3 +++ drivers/char/agp/intel-gtt.c | 23 +++ 3 files changed, 27 insertions(+), 0 deletions(-) diff --git a/drivers/char/agp/intel-agp.c

[Intel-gfx] [PATCH 17/26] agp/intel: bind ValleyView AGP driver

With the code in place, we can bind this driver. Signed-off-by: Jesse Barnes --- drivers/char/agp/intel-gtt.c |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c index ccc0045..08336ba 100644 --- a/drivers/char/agp

[Intel-gfx] [PATCH 21/26] drm/i915: ValleyView IRQ support

ValleyView has a new interrupt architecture; best to put it in a new set of functions. Also make sure the ring mask functions handle ValleyView. FIXME: fix flipping; need to enable interrupts and call prepare/finish Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_debugfs.c | 40

[Intel-gfx] [PATCH 22/26] drm/i915: display regs are at 0x180000 on ValleyView

Although internally the MMIO offsets for display regs haven't changed, their visibility through the PCI BAR has been affected by the addition of the Gunit, which occupies the low part of the address space. Display regs on VLV are offset into the BAR by 0x18, so we need to add that for any disp

[Intel-gfx] [PATCH 20/26] drm/i915: ValleyView has limited cacheability

The GT can snoop CPU writes, but doesn't snoop into the CPU cache when it does writes, so we can't use the cache bits the same way. So map the status and pipe control pages as uncached on ValleyView, and only set the pages to cached if we're on a supported platform. v2: add clarifying comments an

[Intel-gfx] [PATCH 23/26] drm/i915: check for disabled interrupts on ValleyView

Haven't seen this yet, but it doesn't hurt. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_gem.c |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 1f441f5..9cef64b 100644 --- a/drivers/gpu/

[Intel-gfx] [PATCH 24/26] drm/i915: add HDMI and DP port enumeration on ValleyView

ValleyView is similar to IbexPeak here, but with different register offsets. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 18 ++ 1 files changed, 18 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i91

[Intel-gfx] [PATCH 12/26] drm/i915: program drain latency regs on ValleyView

From: Gajanan Bhat This patch adds support for programming drain latency registers of Pondicherry memory arbiter of Valleyview. v2: clarify function names (Daniel) fix summary typo (Daniel) Signed-off-by: Gajanan Bhat Reviewed-by: Shobhit Kumar Reviewed-by: Vijay Purushothaman Reviewed-b

[Intel-gfx] [PATCH 13/26] drm/i915: Enable DP panel power sequencing for ValleyView

From: Shobhit Kumar VLV supports two dp panels, there are two set of panel power sequence registers which needed to be programmed based on the configured pipe. This patch add supports for the same Acked-by: Acked-by: Ben Widawsky Signed-off-by: Beeresh G Reviewed-by: Vijay Purushothaman Revie

[Intel-gfx] [PATCH 19/26] drm/i915: add ValleyView specific force wake get/put functions

ValleyView handles force wake differently than previous chipsets, so add a couple of new functions for it. But leave it disabled by default until we test it (need a chip with the Punit enabled first). Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_drv.c | 28 ++

[Intel-gfx] [PATCH 18/26] drm/i915: add ValleyView specific CRT detect function

Might be able to merge this back in at some point, but we're seeing bugs with ADPA based detection, so keep it separate for now with explicit hotplug trigger usage. v2: drop superfluous debug message Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_crt.c | 38 +++

[Intel-gfx] [PATCH 26/26] drm/i915: bind driver to ValleyView chipsets

With the code in place, we can bind the driver, should make bisect possible. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_drv.c |3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 094baf3.

[Intel-gfx] [PATCH 25/26] drm/i915: disable turbo on ValleyView for now

We'll probably need new init functions and will need to test it. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_suspend.c |2 +- drivers/gpu/drm/i915/intel_display.c |4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_suspend.c b

[Intel-gfx] [PATCH 09/26] drm/i915: split PLL update code out of i9xx_crtc_mode_set

Makes it more readable and maintainable. ValleyView will add its own PLL update function in a later patch. v2: split LVDS bits out of this patch (Daniel) Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 291 -- 1 files changed, 172 inserti

[Intel-gfx] [PATCH 07/26] drm/i915: add ValleyView clock gating init

Set the same bits as IVB plus a few others. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_reg.h | 18 + drivers/gpu/drm/i915/intel_display.c | 46 ++ 2 files changed, 64 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i

[Intel-gfx] [PATCH 08/26] drm/i915: add DPIO read/write functions for ValleyView

ValleyView and similar hardware (like CedarView) put some display related registers like the PLL controls and dividers on a DPIO bus. Add simple indirect register access routines to get to those registers. v2: move new wait_for macro to intel_drv.h (Ben) fix DPIO_PKT double write (Ben) ad

[Intel-gfx] [PATCH 06/26] drm/i915: interrupt bit definitions for VLV

--- drivers/gpu/drm/i915/i915_reg.h | 41 +++ 1 files changed, 41 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 869c695..1af17e0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gp

[Intel-gfx] [PATCH 05/26] drm/i915: PLL defines for VLV

--- drivers/gpu/drm/i915/i915_reg.h |9 + drivers/gpu/drm/i915/intel_display.c | 10 +- 2 files changed, 18 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0540099..869c695 100644 --- a/drivers/gpu/drm/i

[Intel-gfx] [PATCH 04/26] drm/i915: ValleyView watermark support

Add support for ValleyView watermark handling. It's like Cantiga with a few small differences (big FIFO mode and different WM limits). Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_reg.h |9 + drivers/gpu/drm/i915/intel_display.c | 65 +

[Intel-gfx] [PATCH 02/26] drm/i915: re-order GT IIR bit definitions

They were all over the place, order them by position and add a few. v2: add gen indications to the new bits (Ben) Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_reg.h | 20 ++-- 1 files changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i91

[Intel-gfx] [PATCH 03/26] drm/i915: add ValleyView driver structs and IS_VALLEYVIEW macro

For use by the rest of the ValleyView code. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_drv.c | 18 ++ drivers/gpu/drm/i915/i915_drv.h |2 ++ 2 files changed, 20 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 01/26] drm/i915: move NEEDS_FORCE_WAKE to i915_drv.c

It's only used by the main read/write functions, so we can keep it with them. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_drv.c |6 ++ drivers/gpu/drm/i915/i915_drv.h |6 -- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv

[Intel-gfx] [RFCv2] ValleyView support

I incorporated all the comments so far but avoided the big ugly of the display offset for now until we figure out what we want to do. The code is also available in my drm-intel git tree on kernel.org under the vlv-upstream branch. Thanks, Jesse ___ Int

Re: [Intel-gfx] [PATCH 19/25] drm/i915: display regs are at 0x180000 on ValleyView

On Wed, 21 Mar 2012 14:36:47 -0700 Jesse Barnes wrote: > On Wed, 21 Mar 2012 22:33:43 +0100 > Daniel Vetter wrote: > > > On Wed, Mar 21, 2012 at 12:48:40PM -0700, Jesse Barnes wrote: > > > Although internally the MMIO offsets for display regs haven't changed, > > > their visibility through the

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Check VBIOS value for determining LVDS dual channel mode, too

2012/3/20 Takashi Iwai : > > This patch adds a workaround for that problem by checking the initial > LVDS register value in VBT. > > Reviewed-by: Rodrigo Vivi > Reviewed-by: Adam Jackson > Signed-off-by: Takashi Iwai Tested on 4 laptops. Two of them with docking stations so I didn't need to ope

Re: [Intel-gfx] [PATCH 03/25] drm/i915: re-order GT IIR bit definitions

On Wed, 21 Mar 2012 18:10:36 -0700 Ben Widawsky wrote: > On Wed, 21 Mar 2012 12:48:24 -0700 > Jesse Barnes wrote: > > > They were all over the place, order them by position and add a few. > > > > Signed-off-by: Jesse Barnes > > --- > > drivers/gpu/drm/i915/i915_reg.h | 20 ++---

Re: [Intel-gfx] [PATCH 10/25] drm/i915: Enable DP panel power sequencing for ValleyView

On Wed, 21 Mar 2012 12:48:31 -0700 Jesse Barnes wrote: > VLV supports two dp panels, there are two set of panel power sequence > registers which needed to be programmed based on the configured > pipe. This patch add supports for the same > > Signed-off-by: Beeresh G > Reviewed-by: Vijay Purusho

Re: [Intel-gfx] [PATCH 04/25] drm/i915: Add basic support for parsing of VBT OEM Custom Block

On Thu, 22 Mar 2012 09:11:37 -0700 Ben Widawsky wrote: > On Thu, 22 Mar 2012 08:45:32 -0700 > Jesse Barnes wrote: > > > On Wed, 21 Mar 2012 18:30:11 -0700 > > Ben Widawsky wrote: > > > > > On Wed, 21 Mar 2012 12:48:25 -0700 > > > Jesse Barnes wrote: > > > > > > > From: Rohit Jain > > > >

Re: [Intel-gfx] [PATCH 2/2] drm/i915: [dinq] fix two instances -Wunitialized

On Wed, Feb 15, 2012 at 02:42:43PM +0100, Ben Widawsky wrote: > Introduced in commit 8461d226 and 8c59967c > > Cc: Daniel Vetter > Signed-off-by: Ben Widawsky I've merged this two here, but not before adding some grumpy complains about gcc (and doing a s/fix/shut up/ in the commit headlines). -

Re: [Intel-gfx] [PATCH 2/2] drm/i915: use semaphores for the display plane

On Thu, 22 Mar 2012 16:18:54 + Chris Wilson wrote: > On Thu, 22 Mar 2012 09:07:09 -0700, Ben Widawsky wrote: > > On Thu, 22 Mar 2012 09:56:07 + > > Chris Wilson wrote: > > > > > On Wed, 21 Mar 2012 17:19:13 -0700, Ben Widawsky > > > wrote: > > > > * For the display plane, we want to

Re: [Intel-gfx] [PATCH 2/2] drm/i915: use semaphores for the display plane

On Thu, 22 Mar 2012 09:07:09 -0700, Ben Widawsky wrote: > On Thu, 22 Mar 2012 09:56:07 + > Chris Wilson wrote: > > > On Wed, 21 Mar 2012 17:19:13 -0700, Ben Widawsky > > wrote: > > > * For the display plane, we want to be in the GTT but out of any > > > write > > > - * domains. So in many

Re: [Intel-gfx] [PATCH 04/25] drm/i915: Add basic support for parsing of VBT OEM Custom Block

On Thu, 22 Mar 2012 08:45:32 -0700 Jesse Barnes wrote: > On Wed, 21 Mar 2012 18:30:11 -0700 > Ben Widawsky wrote: > > > On Wed, 21 Mar 2012 12:48:25 -0700 > > Jesse Barnes wrote: > > > > > From: Rohit Jain > > > > > > Added support for parsing the OEM Customizable Modes Block (#20) > > > in

Re: [Intel-gfx] [PATCH 2/2] drm/i915: use semaphores for the display plane

On Thu, 22 Mar 2012 09:56:07 + Chris Wilson wrote: > On Wed, 21 Mar 2012 17:19:13 -0700, Ben Widawsky > wrote: > > In theory this will have performance and power improvements. > > Performance because we don't need to stall when the scanout BO is > > busy, and power because we don't have to s

Re: [Intel-gfx] [PATCH 04/25] drm/i915: Add basic support for parsing of VBT OEM Custom Block

On Wed, 21 Mar 2012 18:30:11 -0700 Ben Widawsky wrote: > On Wed, 21 Mar 2012 12:48:25 -0700 > Jesse Barnes wrote: > > > From: Rohit Jain > > > > Added support for parsing the OEM Customizable Modes Block (#20) > > in the VBIOS table. > > > > Signed-off-by: Rohit Jain > > Reviewed-by: Shobhi

Re: [Intel-gfx] [PATCH] drm/i915: Sanitize BIOS debugging bits from PIPECONF

On Thu, Mar 22, 2012 at 12:00, Chris Wilson wrote: > Quoting the BSpec from time immemorial: > > PIPEACONF, bits 28:27: Frame Start Delay (Debug) > > Used to delay the frame start signal that is sent to the display planes. > Care must be taken to insure that there are enough lines during VBLANK

[Intel-gfx] [PATCH 2/2] drm/i915: Remove fence pipelining infrastructure

I have failed to find a way to make this work without random GPU deaths, so remove the ability to pipeline a fence update using the GPU. In the process, we can refactor the code to improve the error handling and avoid unnecessary modifications to our VMA if we do not need to update the fence regist

[Intel-gfx] [PATCH 1/2] drm/i915: Reorganise rules for get_fence/put_fence

By simplifying the rules to calling get_fence when writing to the through the GTT in a tiled manner, and calling put_fence before writing to the object through the GTT in a linear manner, the code becomes clearer and there is less chance of making a mistake. Signed-off-by: Chris Wilson --- drive

Re: [Intel-gfx] [PATCH 08/25] drm/i915: ValleyView mode setting limits and PLL functions

> -Original Message- > From: intel-gfx- > bounces+vijay.a.purushothaman=intel@lists.freedesktop.org [mailto:intel- > gfx-bounces+vijay.a.purushothaman=intel@lists.freedesktop.org] On > Behalf Of Ben Widawsky > Sent: Wednesday, March 21, 2012 8:54 PM > To: Jesse Barnes > Cc: intel-gf

[Intel-gfx] [PATCH] drm/i915: Sanitize BIOS debugging bits from PIPECONF

Quoting the BSpec from time immemorial: PIPEACONF, bits 28:27: Frame Start Delay (Debug) Used to delay the frame start signal that is sent to the display planes. Care must be taken to insure that there are enough lines during VBLANK to support this setting. An instance of the BIOS leavin

Re: [Intel-gfx] [PATCH 07/37] drm/i915: add DP_TP_CTL registers

On Thu, Mar 22, 2012 at 09:18:32AM -0300, Eugeni Dodonov wrote: > On Thu, Mar 22, 2012 at 07:43, Chris Wilson wrote: > > > On Wed, 21 Mar 2012 22:09:42 -0300, Eugeni Dodonov < > > eugeni.dodo...@intel.com> wrote: > > > This is one set of those registers for each pipe. > > > Would these not benefit

Re: [Intel-gfx] [PATCH 07/37] drm/i915: add DP_TP_CTL registers

On Thu, Mar 22, 2012 at 07:43, Chris Wilson wrote: > On Wed, 21 Mar 2012 22:09:42 -0300, Eugeni Dodonov < > eugeni.dodo...@intel.com> wrote: > > This is one set of those registers for each pipe. > Would these not benefit from a #define DP_TP_CTL(pipe)? > Sorry, my typo went in - there is one set

Re: [Intel-gfx] [PATCH 26/37] drm/i915: reuse Ivybridge interrupts code for Haswell

On Thu, Mar 22, 2012 at 07:22, Daniel Vetter wrote: > On Wed, Mar 21, 2012 at 10:10:01PM -0300, Eugeni Dodonov wrote: > > Signed-off-by: Eugeni Dodonov > > Hm, I have a feeling that some of these s/IS_IVB/IS_GEN7/ checks will > collide with the vlv code. I guess neither Jesse nor you have tried

Re: [Intel-gfx] [PATCH 23/37] drm/i915: do not set 6BPP dithering on haswell

On Thu, Mar 22, 2012 at 07:16, Daniel Vetter wrote: > On Wed, Mar 21, 2012 at 10:09:58PM -0300, Eugeni Dodonov wrote: > > We don't have those bits on Haswell anymore, so do not set them. > > > > Signed-off-by: Eugeni Dodonov > > Hm, how is 6bpp dithering supposed to work now, when e.g. a lame dp

Re: [Intel-gfx] [PATCH 37/37] drm/i915: dump registers read/write ops

On Wed, 21 Mar 2012 22:10:12 -0300, Eugeni Dodonov wrote: > This logs all the registers and SBI accesses as they happen. > > Note that it is not supposed to go into the final patch series. But there > are too many subtle changes in both HSW and LPT that are much easier to > spot with this extra

Re: [Intel-gfx] [PATCH 21/37] drm/i915: calculate watermarks on Gen7 archs in one place

On Thu, Mar 22, 2012 at 10:52:50AM +, Chris Wilson wrote: > On Wed, 21 Mar 2012 22:09:56 -0300, Eugeni Dodonov > wrote: > > Signed-off-by: Eugeni Dodonov > > --- > > drivers/gpu/drm/i915/intel_display.c |2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drive

Re: [Intel-gfx] [PATCH 31/37] drm/i915: enable PCH earlier

On Wed, 21 Mar 2012 22:10:06 -0300, Eugeni Dodonov wrote: > The modesetting sequence for PCH-related connections mentions that the > order of plane/pipe enablement could happen either before of after PCH > enablement. > > With LPT, however, we need to enable some things earlier to be able to > t

Re: [Intel-gfx] [PATCH 29/37] drm/i915: enable power wells on haswell init

On Wed, 21 Mar 2012 22:10:04 -0300, Eugeni Dodonov wrote: > This attempts to enable all the available power wells during the > initialization. > > Signed-off-by: Eugeni Dodonov > --- > drivers/gpu/drm/i915/intel_display.c | 31 +++ > 1 file changed, 31 insertions(

Re: [Intel-gfx] [PATCH 22/37] drm/i915: program WM_LINETIME on Haswell

On Wed, 21 Mar 2012 22:09:57 -0300, Eugeni Dodonov wrote: > The line time can be programmed according to the number of horizontal > pixels vs effective pixel rate ratio. > > Signed-off-by: Eugeni Dodonov > --- > drivers/gpu/drm/i915/intel_display.c | 11 +++ > 1 file changed, 11 inse

Re: [Intel-gfx] [PATCH 21/37] drm/i915: calculate watermarks on Gen7 archs in one place

On Wed, 21 Mar 2012 22:09:56 -0300, Eugeni Dodonov wrote: > Signed-off-by: Eugeni Dodonov > --- > drivers/gpu/drm/i915/intel_display.c |2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > in

Re: [Intel-gfx] [PATCH 18/37] drm/i915: add GTC registers

On Wed, 21 Mar 2012 22:09:53 -0300, Eugeni Dodonov wrote: > Add Global Time Clock registers Interesting; driven by what? Is it coupled to the EU? Will it fail along with the GPU or is an external source? -Chris -- Chris Wilson, Intel Open Source Technology Centre __

Re: [Intel-gfx] [PATCH 13/37] drm/i915: add support for SBI ops

On Wed, 21 Mar 2012 22:09:48 -0300, Eugeni Dodonov wrote: > With Lynx Point, we need to use SBI to communicate with the display clock > control. This commit adds helper functions to access the registers via > SBI. > > Signed-off-by: Eugeni Dodonov > --- > drivers/gpu/drm/i915/intel_display.c |

Re: [Intel-gfx] [RFC] [PATCH 00/38] Haswell

On Wed, Mar 21, 2012 at 10:09:35PM -0300, Eugeni Dodonov wrote: > Hi folks, > > To contribute to everyones curiosity and further enrich Phoronix articles > :), this is the initial Haswell enablement patchset for basic modesetting > support over VGA. > > This is actually the first time I am doing

Re: [Intel-gfx] [PATCH 08/37] drm/i915: add DP_TP_STATUS registers

On Wed, 21 Mar 2012 22:09:43 -0300, Eugeni Dodonov wrote: > There is one set of those registers for each port. Looks like we need an enum port in addition to enum plane and enum pipe. And a _PORT() switcher. The idea behind having separate PIPE, PLANE, PORT macros was that eventually we would pu

Re: [Intel-gfx] [PATCH 07/37] drm/i915: add DP_TP_CTL registers

On Wed, 21 Mar 2012 22:09:42 -0300, Eugeni Dodonov wrote: > This is one set of those registers for each pipe. > > Signed-off-by: Eugeni Dodonov > --- > drivers/gpu/drm/i915/i915_reg.h | 16 > 1 file changed, 16 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h

Re: [Intel-gfx] [PATCH 35/37] drm/i915: program iCLKIP on Lynx Point

On Wed, Mar 21, 2012 at 10:10:10PM -0300, Eugeni Dodonov wrote: > The iCLKIP clock is used to drive the VGA pixel clock on the PCH. In order > to do so, it must be programmed to properly do the clock ticks according > to the divisor, phase direction, phase increments and a special auxiliary > divis

Re: [Intel-gfx] [PATCH 26/37] drm/i915: reuse Ivybridge interrupts code for Haswell

On Wed, Mar 21, 2012 at 10:10:01PM -0300, Eugeni Dodonov wrote: > Signed-off-by: Eugeni Dodonov Hm, I have a feeling that some of these s/IS_IVB/IS_GEN7/ checks will collide with the vlv code. I guess neither Jesse nor you have tried to merge in each another's branch yet. This will be fun to sort

Re: [Intel-gfx] [PATCH 23/37] drm/i915: do not set 6BPP dithering on haswell

On Wed, Mar 21, 2012 at 10:09:58PM -0300, Eugeni Dodonov wrote: > We don't have those bits on Haswell anymore, so do not set them. > > Signed-off-by: Eugeni Dodonov Hm, how is 6bpp dithering supposed to work now, when e.g. a lame dp link can't handle more due to bandwidth issues? -Daniel > ---

Re: [Intel-gfx] [PATCH 13/37] drm/i915: add support for SBI ops

On Wed, Mar 21, 2012 at 10:09:48PM -0300, Eugeni Dodonov wrote: > With Lynx Point, we need to use SBI to communicate with the display clock > control. This commit adds helper functions to access the registers via > SBI. > > Signed-off-by: Eugeni Dodonov Does this sbi stuff on hsw have anything t

Re: [Intel-gfx] [PATCH 03/37] drm/i915: add HAS_PLL_SPLIT macro

On Wed, Mar 21, 2012 at 10:09:38PM -0300, Eugeni Dodonov wrote: > Ivy Bridge is the only GPU which has split 3-display support over 2 PLLs. > > Signed-off-by: Eugeni Dodonov This is imo a strange name for '3 pipes but just 2 plls' hw. And I couldn't find any usage of this in your series, so I do

Re: [Intel-gfx] [PATCH 04/37] drm/i915: add haswell into the PCH SPLIT company

On Wed, Mar 21, 2012 at 10:09:39PM -0300, Eugeni Dodonov wrote: > Haswell is similar to Ivy Bridge in this sense. > > Signed-off-by: Eugeni Dodonov Given that vlv is gen7, too, but not pch_split, I think it's time to promote this into a feature flag. We use this at tons of places, so the added i

Re: [Intel-gfx] [PATCH 01/37] drm/i915: add Haswell devices and their PCI IDs

On Wed, Mar 21, 2012 at 10:09:36PM -0300, Eugeni Dodonov wrote: > This adds product definitions for desktop, mobile and server boards. > > Signed-off-by: Eugeni Dodonov Like in the vlv series we need to split this into a second patch, which just adds the pci ids to the tables, and which will get

Re: [Intel-gfx] [PATCH 2/2] drm/i915: use semaphores for the display plane

On Wed, 21 Mar 2012 17:19:13 -0700, Ben Widawsky wrote: > In theory this will have performance and power improvements. Performance > because we don't need to stall when the scanout BO is busy, and power > because we don't have to stall when the BO is busy ie. we can get the > work done sooner and

Re: [Intel-gfx] [PATCH 1/2] drm/i915: extract ring sync code

On Wed, 21 Mar 2012 17:19:12 -0700, Ben Widawsky wrote: > We want to use this function elsewhere... > > Signed-off-by: Ben Widawsky > --- > drivers/gpu/drm/i915/i915_drv.h| 19 + > drivers/gpu/drm/i915/i915_gem.c| 43 > drivers/gpu/drm/i9